summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/r8a7792.dtsi
AgeCommit message (Expand)AuthorFilesLines
2016-09-05ARM: dts: r8a7792: add QSPI supportSergei Shtylyov1-0/+16
2016-09-05ARM: dts: r8a7792: add QSPI clockSergei Shtylyov1-2/+5
2016-08-23ARM: dts: r8a7792: add VSP1V supportSergei Shtylyov1-0/+24
2016-08-23ARM: dts: r8a7792: add VSP1V clocksSergei Shtylyov1-3/+8
2016-08-09ARM: dts: r8a7792: add DU supportSergei Shtylyov1-0/+28
2016-08-09ARM: dts: r8a7792: add DU clocksSergei Shtylyov1-2/+11
2016-08-09ARM: dts: r8a7792: fix misindented lineSergei Shtylyov1-1/+1
2016-08-09ARM: dts: r8a7792: add VIN supportSergei Shtylyov1-0/+66
2016-08-09ARM: dts: r8a7792: add VIN clocksSergei Shtylyov1-3/+17
2016-08-09ARM: dts: r8a7792: add I2C supportSergei Shtylyov1-0/+82
2016-08-09ARM: dts: r8a7792: add I2C clocksSergei Shtylyov1-2/+7
2016-08-09ARM: dts: r8a7792: add SDHI supportSergei Shtylyov1-0/+12
2016-08-09ARM: dts: r8a7792: add SD clocksSergei Shtylyov1-0/+16
2016-08-08ARM: dts: r8a7792: add CAN supportSergei Shtylyov1-0/+24
2016-08-08ARM: dts: r8a7792: add CAN clocksSergei Shtylyov1-2/+20
2016-08-08ARM: dts: r8a7792: add EtherAVB supportSergei Shtylyov1-0/+12
2016-08-08ARM: dts: r8a7792: add EtherAVB clocksSergei Shtylyov1-0/+16
2016-08-08ARM: dts: r8a7792: add GPIO supportSergei Shtylyov1-0/+168
2016-08-08ARM: dts: r8a7792: add GPIO clocksSergei Shtylyov1-0/+21
2016-08-08ARM: dts: r8a7792: add PFC supportSergei Shtylyov1-0/+5
2016-07-15ARM: dts: r8a7792: remove ADSP clockSergei Shtylyov1-1/+1
2016-07-15ARM: dts: r8a7792: add PLL1 divided by 2 clockSergei Shtylyov1-0/+7
2016-06-30ARM: dts: r8a7792: add SMP supportSergei Shtylyov1-0/+16
2016-06-24ARM: dts: r8a7792: add JPU supportSergei Shtylyov1-0/+9
2016-06-24ARM: dts: r8a7792: add JPU clocksSergei Shtylyov1-0/+16
2016-06-16ARM: dts: r8a7792: add IRQC supportSergei Shtylyov1-0/+13
2016-06-16ARM: dts: r8a7792: add [H]SCIF supportSergei Shtylyov1-0/+90
2016-06-16ARM: dts: r8a7792: add SYS-DMAC supportSergei Shtylyov1-0/+64
2016-06-16ARM: dts: r8a7792: initial SoC device treeSergei Shtylyov1-0/+170