Age | Commit message (Collapse) | Author | Files | Lines |
|
This adds the PTP timesource to the IXP45x and IXP46x
platforms.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
Replace the "simple-bus" simplification by the proper bus for
IXP4xx memory or device expansion.
Use chip-select addressing with two address cells on all the
flashes mounted on the IXP4xx devices. This includes all flash
chips.
Change the unit-name from @50000000 to @c4000000 as the DTS
validation screams. The registers for controlling the bus are
at c4000000 but the actual memory windows and ranges are at
50000000. Well it is just syntax, we can live with it.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
All of IXP4xx SoCs has an EthA at 0xc800c000 so move this
from the IXP[56]x to the IXP4xx DTSI.
Then add the second ethernet port on the Cambria GW2358-4
on EthA.
Reported-by: Zoltan HERPAI <wigyori@uid0.hu>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
This adds ethernet to the IXP4xx device trees.
Cc: Zoltan HERPAI <wigyori@uid0.hu>
Cc: Raylynn Knight <rayknight@me.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
This adds a device tree for the IXP4xx-based Linksys
NSLU2 and Gateworks GW2358 which encompass the Gateworks
Cambria family.
These will be the first IXP4xx device tree platforms.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|