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path: root/arch/arm/boot/dts/berlin2q.dtsi
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2014-11-18ARM: dts: berlin: add BG2Q nodes for USB supportAntoine Tenart1-0/+54
Adds nodes describing the Marvell Berlin BG2Q USB PHY and USB. The BG2Q SoC has 3 USB host controller, compatible with ChipIdea. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-10-29ARM: dts: berlin: Add phy-connection-type to BG2Q EthernetAntoine Ténart1-0/+1
Internal FastEthernet PHY on BG2Q is connected via MII, add a corresponding phy-connection-type property to the Ethernet node. Tested-by: Antoine Ténart <antoine.tenart@free-electrons.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-10-29ARM: dts: berlin: enable timer 1 for sched_clockAntoine Ténart1-1/+0
Enable timer 1 to be the source for the sched_clock, allowing to have a more precise value than 1/HZ. Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-10-29ARM: dts: berlin: add a required reset property in the chip controller nodeAntoine Ténart1-0/+1
The chip controller node now also describes the Marvell Berlin reset controller. Add the required 'reset-cells' property. Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-10-29ARM: dts: berlin: add the AHCI node for the BG2QAntoine Ténart1-0/+39
The BG2Q has an AHCI SATA controller. Add the corresponding nodes (AHCI, PHY) into its device tree. Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-10-01ARM: dts: berlin: add the Ethernet nodeAntoine Ténart1-0/+17
This patch adds the Ethernet node, enabling the network unit on Berlin BG2Q SoCs. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: David S. Miller <davem@davemloft.net>
2014-06-16ARM: dts: berlin: add SMP related nodes and properties for BG2QAntoine Ténart1-0/+6
Add required nodes and properties into the Berlin BG2Q device tree to take advantage of the newly introduced SMP support. Add the scu and cpu-ctrl nodes along with the CPUs enable-method property. Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-06-16ARM: dts: berlin: add I2C nodes for BG2QAntoine Ténart1-0/+72
The Marvell Berlin BG2Q has 4 TWSI compatible with the Synopsys DesignWare I2C driver. Add the corresponding nodes. The pin-muxing setup is also done here, since there cannot be another muxing setup if I2C{0,1,2,3} are enabled. Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-06-16ARM: dts: berlin2q: set L2CC tag and data latency to 2 cyclesJisheng Zhang1-0/+2
For all BG2Q SoCs, 2 cycles is the best/correct value. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-05-20ARM: dts: berlin: add the SDHCI nodes for the BG2QAntoine Tenart1-0/+24
Add the SDHCI nodes for the Marvell Berlin BG2Q, using the mrvl,pxav3-mmc driver. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-05-20ARM: dts: berlin: add the pinctrl node and muxing setup for uartsAntoine Tenart1-0/+19
Add pinctrl bindings and system control nodes to what we currently know about Berlin SoCs. Where available, also set default pinctrl property for uarts, when there is only one pinmux option for it. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-05-20ARM: dts: berlin: convert BG2Q to DT clock nodesAlexandre Belloni1-35/+19
This converts Berlin BG2Q SoC dtsi to make use of the new DT clock nodes for Berlin SoCs. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-05-20ARM: dts: berlin: add the BG2Q GPIO nodesAntoine Tenart1-0/+102
The Marvell Berlin BG2Q has 6 GPIO ports compatible with the snps,dw-apb-gpio driver. This patch adds the corresponding device tree nodes. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Reviewed-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-05-20ARM: dts: berlin: add scu and chipctrl device nodes for BG2/BG2QSebastian Hesselbarth1-0/+10
This adds scu and general purpose registers device nodes required for SMP on Berlin BG2 and BG2Q SoCs. The secondary CPUs will pick their jump address from general purpose (SW generic) register 1. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Jisheng Zhang <jszhang@marvell.com> Tested-by: Antoine Tenart <antoine.tenart@free-electrons.com>
2014-05-20ARM: dts: berlin: add the Marvell Armada 1500 proAntoine Tenart1-0/+224
Adds initial support for the Marvell Armada 1500 pro (BG2Q) SoC (Berlin family). The SoC has nodes for cpu, l2 cache controller, interrupt controllers, local timer, apb timers and uarts for now. Also add corresponding binding documentation. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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