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2025-05-14dt-bindings: mmc: marvell,xenon-sdhci: Allow "dma-coherent" and "iommus"Rob Herring (Arm)1-0/+5
The Marvell xenon-sdhci block can be cache-coherent and needs the "dma-coherent" property. It can also be behind an IOMMU and needs the "iommus" property. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250320-dt-marvell-mmc-v1-1-e51002ea0238@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-05-14dt-bindings: mmc: Remove redundant sdhci.txtRob Herring (Arm)1-13/+0
The properties in sdhci.txt are documented in sdhci-common.yaml, too. Remove the txt binding. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250320211922.1135669-1-robh@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-05-14dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCsFabrizio Castro1-19/+82
Document the Renesas RZ/V2H(P) family of SoCs DMAC block. The Renesas RZ/V2H(P) DMAC is very similar to the one found on the Renesas RZ/G2L family of SoCs, but there are some differences: * It only uses one register area * It only uses one clock * It only uses one reset * Instead of using MID/IRD it uses REQ No * It is connected to the Interrupt Control Unit (ICU) Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250423143422.3747702-3-fabrizio.castro.jz@renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: dma: rz-dmac: Restrict properties for RZ/A1HFabrizio Castro1-0/+8
Make sure we don't allow for the clocks, clock-names, resets, reset-names. and power-domains properties for the Renesas RZ/A1H SoC because its DMAC doesn't have clocks, resets, and power domains. Fixes: 209efec19c4c ("dt-bindings: dma: rz-dmac: Document RZ/A1H SoC") Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20250423143422.3747702-2-fabrizio.castro.jz@renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: Document Tegra264 ADMA supportSheetal1-0/+2
Add Tegra264 ADMA support to the device tree bindings documentation. The Tegra264 ADMA hardware supports 64 DMA channels and requires specific register configurations. Signed-off-by: Sheetal <sheetal@nvidia.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250512050010.1025259-2-sheetal@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14ASoC: dt-bindings: mediatek: Simplify mediatek,clk-providerKrzysztof Kozlowski2-8/+6
"mediatek,clk-provider" property is a string, not an string array, thus "items" is not really correct. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20250514105702.28622-2-krzysztof.kozlowski@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-14regulator: dt-bindings: mt6357: Drop fixed compatible requirementNícolas F. R. A. Prado1-11/+1
Some of the regulators on the MT6357 PMIC currently reference the fixed-regulator dt-binding, which enforces the presence of a regulator-fixed compatible. However since all regulators on the MT6357 PMIC are handled by a single mt6357-regulator driver, probed through MFD, the compatibles don't serve any purpose. In fact they cause failures in the DT kselftest since they aren't probed by the fixed regulator driver as would be expected. Furthermore this is the only dt-binding in this family like this: mt6359-regulator and mt6358-regulator don't require those compatibles. Commit d77e89b7b03f ("arm64: dts: mediatek: mt6357: Drop regulator-fixed compatibles") removed the compatibles from Devicetree, but missed updating the binding, which still requires them, introducing dt-binding errors. Remove the compatible requirement by referencing the plain regulator dt-binding instead to fix the dt-binding errors. Fixes: d77e89b7b03f ("arm64: dts: mediatek: mt6357: Drop regulator-fixed compatibles") Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://patch.msgid.link/20250514-mt6357-regulator-fixed-compatibles-removal-bindings-v1-1-2421e9cc6cc7@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-14dt-bindings: phy: rockchip,inno-usb2phy: add rk3562Kever Yang1-0/+2
Add compatible for the USB2 phy in the Rockchip RK3562 SoC. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250415050005.52773-1-kever.yang@rock-chips.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: phy: rockchip,inno-usb2phy: add rk3036 compatibleHeiko Stuebner1-0/+2
Add compatible for the USB2 phy in the Rockchip RK3036 SoC. Apart from some bits that got swapped around in the phy registers, the block is nearly the same as the one on the rk3128. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250503201512.991277-2-heiko@sntech.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: phy: renesas,usb2-phy: Document RZ/V2H(P) SoCLad Prabhakar1-1/+4
Document USB2.0 phy bindings for RZ/V2H(P) ("R9A09gG57") SoC. RZ/V2H(P) USB2.0 phy is similar to one found on the RZ/G2L SoC, but it needs additional configuration to be done as compared RZ/G2L USB2.0 phy. To handle this difference a SoC specific compat string is added for RZ/V2H(P) SoC. Like the RZ/G2L SoC, the RZ/V2H(P) USB2.0 PHY requires the `resets` property and has two clocks. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414145729.343133-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: phy: renesas,usb2-phy: Add clock constraint for RZ/G2L familyLad Prabhakar1-0/+3
The RZ/G2L family requires two clocks for USB2 PHY, which are already defined in the DTSI files. Add a constraint in the DT binding document to ensure validation with `dtbs_check`. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414145729.343133-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: phy: samsung,usb3-drd-phy: add exynos2200 supportIvaylo Ivanov1-4/+34
Document support for Exynos2200. As the USBDRD 3.2 4nm controller consists of Synopsys eUSB2.0 phy and USBDP/SS combophy, which will be handled by external drivers, define only the bus clocked used by the link controller. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250504144527.1723980-3-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: phy: add exynos2200 eusb2 phy supportIvaylo Ivanov1-0/+80
Document the exynos2200 eUSB2 compatible. Unlike the currently documented Qualcomm SoCs, the driver doesn't make use of reset lines for reset control and uses more clocks. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250504144527.1723980-2-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: phy: rockchip: Convert RK3399 PCIe PHY to schemaRob Herring (Arm)3-38/+56
Convert the Rockchip RK3399 PCIe PHY to DT schema format. Move the example to the GRF binding as that has the complete block. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250415011824.2320039-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: phy: imx8mq-usb: add imx95 tuning supportXu Yang1-3/+31
The parameter value of below 3 properties are USB PHY specific. i.MX8MP and i.MX95 USB PHY has different meanings. This will enlarge parameters value and add constraints for them. - fsl,phy-tx-vref-tune-percent - fsl,phy-tx-rise-tune-percent - fsl,phy-comp-dis-tune-percent Reviewed-by: Jun Li <jun.li@nxp.com> Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250430094502.2723983-2-xu.yang_2@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: phy: imx8mq-usb: fix fsl,phy-tx-vboost-level-microvolt propertyXu Yang1-2/+1
The ticket TKT0676370 shows the description of TX_VBOOST_LVL is wrong in register PHY_CTRL3 bit[31:29]. 011: Corresponds to a launch amplitude of 1.12 V. 010: Corresponds to a launch amplitude of 1.04 V. 000: Corresponds to a launch amplitude of 0.88 V. After updated: 011: Corresponds to a launch amplitude of 0.844 V. 100: Corresponds to a launch amplitude of 1.008 V. 101: Corresponds to a launch amplitude of 1.156 V. This will correct it accordingly. Fixes: b2e75563dc39 ("dt-bindings: phy: imx8mq-usb: add phy tuning properties") Cc: stable@vger.kernel.org Reviewed-by: Jun Li <jun.li@nxp.com> Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250430094502.2723983-1-xu.yang_2@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14ASoC: dt-bindings: Add Everest ES8389 audio CODECZhang Yi1-0/+50
Add device tree binding documentation for Everest ES8389 which is different from ES8388 Signed-off-by: Zhang Yi <zhangyi@everest-semi.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20250514094546.35508-3-zhangyi@everest-semi.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-14dt-bindings: phy: mediatek,tphy: Add support for MT6893AngeloGioacchino Del Regno1-0/+1
Add a compatible string for the MediaTek Dimensity 1200 (MT6893) SoC: this chip integrates a MediaTek generic T-PHY version 2. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250416120220.147798-2-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: phy: mediatek,dsi-phy: Add support for MT6893AngeloGioacchino Del Regno1-0/+1
Add support for the MediaTek Dimensity 1200 (MT6893) SoC: the DSI PHY found in this chip is fully compatible with the one found in the MT8183 SoC. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250416120220.147798-1-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: arm: stm32: Document Ultratronik's Fly board DT bindingGoran Rađenović1-0/+5
This commit documents ultra-fly-sbc devicetree binding based on STM32MP157 SoC. Signed-off-by: Goran Rađenović <goran.radni@gmail.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250508143818.2574558-3-goran.radni@gmail.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14dt-bindings: vendor-prefixes: Add UltratronikGoran Rađenović1-0/+2
Ultratronik GmbH is a German electronics company: https://www.ultratronik-ems.de/ Signed-off-by: Goran Rađenović <goran.radni@gmail.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250508143818.2574558-2-goran.radni@gmail.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14dt-bindings: arm: stm32: add compatible for stm32h747i-disco boardDario Binacchi1-0/+4
The board includes an STM32H747XI SoC with the following resources: - 2 Mbytes Flash - 1 MByte SRAM - LCD-TFT controller - MIPI-DSI interface - FD-CAN - USB 2.0 high-speed/full-speed - Ethernet MAC - camera interface Detailed information can be found at: https://www.st.com/en/evaluation-tools/stm32h747i-disco.html Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250427074404.3278732-3-dario.binacchi@amarulasolutions.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14dt-bindings: phy: rockchip: Convert RK3399 Type-C PHY to schemaRob Herring (Arm)3-85/+117
Convert the Rockchip RK3399 Type-C PHY to DT schema format. Add the missing "power-domains" property and "port" and "orientation-switch" properties in the child nodes. Omit the previously deprecated properties as they aren't used anywhere. Drop the 2nd example which was pretty much identical to the 1st example. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250416202419.3836688-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: phy: cadence-torrent: enable PHY_TYPE_USXGMIISiddharth Vadapalli1-2/+1
The Cadence Torrent SERDES supports USXGMII protocol. Hence, update the bindings to allow PHY_TYPE_USXGMII. Since PHY_TYPE_USXGMII has the value of "12" while the existing maximum allowed PHY TYPE is "9", switch back to using "enum" property in the bindings to account for this discontinuity. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250411055743.623135-1-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: phy: mtk-xs-phy: support type switch by pericfgFrank Wunderlich1-0/+15
Add support for type switch by pericfg register between USB3/PCIe. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250422132438.15735-5-linux@fw-web.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: phy: mtk-xs-phy: Add mt7988 compatibleFrank Wunderlich1-0/+1
Add compatible for xs-phy on mt7988. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250422132438.15735-4-linux@fw-web.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14dt-bindings: ata: Convert ti,dm816-ahci to DT schemaRob Herring (Arm)2-21/+43
Convert the TI DM816 AHCI SATA Controller to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
2025-05-14dt-bindings: display: imx: Add i.MX8qxp Display ControllerLiu Ying1-0/+236
i.MX8qxp Display Controller(DC) is comprised of three main components that include a blit engine for 2D graphics accelerations, display controller for display output processing, as well as a command sequencer. Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414035028.1561475-9-victor.liu@nxp.com
2025-05-14dt-bindings: interrupt-controller: Add i.MX8qxp Display Controller interrupt ↵Liu Ying1-0/+318
controller i.MX8qxp Display Controller has a built-in interrupt controller to support Enable/Status/Preset/Clear interrupt bit. Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414035028.1561475-8-victor.liu@nxp.com
2025-05-14dt-bindings: display: imx: Add i.MX8qxp Display Controller command sequencerLiu Ying1-0/+67
i.MX8qxp Display Controller contains a command sequencer is designed to autonomously process command lists. Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414035028.1561475-7-victor.liu@nxp.com
2025-05-14dt-bindings: display: imx: Add i.MX8qxp Display Controller AXI performance ↵Liu Ying1-0/+57
counter i.MX8qxp Display Controller contains a AXI performance counter which allows measurement of average bandwidth and latency during operation. Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414035028.1561475-6-victor.liu@nxp.com
2025-05-14dt-bindings: display: imx: Add i.MX8qxp Display Controller pixel engineLiu Ying1-0/+250
i.MX8qxp Display Controller pixel engine consists of all processing units that operate in the AXI bus clock domain. Command sequencer and interrupt controller of the Display Controller work with AXI bus clock, but they are not in pixel engine. Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414035028.1561475-5-victor.liu@nxp.com
2025-05-14dt-bindings: display: imx: Add i.MX8qxp Display Controller display engineLiu Ying1-0/+152
i.MX8qxp Display Controller display engine consists of all processing units that operate in a display clock domain. Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414035028.1561475-4-victor.liu@nxp.com
2025-05-14dt-bindings: display: imx: Add i.MX8qxp Display Controller blit engineLiu Ying1-0/+204
i.MX8qxp Display Controller contains a blit engine for raster graphics. It may read up to 3 source images from memory and computes one destination image from it, which is written back to memory. Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414035028.1561475-3-victor.liu@nxp.com
2025-05-14dt-bindings: display: imx: Add i.MX8qxp Display Controller processing unitsLiu Ying17-0/+963
Freescale i.MX8qxp Display Controller is implemented as construction set of building blocks with unified concept and standardized interfaces. Document all existing processing units. Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414035028.1561475-2-victor.liu@nxp.com
2025-05-14dt-bindings: trivial-devices: Add Maxim max30208Rodrigo Gobbi1-0/+2
The temperature sensor for maxim is a simple i2c driver, it's eligible to trivial devices. Signed-off-by: Rodrigo Gobbi <rodrigo.gobbi.7@gmail.com> Link: https://lore.kernel.org/r/20250503190509.33074-1-rodrigo.gobbi.7@gmail.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-05-14dt-bindings: soc: fsl,qman-fqd: Fix reserved-memory.yaml referenceRob Herring (Arm)1-2/+2
The reserved-memory.yaml reference needs the full path. No warnings were generated because the example has the wrong compatible string, so fix that too. Fixes: 304a90c4f75d ("dt-bindings: soc: fsl: Convert q(b)man-* to yaml format") Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250507154231.1590634-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-05-14dt-bindings: interrupt-controller: Convert ti,omap-intc-irq to DT schemaRob Herring (Arm)3-55/+52
Convert the TI OMAP2/3 interrupt controller binding to schema format. It's a straight-forward conversion of the typical interrupt controller. "ti,intc-size" property isn't actually used with "ti,omap2-intc", so the 2 bindings can be combined. Link: https://lore.kernel.org/r/20250505144917.1294150-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-05-14dt-bindings: interrupt-controller: Convert ti,omap4-wugen-mpu to DT schemaRob Herring (Arm)2-31/+55
Convert the TI Wakeup Generator interrupt controller binding to schema format. It's a straight-forward conversion of the typical interrupt controller. Link: https://lore.kernel.org/r/20250505144913.1293967-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-05-14dt-bindings: interrupt-controller: Convert ti,keystone-irq to DT schemaRob Herring (Arm)2-36/+63
Convert the TI Keystone 2 interrupt controller binding to schema format. It's a straight-forward conversion of the typical interrupt controller. Link: https://lore.kernel.org/r/20250505144908.1293785-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-05-14dt-bindings: interrupt-controller: Convert technologic,ts4800-irqc to DT schemaRob Herring (Arm)2-14/+49
Convert the TS-4800 FPGA interrupt controller binding to schema format. It's a straight-forward conversion of the typical interrupt controller. Link: https://lore.kernel.org/r/20250505144856.1293370-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-05-14dt-bindings: interrupt-controller: Convert st,spear3xx-shirq to DT schemaRob Herring (Arm)2-44/+67
Convert the SPEAr3xx Shared interrupt controller binding to schema format. It's a straight-forward conversion of the typical interrupt controller. Link: https://lore.kernel.org/r/20250505144851.1293180-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-05-14dt-bindings: interrupt-controller: Convert snps,dw-apb-ictl to DT schemaRob Herring (Arm)2-43/+64
Convert the Synopsys DW-APB interrupt controller binding to schema format. It's a straight-forward conversion of the typical interrupt controller. Link: https://lore.kernel.org/r/20250505144842.1292840-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-05-14dt-bindings: interrupt-controller: Convert snps,archs-intc to DT schemaRob Herring (Arm)2-22/+48
Convert the ARC-HS incore interrupt controller binding to schema format. It's a straight-forward conversion of the typical interrupt controller. Link: https://lore.kernel.org/r/20250505144834.1292666-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-05-14dt-bindings: interrupt-controller: Convert snps,archs-idu-intc to DT schemaRob Herring (Arm)2-46/+48
Convert the ARC-HS Interrupt Distribution Unit interrupt controller binding to schema format. It's a straight-forward conversion of the typical interrupt controller. Link: https://lore.kernel.org/r/20250505144830.1292495-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-05-14dt-bindings: interrupt-controller: Convert snps,arc700-intc to DT schemaRob Herring (Arm)2-24/+42
Convert the Arc Core interrupt controller binding to schema format. It's a straight-forward conversion of the typical interrupt controller. Link: https://lore.kernel.org/r/20250505144826.1292329-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-05-14dt-bindings: interrupt-controller: Convert qca,ar7100-misc-intc to DT schemaRob Herring (Arm)2-45/+52
Convert the Qualcomm Atheros ath79 Misc interrupt controller binding to schema format. Adjust the compatible values to match what's actually in use. Link: https://lore.kernel.org/r/20250505144821.1292151-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-05-14dt-bindings: interrupt-controller: Convert qca,ar7100-cpu-intc to DT schemaRob Herring (Arm)2-44/+61
Convert the Qualcomm Atheros ath79 CPU interrupt controller binding to schema format. Link: https://lore.kernel.org/r/20250505144817.1291980-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-05-14dt-bindings: interrupt-controller: Convert marvell,odmi-controller to DT schemaRob Herring (Arm)2-42/+54
Convert the Marvell On-Die Message interrupt controller binding to schema format. Drop the 'interrupt-controller' property which isn't relevant for an MSI controller. Link: https://lore.kernel.org/r/20250505144727.1290271-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-05-14dt-bindings: interrupt-controller: Convert marvell,cp110-icu to DT schemaRob Herring (Arm)2-112/+98
Convert the Marvell ICU interrupt controller to DT schema format. Add the missing addressing properties to read and translate child node addresses. Drop the legacy binding description and example. Link: https://lore.kernel.org/r/20250505144524.1285795-1-robh@kernel.org Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2026-05-26 19:49:44 +0300