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2025-09-01dt-bindings: display: sitronix,st7567: add optional inverted propertyMarcus Folkesson1-0/+5
Depending on which display that is connected to the controller, an "1" means either a black or a white pixel. The supported format (R1) expects the pixels to map against: 0 => Black 1 => White If this is not what the display map against, the controller has support to invert these values. Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Link: https://lore.kernel.org/r/20250721-st7571-format-v2-3-159f4134098c@gmail.com Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
2025-09-01dt-bindings: display: sitronix,st7571: add optional inverted propertyMarcus Folkesson1-0/+5
Depending on which display that is connected to the controller, an "1" means either a black or a white pixel. The supported formats (R1/R2/XRGB8888) expects the pixels to map against (4bit): 00 => Black 01 => Dark Gray 10 => Light Gray 11 => White If this is not what the display map against, the controller has support to invert these values. Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250721-st7571-format-v2-2-159f4134098c@gmail.com Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
2025-09-01dt-bindings: lpspi: Document support for S32GLarisa Grigore1-0/+5
Add compatible strings 'nxp,s32g2-lpspi' and 'nxp,s32g3-lpspi' for S32G2 and S32G3. Require nxp,s32g3-lpspi to fallback to nxp,s32g2-lpspi since they are currently compatible. Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: James Clark <james.clark@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20250828-james-nxp-lpspi-v2-5-6262b9aa9be4@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-01dt-bindings: gpu: img,powervr-rogue: Add TH1520 GPU supportMichal Wilczynski1-8/+29
Rework the PowerVR Rogue GPU binding to use an explicit, per variant style for defining power domain properties and add support for the T-HEAD TH1520 SoC's GPU. To improve clarity and precision, the binding is refactored so that power domain items are listed explicitly for each variant [1]. The previous method relied on an implicit, positional mapping between the `power-domains` and `power-domain-names` properties. This change replaces the generic rules with self contained if/then blocks for each GPU variant, making the relationship between power domains and their names explicit and unambiguous. The generic if block for img,img-rogue, which previously required power-domains and power-domain-names for all variants, is removed. Instead, each specific GPU variant now defines its own power domain requirements within a self-contained if/then block, making the schema more explicit. This new structure is then used to add support for the `thead,th1520-gpu`. While its BXM-4-64 IP has two conceptual power domains, the TH1520 SoC integrates them behind a single power gate. The new binding models this with a specific rule that enforces a single `power-domains` entry and disallows the `power-domain-names` property. Link: https://lore.kernel.org/all/4d79c8dd-c5fb-442c-ac65-37e7176b0cdd@linaro.org/ [1] Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Matt Coster <matt.coster@imgtec.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com> Link: https://lore.kernel.org/r/20250822-apr_14_for_sending-v13-2-af656f7cc6c3@samsung.com Signed-off-by: Matt Coster <matt.coster@imgtec.com>
2025-09-01Merge tag 'sti-dt-for-v6.18-round1' of ↵Arnd Bergmann1-4/+0
https://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti into soc/dt STi dt fixes: - Drop STiH407/10-B2120 DT boards and bindings. - Remove remaining STiH415/6 reference from STi machine. - Fix phy-names value for stih407-family.dtsi. * tag 'sti-dt-for-v6.18-round1' of https://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti: ARM: sti: drop B2120 board support ARM: sti: removal of stih415/stih416 related entries dt-bindings: arm: sti: drop B2120 board support ARM: dts: sti: rename SATA phy-names Link: https://lore.kernel.org/r/e4703e99-e44e-41d2-b744-a12ed4cb6692@foss.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-01Merge tag 'renesas-dts-for-v6.18-tag1' of ↵Arnd Bergmann1-0/+172
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt Renesas DTS updates for v6.18 - Add initial support for the RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs and their evaluation boards, - Add SPI support for the RZ/V2H SoC, - Add DMAC and I3C support for the RZ/G3E SoC, - Add I3C support for the RZ/G3S SoCs, - Miscellaneous fixes and improvements. * tag 'renesas-dts-for-v6.18-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (31 commits) arm64: dts: renesas: Minor whitespace cleanup arm64: dts: renesas: sparrow-hawk: Set VDDQ18_25_AVB voltage on EVTB1 arm64: dts: renesas: sparrow-hawk: Invert microSD voltage selector on EVTB1 arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Enable I2C0 and I2C1 support arm64: dts: renesas: r9a09g077: Add pinctrl node arm64: dts: renesas: r9a09g087: Add DT nodes for SCI channels 1-5 arm64: dts: renesas: r9a09g077: Add DT nodes for SCI channels 1-5 arm64: dts: renesas: r9a09g047: Add I3C node arm64: dts: renesas: r9a08g045: Add I3C node arm64: dts: renesas: sparrow-hawk: Update thermal trip points arm64: dts: renesas: rzg2: Increase CANFD clock rates arm64: dts: renesas: rcar-gen3: Increase CANFD clock rates ARM: dts: renesas: porter: Fix CAN pin group ARM: dts: renesas: r7s72100: Add boot phase tags arm64: dts: renesas: sparrow-hawk: Describe generic SPI NOR support arm64: dts: renesas: rzg2lc-smarc: Disable CAN-FD channel0 arm64: dts: renesas: r9a09g047: Add DMAC nodes arm64: dts: renesas: r9a09g057h48-kakip: Fix misplaced article arm64: dts: renesas: r9a09g087: Add SDHI nodes arm64: dts: renesas: r9a09g077: Add SDHI nodes ... Link: https://lore.kernel.org/r/cover.1756468048.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-01Merge tag 'ixp4xx-dts-v6.18' of ↵Arnd Bergmann2-0/+4
https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into soc/dt IXP4xx DTS updates for v6.18: Add the Actiontec router MI424WR A/C and D device trees. Prerequisite DT bindings have been merged in networking and GPIO git trees: https://lore.kernel.org/netdev/175106401649.2079310.16035106613106076029.git-patchwork-notify@kernel.org/ https://lore.kernel.org/linux-gpio/175614780274.8817.4717113656972710108.b4-ty@linaro.org/ * tag 'ixp4xx-dts-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator: ARM: dts: Add ixp4xx Actiontec MI424WR device trees dt-bindings: arm: ixp4xx: List actiontec devices dt-bindings: Add Actiontec vendor prefix Link: https://lore.kernel.org/r/CACRpkdZoDCXgsTGzUUWABbp_r1Xjv7vp7_NjEnEWzMmDQG+UJQ@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-01Merge tag 'aspeed-6.18-devicetree-0' of ↵Arnd Bergmann1-0/+3
https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt Early ASPEED devicetree updates for 6.18 Notable changes: - Meta's Wedge400 and Fuji boards have had parallel devicetrees added for a transition to a new static flash layout. The original layout is deprecated and I anticipate removing related devicetrees in future releases. New platforms: - Darwin (Meta) Darwin is Meta's rack switch platform with an AST2600 BMC integrated for health monitoring purpose. Updates and fixes: - GB200NVL (Nvidia): Networking, I2C, regulators, GPIOs - Wedge400, Fuji (Meta): Fix warnings from devicetree bindings - Use fixed-layout for NVMEM on Asrock platforms - Various: minor fixes for warnings from FSI devicetree bindings * tag 'aspeed-6.18-devicetree-0' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux: (24 commits) ARM: dts: aspeed: x570d4u: convert NVMEM content to layout syntax ARM: dts: aspeed: romed8hm3: convert NVMEM content to layout syntax ARM: dts: aspeed: e3c256d4i: convert NVMEM content to layout syntax ARM: dts: aspeed: e3c246d4i: convert NVMEM content to layout syntax ARM: dts: aspeed: Add missing "ibm,spi-fsi" compatibles ARM: dts: aspeed: Drop "fsi-master" compatibles ARM: dts: aspeed: Drop "no-gpio-delays" ARM: dts: aspeed: Add Facebook Darwin (AST2600) BMC dt-bindings: arm: aspeed: add Facebook Darwin board ARM: dts: aspeed: facebook-fuji: Include facebook-fuji-data64.dts ARM: dts: aspeed: Add Facebook Fuji-data64 (AST2600) Board dt-bindings: arm: aspeed: add Facebook Fuji-data64 board ARM: dts: aspeed: wedge400: Include wedge400-data64.dts ARM: dts: aspeed: Add Facebook Wedge400-data64 (AST2500) BMC dt-bindings: arm: aspeed: add Facebook Wedge400-data64 board ARM: dts: aspeed: Add facebook-bmc-flash-layout-128-data64.dtsi ARM: dts: aspeed: Move eMMC out of ast2600-facebook-netbmc-common.dtsi ARM: dts: aspeed: Fix DTB warnings in ast2600-facebook-netbmc-common.dtsi ARM: dts: aspeed: fuji: Fix DTB warnings ARM: dts: aspeed: wedge400: Fix DTB warnings ... Link: https://lore.kernel.org/r/cb634cffaf0db9d25fb3062f0eee41e03955321f.camel@codeconstruct.com.au Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-01dt-bindings: gpio: Add Tegra256 supportPrathamesh Shete1-0/+2
Extend the existing Tegra186 GPIO controller device tree bindings with support for the GPIO controller found on Tegra256. The number of pins is slightly different, but the programming model remains the same Add a new header, include/dt-bindings/gpio/tegra256-gpio.h, that defines port IDs as well as the TEGRA256_MAIN_GPIO() helper, both of which are used in conjunction to create a unique specifier for each pin. The OS can reconstruct the port ID and pin from these values to determine the register region for the corresponding GPIO. However, the OS does not use the macro definitions in this file. The symbolic names help associate these GPIO specifiers with the names used in the technical documentation available for the chip. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250823055420.24664-1-pshete@nvidia.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-09-01dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-8 SoCSeonGu Kang1-0/+1
Document the compatible string for ARTPEC-8 SoC pinctrl block, which is similar to other Samsung SoC pinctrl blocks. Signed-off-by: SeonGu Kang <ksk4725@coasia.com> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250901051926.59970-2-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-08-31dt-bindings: arm: apple: Add t8112 j415 compatibleJanne Grunau1-0/+2
This adds the "apple,j415" (MacBook Air (15-inch, M2, 2023) to the apple,t8112 platform. Reviewed-by: Neal Gompa <neal@gompa.dev> Reviewed-by: Sven Peter <sven@kernel.org> Signed-off-by: Janne Grunau <j@jannau.net> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250823-apple-dt-sync-6-17-v2-4-6dc0daeb4786@jannau.net Signed-off-by: Sven Peter <sven@kernel.org>
2025-08-31dt-bindings: arm: Convert Axis board/soc bindings to json-schemaRavi Patel2-13/+29
Convert Axis SoC bindings to DT schema format using json-schema. Existing bindings supports ARTPEC-6 SoC and board. Signed-off-by: SungMin Park <smn1196@coasia.com> Signed-off-by: SeonGu Kang <ksk4725@coasia.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Link: https://lore.kernel.org/r/20250825114436.46882-7-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-08-31dt-bindings: clock: Add ARTPEC-8 clock controllerHakyeong Kim1-0/+213
Add dt-schema for Axis ARTPEC-8 SoC clock controller. The Clock Management Unit (CMU) has a top-level block CMU_CMU which generates clocks for other blocks. Add device-tree binding definitions for following CMU blocks: - CMU_CMU - CMU_BUS - CMU_CORE - CMU_CPUCL - CMU_FSYS - CMU_IMEM - CMU_PERI Signed-off-by: Hakyeong Kim <hgkim05@coasia.com> Signed-off-by: SeonGu Kang <ksk4725@coasia.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Link: https://lore.kernel.org/r/20250825114436.46882-2-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-08-31dt-bindings: iio: adc: add IIO backend supportIoana Risteiu1-1/+43
Add the generic io-backends property to the AD7779 binding to enable support for the IIO backend framework. Also add the adi,num-lanes property to set the number of lanes used by AD7779. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Ioana Risteiu <Ioana.Risteiu@analog.com> Link: https://patch.msgid.link/20250825221355.6214-3-Ioana.Risteiu@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2025-08-31dt-bindings: media: rkisp1: Add second power domain on i.MX8MPLaurent Pinchart1-1/+18
In the NXP i.MX8MP, the pclk clock required by the ISP is gated by the MIPI CSI-2 power domain. Add it to the power-domains property, and require specifying power-domain-names accordingly. Link: https://lore.kernel.org/r/20250616011115.19515-3-laurent.pinchart@ideasonboard.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
2025-08-31dt-bindings: media: rkisp1: Require pclk clock on i.MX8MP variantLaurent Pinchart1-0/+4
The ISP integrated in the NXP i.MX8MP requires the pclk clock to access the HDR stitching registers. Make it mandatory in the DT binding. Link: https://lore.kernel.org/r/20250616011115.19515-2-laurent.pinchart@ideasonboard.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
2025-08-31dt-bindings: media: nxp,imx-mipi-csi2: Add fsl,num-channels propertyLaurent Pinchart1-0/+7
The CSI-2 receiver can be instantiated with up to four output channels. This is an integration-specific property, specify the number of instantiated channels through a new fsl,num-channels property. The property is optional, and defaults to 1 as only one channel is currently supported by drivers. Using the compatible string to infer the number of channels has been considered, but multiple instances of the same CSIS in the same SoC could conceptually be synthesized with a different number of channels. An explicit property is therefore more appropriate. The only known SoC to have more than one channel is the i.MX8MP. As the binding examples do not cover that SoC, don't update them. Link: https://lore.kernel.org/r/20250822002734.23516-12-laurent.pinchart@ideasonboard.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
2025-08-31dt-bindings: media: nxp,imx-mipi-csi2: Mark clock-frequency as deprecatedLaurent Pinchart1-2/+9
Usage of the clock-frequency property, which is already optional, is discouraged in favour of using assigned-clock-rates (and assigned-clock-parents where needed). Mark the property as deprecated, and update the examples accordingly. Link: https://lore.kernel.org/r/20250822002734.23516-11-laurent.pinchart@ideasonboard.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
2025-08-30dt-bindings: iio: adc: adi,ad7124: fix clocks propertiesDavid Lechner1-5/+16
Use correct clocks properties for the AD7124 family of ADCs. These ADCs have an internal clock along with an optional external clock that can be connected to the CLK pin. This pin can be wired up 3 ways: 1. Not connected - the internal clock is used. 2. Connected to an external clock (input) - the external clock is used. 3. Connected to the CLK pin on another ADC (output) - the internal clock is used on one and the other is configured for an external clock. The new bindings describe these 3 cases by picking one of the following: 1. Omit both clocks and #clock-cells properties. 2. Include only the clocks property with a phandle to the external clock. 3. Include only the #clock-cells property on the ADC providing the output. The clock-names property is now deprecated and should not be used. The MCLK signal that it refers to is an internal counter in the ADC and therefore does not make sense as a devicetree property as it can't be connected to anything external to the ADC. Since there is only one possible external clock, the clock-names property is not needed anyway. Based on the implementation of the Linux driver, it looks like the "mclk" clock was basically being used as a control to select the power mode of the ADC, which is not something that should be done in the devicetree. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20250828-iio-adc-ad7124-proper-clock-support-v3-1-0b317b4605e5@baylibre.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2025-08-30dt-bindings: crypto: Add binding for TI DTHE V2T Pratham1-0/+50
Add DT binding for Texas Instruments DTHE V2 cryptography engine. DTHE V2 is introduced as a part of TI AM62L SoC and can currently be only found in it. Signed-off-by: T Pratham <t-pratham@ti.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-08-30Merge tag 'renesas-pinctrl-for-v6.18-tag1' of ↵Linus Walleij1-0/+172
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.18 - Add support for Output Enable (OEN) on RZ/G3E, - Add support for the RZ/T2H and RZ/N2H SoCs, - Miscellaneous fixes and improvements. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-30dt-bindings: pinctrl: Convert brcm,iproc-gpio to DT schemaRob Herring (Arm)2-123/+111
Convert the Broadcom iProc/Cygnus GPIO/Pinconf binding to DT schema format. The child node structure is based on the example as there's not any actual .dts files with child nodes. The binding wasn't clear that "reg" can be 1 or 2 entries. The number of "reg" entries doesn't appear to be based on compatible, so no per compatible constraints for it The "brcm,iproc-stingray-gpio" could possibly be dropped. There are no .dts files using it, but the driver uses it. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/20250812203348.733749-1-robh@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-30dt-bindings: pinctrl: Convert brcm,bcm2835-gpio to DT schemaRob Herring (Arm)2-99/+120
Convert the Broadcom BCM2835 GPIO (and pinmux) controller binding to DT schema format. The structure of the child nodes wasn't well defined. The schema is based on the .dts users. The legacy binding is a single level of child nodes while the standard binding is 2 levels of child nodes. The "all banks" interrupt is treated as optional following actual users. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/20250812203337.731648-1-robh@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-29dt-bindings: mips: loongson: Add LS1B-DEMO and CQ-T300BKeguang Zhang1-0/+2
Document two Loongson-1 boards: - loongson,ls1b-demo: a board based on Loongson-1B - loongson,cq-t300b: a board based on Loongson-1C Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Keguang Zhang <keguang.zhang@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2025-08-29dt-bindings: mips: cpu: Add MIPS 34Kc CoreAleksander Jan Bajkowski1-0/+1
Document MIPS 34Kc device tree bindings. It is used in the Realtek RTL930x SoC. Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2025-08-29Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski2-1/+3
Cross-merge networking fixes after downstream PR (net-6.17-rc4). No conflicts. Adjacent changes: drivers/net/ethernet/intel/idpf/idpf_txrx.c 02614eee26fb ("idpf: do not linearize big TSO packets") 6c4e68480238 ("idpf: remove obsolete stashing code") Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-08-29dt-bindings: arm: ixp4xx: List actiontec devicesLinus Walleij1-0/+2
Add two IXP4xx device families from OpenWrts backlog: Actiontec MI424WR revision A/C and revision D, both of these are IXP4xx devices. Revisions E and later use different chipsets. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/20250822-ixp4xx-mi424wr-dts-v2-2-cc804884474d@linaro.org
2025-08-29dt-bindings: Add Actiontec vendor prefixLinus Walleij1-0/+2
Actiontec is a US manufacturer of telecom equipment. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/20250822-ixp4xx-mi424wr-dts-v2-1-cc804884474d@linaro.org
2025-08-29dt-bindings: soc: xilinx: Add support for K24, KR260 and KD240 CCsMichal Simek1-0/+81
The commit 7a4c31ee877a ("arm64: zynqmp: Add support for Xilinx Kria SOM board") has added support for k26 and kv260 and the commit dbcd27526e6a ("dt-bindings: soc: xilinx: Add support for KV260 CC") has added support for KV260 and this is follow up patch for adding description for k24 SOM, KR260 (robotics platform) and KD240 (driver platform). The bootflow is the same that's why for more information please take a look at above commits. The KD240 kit is based on smaller k24 SOM with only 2GB of memory. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/8ff66d0dc4e0de6f239c25d43a2a96b4224305e8.1752837842.git.michal.simek@amd.com
2025-08-29Merge tag 'drm-fixes-2025-08-29' of https://gitlab.freedesktop.org/drm/kernelLinus Torvalds1-1/+0
Pull drm fixes from Dave Airlie: "Weekly fixes, feels a bit big. The major piece is msm fixes, then the usual amdgpu/xe along with some mediatek and nouveau fixes and a tegra revert. gpuvm: - fix some typos xe: - Fix user-fence race issue - Couple xe_vm fixes - Don't trigger rebind on initial dma-buf validation - Fix a build issue related to basename() posix vs gnu discrepancy amdgpu: - pin buffers while vmapping - UserQ fixes - Revert CSA fix - SR-IOV fix nouveau: - fix linear modifier - remove some dead code msm: - Core/GPU: - fix comment doc warning in gpuvm - fix build with KMS disabled - fix pgtable setup/teardown race - global fault counter fix - various error path fixes - GPU devcoredump snapshot fixes - handle in-place VM_BIND remaps to solve turnip vm update race - skip re-emitting IBs for unusable VMs - Don't use %pK through printk - moved display snapshot init earlier, fixing a crash - DPU: - Fixed crash in virtual plane checking code - Fixed mode comparison in virtual plane checking code - DSI: - Adjusted width of resulution-related registers - Fixed locking issue on 14nm PLLs - UBWC (per Bjorn's ack) - Added UBWC configuration for several missing platforms (fixing regression) mediatek: - Add error handling for old state CRTC in atomic_disable - Fix DSI host and panel bridge pre-enable order - Fix device/node reference count leaks in mtk_drm_get_all_drm_priv - mtk_hdmi: Fix inverted parameters in some regmap_update_bits calls tegra: - revert dma-buf change" * tag 'drm-fixes-2025-08-29' of https://gitlab.freedesktop.org/drm/kernel: (56 commits) drm/mediatek: mtk_hdmi: Fix inverted parameters in some regmap_update_bits calls drm/amdgpu/userq: fix error handling of invalid doorbell drm/amdgpu: update firmware version checks for user queue support drm/amd/amdgpu: disable hwmon power1_cap* for gfx 11.0.3 on vf mode Revert "drm/amdgpu: fix incorrect vm flags to map bo" drm/amdgpu/gfx12: set MQD as appriopriate for queue types drm/amdgpu/gfx11: set MQD as appriopriate for queue types drm/xe: switch to local xbasename() helper drm/xe: Don't trigger rebind on initial dma-buf validation drm/xe/vm: Clear the scratch_pt pointer on error drm/xe/vm: Don't pin the vm_resv during validation drm/xe/xe_sync: avoid race during ufence signaling Revert "drm/tegra: Use dma_buf from GEM object instance" soc: qcom: use no-UBWC config for MSM8956/76 soc: qcom: add configuration for MSM8929 soc: qcom: ubwc: add more missing platforms soc: qcom: ubwc: use no-uwbc config for MSM8917 drm/msm/dpu: Add a null ptr check for dpu_encoder_needs_modeset dt-bindings: display/msm: qcom,mdp5: drop lut clock drm/gpuvm: fix various typos in .c and .h gpuvm file ...
2025-08-29Merge tag 'drm-msm-fixes-2025-08-26' of ↵Dave Airlie1-1/+0
https://gitlab.freedesktop.org/drm/msm into drm-fixes Fixes for v6.17-rc4 Core/GPU: - fix comment doc warning in gpuvm - fix build with KMS disabled - fix pgtable setup/teardown race - global fault counter fix - various error path fixes - GPU devcoredump snapshot fixes - handle in-place VM_BIND remaps to solve turnip vm update race - skip re-emitting IBs for unusable VMs - Don't use %pK through printk - moved display snapshot init earlier, fixing a crash DPU: - Fixed crash in virtual plane checking code - Fixed mode comparison in virtual plane checking code DSI: - Adjusted width of resulution-related registers - Fixed locking issue on 14nm PLLs UBWC (per Bjorn's ack) - Added UBWC configuration for several missing platforms (fixing regression) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rob Clark <rob.clark@oss.qualcomm.com> Link: https://lore.kernel.org/r/CACSVV02+u1VW1dzuz6JWwVEfpgTj6Y-JXMH+vX43KsKTVsW+Yg@mail.gmail.com
2025-08-29dt-bindings: display/msm: describe MDSS on SC8180XDmitry Baryshkov1-0/+359
Describe the Mobile Display SubSystem (MDSS) unit as present on the SC8180X platform. Reported-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/662498/ Link: https://lore.kernel.org/r/20250704-mdss-schema-v1-3-e978e4e73e14@oss.qualcomm.com
2025-08-29dt-bindings: display/msm: describe DPU on SC8180XDmitry Baryshkov1-0/+103
Describe the Display Processing Unit (DPU) as present on the SC8180X platform. Reported-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/662502/ Link: https://lore.kernel.org/r/20250704-mdss-schema-v1-2-e978e4e73e14@oss.qualcomm.com
2025-08-29dt-bindings: display/msm: dsi-controller-main: add SC8180XDmitry Baryshkov1-0/+2
Describe the SC8180X-specific compatible for the DSI controller persent on the SoC. While the current DT for SC8180X doesn't use this compatible, all other platforms were updated to have one. This change makes SC8180X follow the lead. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/662495/ Link: https://lore.kernel.org/r/20250704-mdss-schema-v1-1-e978e4e73e14@oss.qualcomm.com
2025-08-29dt-bindings: display/msm/gpu: describe clocks for each Adreno GPU typeDmitry Baryshkov1-26/+194
Rather than having a single list with all possible clocks for A3xx-A5xx define individual Adreno GPU types and corresponding clock lists. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/661348/ Link: https://lore.kernel.org/r/20250628-rework-msm-gpu-schema-v1-3-89f818c51b6a@oss.qualcomm.com
2025-08-29dt-bindings: display/msm/gpu: describe alwayson clockDmitry Baryshkov1-0/+2
Adreno A506 and A510 have one extra clock, alwayson. Describe it in the schema. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/661352/ Link: https://lore.kernel.org/r/20250628-rework-msm-gpu-schema-v1-2-89f818c51b6a@oss.qualcomm.com
2025-08-29dt-bindings: display/msm/gpu: account for 7xx GPUs in clocks conditionsDmitry Baryshkov1-1/+4
Handle two cases for Adreno 7xx: - Adreno 702 follows A610 and A619 example and has clocks in the GPU node. - Newer 7xx GPUs use a different pattern for the compatibles and did not match currently. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/661351/ Link: https://lore.kernel.org/r/20250628-rework-msm-gpu-schema-v1-1-89f818c51b6a@oss.qualcomm.com
2025-08-28ASoC: renesas: msiof: Make small adjustments to avoidMark Brown1-1/+1
Merge series from Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>: Current Renesas MSIOF get unknown error when first used. This patch-set will fixup this issue.
2025-08-28dt-bindings: cache: ax45mp: add 2048 as a supported cache-sets valueConor Dooley1-1/+5
The QiLai implementation of this cache controller uses a cache-sets of 2048, and mandates it in an if/else block - but the definition of the property only permits 1024. Add 2048 as an option, and deny its use outside of the QiLai. Fixes: 51b081cdb9237 ("dt-bindings: cache: add QiLai compatible to ax45mp") Reviewed-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-08-28dt-bindings: PCI: ti,am65: Extend for use with PVUJan Kiszka1-3/+25
The Peripheral Virtualization Unit (PVU) on the AM65 SoC is capable of restricting DMA from PCIe devices to specific regions of host memory. Add the optional property "memory-regions" to point to such regions of memory when PVU is used. Since the PVU deals with system physical addresses, utilizing the PVU with PCIe devices also requires setting up the VMAP registers to map the Requester ID of the PCIe device to the CBA Virtual ID, which in turn is mapped to the system physical address. Hence, describe the VMAP registers which are optional unless the PVU shall be used for PCIe. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Li Hua Qian <huaqian.li@siemens.com> [mani: Expanded PVU in description] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20250728023701.116963-3-huaqian.li@siemens.com
2025-08-28dt-bindings: arm: stm32: add required #clock-cells propertyRaphael Gallais-Pou1-10/+21
On STM32MP25 SoC, the syscfg peripheral provides a clock to the display subsystem through a multiplexer. Since it only provides a single clock, the cell value is 0. Doing so allows the clock consumers to reach the peripheral and gate the clock accordingly. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Yannick Fertre <yannick.fertre@foss.st.com> Acked-by: Christophe Roullier <christophe.roullier@foss.st.com> Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-6-9c825e28f733@foss.st.com Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
2025-08-28dt-bindings: display: st,stm32mp25-lvds: add power-domains propertyRaphael Gallais-Pou1-0/+3
STM32 LVDS peripheral may be in a power domain. Allow an optional single 'power-domains' entry for STM32 LVDS devices. Acked-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-5-9c825e28f733@foss.st.com Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
2025-08-28dt-bindings: display: st,stm32mp25-lvds: add access-controllers propertyRaphael Gallais-Pou1-0/+3
access-controllers is an optional property that allows a peripheral to refer to one or more domain access controller(s). This property is added when the peripheral is under the STM32 firewall controller. It allows an accurate representation of the hardware, where the peripheral is connected to a firewall bus. The firewall can then check the peripheral accesses before allowing its device to probe. Acked-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-4-9c825e28f733@foss.st.com Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
2025-08-28dt-bindings: display: st: add new compatible to LVDS deviceRaphael Gallais-Pou1-1/+6
Update the compatible to accept both "st,stm32mp255-lvds" and st,stm32mp25-lvds" respectively. Default will fall back to "st,stm32mp25-lvds". Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-3-9c825e28f733@foss.st.com Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
2025-08-28dt-bindings: display: st,stm32-ltdc: add access-controllers propertyRaphael Gallais-Pou1-0/+3
access-controllers is an optional property that allows a peripheral to refer to one or more domain access controller(s). This property is added when the peripheral is under the STM32 firewall controller. It allows an accurate representation of the hardware, where the peripheral is connected to a firewall bus. The firewall can then check the peripheral accesses before allowing its device to probe. Acked-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-2-9c825e28f733@foss.st.com Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
2025-08-28dt-bindings: display: st: add two new compatibles to LTDC deviceRaphael Gallais-Pou1-2/+50
The new STMicroelectronics SoC features a display controller similar to the one used in previous SoCs. Because there is additional registers, and different mandatory clocks it is incompatible with existing IPs. On STM32MP251, the device only needs two clocks while on STM32MP255 it needs four. Add the new names to the list of compatible string and handle each quirks accordingly. Acked-by: Philippe Cornu <philippe.cornu@foss.st.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-1-9c825e28f733@foss.st.com Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
2025-08-28dt-bindings: display: rockchip: Add schema for RK3588 DPTX ControllerAndy Yan1-0/+150
The Rockchip RK3588 SoC integrates the Synopsys DesignWare DPTX controller. And this DPTX controller need share a USBDP PHY with the USB 3.0 OTG controller during operation. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250822063959.692098-2-andyshrk@163.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-08-28dt-bindings: net: pse-pd: Add bindings for Si3474 PSE controllerPiotr Kubik1-0/+144
Add the Si3474 I2C Power Sourcing Equipment controller device tree bindings documentation. Signed-off-by: Piotr Kubik <piotr.kubik@adtran.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Kory Maincent <kory.maincent@bootlin.com> Link: https://patch.msgid.link/71a67c6f-6fce-49c7-96ec-554602dbd4f1@adtran.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2025-08-28dt-bindings: Remove outdated cpufreq-dt.txtFrank Li1-61/+0
The information present in this file is outdated and doesn't serve any purpose with the current design of the driver. Remove the outdated file. Signed-off-by: Frank Li <Frank.Li@nxp.com> [ Viresh: Rewrite commit log ] Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2025-08-28dt-bindings: ata: imx: Document 'target-supply'Fabio Estevam1-0/+3
The 'target-supply' property is used by some i.MX devicetree files. Document it to fix the following dt-schema warning: 'target-supply' does not match any of the regexes: '^pinctrl-[0-9]+$' Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
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