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2025-09-13dt-bindings: i2c: qcom-cci: Document sa8775p compatibleWenmeng Liu1-0/+2
Add the sa8775p CCI device string compatible. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Wenmeng Liu <quic_wenmliu@qualcomm.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
2025-09-13dt-bindings: i2c: qcom-cci: Document QCM2290 compatibleLoic Poulain1-2/+20
The CCI on QCM2290 is the interface for controlling camera sensor over I2C. It requires only two clocks. Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
2025-09-12dt-bindings: watchdog: renesas,wdt: Add support for RZ/T2H and RZ/N2HLad Prabhakar1-3/+33
Extend the Renesas WDT device tree bindings to support the watchdog timer found on the RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. The RZ/T2H WDT is mostly compatible with the one found on the RZ/V2H(P), but includes an additional register and differs in the clock division ratio settings for the WDTCR[CKS] field. To reflect these differences, introduce a new compatible string, "renesas,r9a09g077-wdt". The binding schema is updated accordingly. On RZ/T2H, the WDT does not require the "resets" property. It also requires two register regions and the presence of a "power-domains" property. The "clock-names" property is limited to a single entry, "pclk", for this SoC. The RZ/N2H SoC uses the same WDT IP as the RZ/T2H. It is supported by using "renesas,r9a09g087-wdt" as the primary compatible string, with "renesas,r9a09g077-wdt" listed as a fallback to describe the shared hardware features. Example: wdt0: watchdog@80082000 { compatible = "renesas,r9a09g077-wdt"; reg = <0 0x80082000 0 0x400>, <0 0x81295100 0 0x04>; clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; clock-names = "pclk"; power-domains = <&cpg>; status = "disabled"; }; Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
2025-09-12dt-bindings: serial: 8250_omap: Add wakeup pinctrl stateMarkus Schneider-Pargmann1-0/+16
Pins associated with the 8250 omap unit can be the source of a wakeup in deep sleep states. To be able to wakeup, these pins have to be configured in a special way. To support this configuration add the default and wakeup pinctrl states. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Signed-off-by: Kendall Willis <k-willis@ti.com> Link: https://lore.kernel.org/r/20250910-uart-daisy-chain-8250-omap-v2-1-e90d44c1a9ac@ti.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-09-12dt-bindings: nvmem: Document support for Airoha AN8855 Switch EFUSEChristian Marangi1-0/+123
Document support for Airoha AN8855 Switch EFUSE used to calibrate internal PHYs and store additional configuration info. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Srinivas Kandagatla <srini@kernel.org> Link: https://lore.kernel.org/r/20250912131415.303407-5-srini@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-09-12dt-bindings: nvmem: sl28cpld: add sa67mcu compatibleMichael Walle1-1/+6
The Kontron SMARC-sAM67 has the same nvmem layout as the SMARC-sAL28. To To be prepared for any board specific quirks, add a specific compatible. Signed-off-by: Michael Walle <mwalle@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Srinivas Kandagatla <srini@kernel.org> Link: https://lore.kernel.org/r/20250912131415.303407-4-srini@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-09-12dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml fileCiprian Costea1-0/+45
Add bindings to expose the On Chip One-Time Programmable Controller (OCOTP) for the NXP s32g chipset. There are three versions of this chip but they're compatible so we can fall back to the nxp,s32g2-ocotp compatible. Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com> Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Srinivas Kandagatla <srini@kernel.org> Link: https://lore.kernel.org/r/20250912131415.303407-2-srini@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-09-12dt-bindings: misc: qcom,fastrpc: Add GDSP labelLing Xu1-0/+2
There are some products which support GDSP remoteprocs. GDSP is General Purpose DSP where tasks can be offloaded. There are 2 GDSPs named gdsp0 and gdsp1. Add "gdsp0" and "gdsp1" as the new supported labels for GDSP fastrpc domains. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com> Signed-off-by: Ling Xu <quic_lxu5@quicinc.com> Signed-off-by: Srinivas Kandagatla <srini@kernel.org> Link: https://lore.kernel.org/r/20250912131302.303199-2-srini@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-09-12slimbus: qcom: remove unused qcom controller driverSrinivas Kandagatla2-95/+4
Qcom Slimbus controller driver is totally unused and dead code, there is no point in keeping this driver in the kernel without users. This patch removes the driver along with device tree bindings. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Srinivas Kandagatla <srini@kernel.org> Link: https://lore.kernel.org/r/20250912131202.303026-2-srini@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-09-12dt-bindings: marvell: armada-37xx: add ripe,atlas-v5 compatibleTomáš Macholda1-0/+1
Document compatible for RIPE Atlas Probe v5. Signed-off-by: Tomáš Macholda <tomas.macholda@nic.cz> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-09-12dt-bindings: mmc: controller: Add max-sd-hs-hz propertySarthak Garg1-0/+8
Introduce a new optional device tree property max-sd-hs-hz to limit the maximum frequency (in Hz) used for SD cards operating in High-Speed (HS) mode due to any board electrical limitations. Signed-off-by: Sarthak Garg <quic_sartgarg@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-09-12dt-bindings: mmc: sdhci-msm: Document the Lemans compatibleMonish Chunara1-0/+1
Add the MSM SDHCI compatible name to support both eMMC and SD card for Lemans, which uses 'sa8775p' as the fallback SoC. Ensure the new compatible string matches existing Lemans-compatible formats without introducing a new naming convention. The SDHCI controller on Lemans is based on MSM SDHCI v5 IP. Hence, document the compatible with "qcom,sdhci-msm-v5" as the fallback. Signed-off-by: Monish Chunara <quic_mchunara@quicinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Wasim Nazir <wasim.nazir@oss.qualcomm.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-09-12dt-bindings: mmc: sdhci-pxa: Add minItems to pinctrl-namesDuje Mihanović1-0/+2
Some older boards only require a default pinctrl. Add a minItems property so these don't cause dt-validate warnings. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202509030625.PBgLIAwG-lkp@intel.com/ Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-09-12Merge tag 'samsung-pinctrl-6.18' of ↵Linus Walleij2-22/+2
https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers changes for v6.18 1. Add pin controller drivers for new Axis ARTPEC-8 SoC. The SoC shares all main blocks, including the pin controller, with Samsung SoC, so same drivers and bindings are used. 2. Drop remaining support for Samsung S3C2410 SoC pin controllers. The actual SoC support was removed in January 2023, so this is just remaining cleanup. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-12Merge branch 'icc-glymur' into icc-nextGeorgi Djakov1-0/+172
Add interconnect dt-bindings and driver support for Qualcomm's next gen compute SoC - Glymur. * icc-glymur dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Glymur SoC interconnect: qcom: icc-rpmh: increase MAX_PORTS to support four QoS ports interconnect: qcom: add glymur interconnect provider driver Link: https://lore.kernel.org/r/20250814-glymur-icc-v2-0-596cca6b6015@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2025-09-12dt-bindings: interconnect: Add OSM L3 compatible for QCS615 SoCRaviteja Laggyshetty1-0/+5
Add Operation State Manager (OSM) L3 interconnect provider binding for QCS615 SoC. As the OSM hardware in QCS615 and SM8150 are same, added a family-level compatible for SM8150 SoC. Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250819-talos-l3-icc-v3-1-04529e85dac7@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2025-09-12dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62PStefano Radaelli1-0/+6
Add devicetree bindings for Variscite VAR-SOM-AM62P System on Module and its carrier boards. Signed-off-by: Stefano Radaelli <stefano.radaelli21@gmail.com> Reviewed-by: Judith Mendez <jm@ti.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250909213749.28098-2-stefano.radaelli21@gmail.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-09-12dt-bindings: arm: ti: Add binding for AM625 SiPAnshul Dalal1-0/+7
The AM6254atl SiP belongs to the K3 Multicore SoC architecture platform, providing AM625 SoC with 512MiB of integrated DDR in the package. For further information about the package check: https://www.ti.com/lit/ds/symlink/am625sip.pdf Signed-off-by: Anshul Dalal <anshuld@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20250814134531.2743874-3-anshuld@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-09-12dt-bindings: net: Convert APM XGene MDIO to DT schemaRob Herring (Arm)2-37/+54
Convert the APM XGene MDIO bus binding to DT schema format. It's a straight-forward conversion. Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250908231016.2070305-2-robh@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-09-12dt-bindings: net: Convert apm,xgene-enet to DT schemaRob Herring (Arm)2-91/+115
Convert the APM XGene Ethernet binding to DT schema format. Add the missing apm,xgene2-sgenet and apm,xgene2-xgenet compatibles. Drop "reg-names" as required. Add support for up to 16 interrupts. Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250908231016.2070305-1-robh@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-09-12Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski1-0/+5
Cross-merge networking fixes after downstream PR (net-6.17-rc6). Conflicts: net/netfilter/nft_set_pipapo.c net/netfilter/nft_set_pipapo_avx2.c c4eaca2e1052 ("netfilter: nft_set_pipapo: don't check genbit from packetpath lookups") 84c1da7b38d9 ("netfilter: nft_set_pipapo: use avx2 algorithm for insertions too") Only trivial adjacent changes (in a doc and a Makefile). Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-09-12support for Amlogic SPI Flash Controller IPMark Brown1-0/+82
Merge series from Xianwei Zhao <xianwei.zhao@amlogic.com>: This Flash Controller is derived by adding an SPI path to the original raw NAND controller. This controller supports two modes: raw mode and SPI mode. The raw mode has already been implemented in the community (drivers/mtd/nand/raw/meson_nand.c). This submission supports the SPI mode. Add the drivers and bindings corresponding to the SPI Flash Controller.
2025-09-11dt-bindings: soc: renesas: Document R-Car X5H IronhideKuninori Morimoto1-0/+6
Document the compatible values for the Renesas R-Car X5H (R8A78000) SoC, as used on the Renesas Ironhide board. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/87ms73vzen.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-09-11dt-bindings: arm: tegra: Add ASUS TF101G and SL101Svyatoslav Ryhel1-2/+6
Add a compatible for ASUS Eee Pad Transformer TF101G and ASUS Eee Pad Slider SL101. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-09-11dt-bindings: arm: tegra: Add Xiaomi Mi Pad (A0101)Svyatoslav Ryhel1-0/+4
Add a compatible for the Xiaomi Mi Pad (A0101) tablet. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-09-11dt-bindings: display: tegra: Move avdd-dsi-csi-supply from VI to CSISvyatoslav Ryhel2-3/+3
The avdd-dsi-csi-supply is CSI power supply, it has nothing to do with VI, like same supply is used with DSI and has nothing to do with DC. Move it to correct place. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-09-11dt-bindings: i2c: nvidia,tegra20-i2c: Document Tegra264 I2CKartik Rajput1-0/+7
Tegra264 has 17 generic I2C controllers, two of which are in always-on partition of the SoC. In addition to the features supported by Tegra194 it also supports a SW mutex register to allow sharing the same I2C instance across multiple firmware. Document compatible string "nvidia,tegra264-i2c" for Tegra264 I2C. Signed-off-by: Kartik Rajput <kkartik@nvidia.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-09-11dt-bindings: mfd: ti,bq25703a: Add TI BQ25703A ChargerChris Morgan1-0/+117
Document the Texas instruments BQ25703A series of charger managers/ buck/boost regulators. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250904160530.66178-2-macroalpha82@gmail.com Signed-off-by: Lee Jones <lee@kernel.org>
2025-09-11dt-bindings: eeprom: at24: Add compatible for Giantec GT24C256CWasim Nazir1-0/+1
The gt24c256c is another 24c256 compatible EEPROM, and does not follow the generic name matching, so add a separate compatible for it. This ensures accurate device-tree representation and enables proper kernel support for systems using this part. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Wasim Nazir <wasim.nazir@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250908-lemans-evk-bu-v4-5-5c319c696a7d@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-09-11ASoC: dt-bindings: linux,spdif: Add "port" nodeRob Herring (Arm)1-0/+3
The SPDIF receiver/transmitter can be connected to a DAI device via OF graph port. It is already in use and supported. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250910233615.775397-2-robh@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-11ASoC: dt-bindings: ti,pcm1754: add binding documentationStefan Kerkmann1-0/+55
The Texas Instruments PCM1754 is a simple stereo DAC without any digital management interface but soft mute, PCM input format and 44.1 kHz digital de-emphasis can be configured via strapping pins. Only soft mute and PCM input format selection is currently exposed via optional GPIOs in the driver. Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20250910-v6-12-topic-pcm1754-v2-1-0917dbe73c65@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-11Merge tag 'w1-drv-6.18' of ↵Greg Kroah-Hartman1-0/+4
ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux-w1 into char-misc-next Krzysztof writes: 1-Wire bus drivers for v6.18 1. Correct missing interrupts in IMX 1-Wire Devicetree bindings. 2. Drop old, dead code from Matrox driver. * tag 'w1-drv-6.18' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux-w1: w1: matrox: Remove some deadcode in matrox_w1_remove() dt-bindings: w1: imx: Add an entry for the interrupts property
2025-09-11dt-bindings: soc: rockchip: add rk3588 csidphy grf sysconMichael Riesch1-0/+1
Add CSIDPHY GRF syscon compatible for the Rockchip RK3588. Acked-by: "Rob Herring (Arm)" <robh@kernel.org> Signed-off-by: Michael Riesch <michael.riesch@collabora.com> Link: https://lore.kernel.org/r/20250616-rk3588-csi-dphy-v4-1-a4f340a7f0cf@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-09-11dt-bindings: arm: fsl: add TQMa91xx SOM seriesAlexander Stein1-0/+18
TQMa91xx series is using NXP i.MX91 CPU on an LGA or socketable type board. MBa91xxCA is a starterkit base board for TQMa91xx on an adapter board. Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11dt-bindings: fsl: fsl,imx7ulp-smc1: Allow clocks and clock-namesFrank Li1-0/+8
Allow clocks and clock-names to match existed dts file. 'hsrun_divcore' should be 'hsrun-divcore'. But use '_' to keep old dts back compatible. Fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx7ulp-com.dtb: clock-controller@40410000 (fsl,imx7ulp-smc1): '#clock-cells', 'clock-names', 'clocks' do not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/arm/freescale/fsl,imx7ulp-pm.yaml# Signed-off-by: Frank Li <Frank.Li@nxp.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11dt-bindings: arm: fsl: Add bindings for SolidRun i.MX8MP SoM and boardsJosua Mayer1-0/+11
Add bindings for SolidRun i.MX8M Plus System on Module based boards: - CuBox-M is a complete produc with enclosure including the SoM - HummingBoard Mate/Pro/Pulse/Ripple are evaluation boards with common design but different available interfaces. Signed-off-by: Josua Mayer <josua@solid-run.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11dt-bindings: soc: fsl,imx-iomuxc-gpr: Document i.MX53Fabio Estevam1-0/+1
imx53.dtsi has the following compatible entry: compatible = "fsl,imx53-iomuxc-gpr", "syscon"; Document the "fsl,imx53-iomuxc-gpr" entry to fix the following dt-schema warning: failed to match any schema with compatible: ['fsl,imx53-iomuxc-gpr', 'syscon'] Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11dt-bindings: arm: fsl: Add EDM-G-IMX8M-PLUS SOM and WB-EDM-G carrier boardRay Chang1-0/+7
Add support for TechNexion EDM-G-IMX8M-PLUS SOM and WB-EDM-G carrier board. Signed-off-by: Ray Chang <ray.chang@technexion.com> Signed-off-by: Richard Hu <richard.hu@technexion.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11dt-bindings: arm: nxp: lpc: Assign myself as maintainer of NXP LPC32xx platformsVladimir Zapolskiy1-1/+1
Make a formal change to reflect the actual NXP LPC32xx maintainership for the last years. Cc: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2025-09-10dt-bindings: iio: afe: current-sense-amplifier: Add io-channel-cellsPrimoz Fiser1-0/+4
The current-sense-amplifier is an IIO provider thus can be referenced by IIO consumers (via "io-channels" property in consumer device node). Such provider is required to describe number of cells used in phandle lookup with "io-channel-cells" property. Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20250905065503.3022107-1-primoz.fiser@norik.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2025-09-10dt-bindings: iio: magnetometer: Infineon TLV493D 3D Magnetic sensorDixit Parmar2-2/+45
Document the bindings for Infineon TLV493D Low-Power 3D Magnetic Sensor controlled by I2C interface. Main applications includes joysticks, control elements (white goods, multifunction knops), or electric meters (anti- tampering). Drop duplicate entry for infineon,tlv493d from trivial-devices.yaml as its documented in this separate dt-binding file now. Datasheet: https://www.infineon.com/assets/row/public/documents/24/49/infineon-tlv493d-a1b6-datasheet-en.pdf Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dixit Parmar <dixitparmar19@gmail.com> Link: https://patch.msgid.link/20250906-tlv493d-sensor-v6_16-rc5-v6-1-b1a62d968353@gmail.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2025-09-10dt-bindings: iio: adc: samsung,exynos: Drop touchscreen supportKrzysztof Kozlowski1-11/+11
With last user of touchscreen via ADC (S3C24xx SoC) gone, drop the unused has-touchscreen property and optional touchscreen interrupt for samsung,s3c6410-adc. The samsung,s5pv210-adc is the only platform having two interrupts, so add a constrain for that. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20250830-s3c-cleanup-adc-v2-5-4f8299343d32@linaro.org Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2025-09-10dt-bindings: iio: adc: samsung,exynos: Drop S3C2410Krzysztof Kozlowski1-4/+0
Samsung S3C24xx family of SoCs was removed the Linux kernel in the commit 61b7f8920b17 ("ARM: s3c: remove all s3c24xx support"), in January 2023. There are no in-kernel users of remaining S3C24xx compatibles. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20250830-s3c-cleanup-adc-v2-4-4f8299343d32@linaro.org Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2025-09-10dt-bindings: phy: rockchip-inno-csi-dphy: add rk3588 variantMichael Riesch1-1/+49
The Rockchip RK3588 variant of the CSI-2 DPHY features two reset lines. Add the variant and allow for the additional reset. While at it, fix the description of the first reset in order to avoid confusion. Signed-off-by: Michael Riesch <michael.riesch@collabora.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250616-rk3588-csi-dphy-v4-3-a4f340a7f0cf@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-09-10dt-bindings: phy: rockchip-inno-csi-dphy: make power-domains non-requiredMichael Riesch1-1/+14
There are variants of the Rockchip Innosilicon CSI DPHY (e.g., the RK3568 variant) that are powered on by default as they are part of the ALIVE power domain. Remove 'power-domains' from the required properties in order to avoid false positives. Fixes: 22c8e0a69b7f ("dt-bindings: phy: add compatible for rk356x to rockchip-inno-csi-dphy") Cc: stable@kernel.org Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Michael Riesch <michael.riesch@collabora.com> Link: https://lore.kernel.org/r/20250616-rk3588-csi-dphy-v4-2-a4f340a7f0cf@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-09-10dt-bindings: phy: Add Sophgo CV1800 USB phyInochi Amaoto1-0/+54
The USB phy of Sophgo CV18XX series SoC needs to sense a pin called "VBUS_DET" to get the right operation mode. If this pin is not connected, it only supports setting the mode manually. Add USB phy bindings for Sophgo CV18XX/SG200X series SoC. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250708063038.497473-2-inochiama@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-09-10dt-bindings: pinctrl: qcom: Add SDM660 LPI pinctrlNickolay Goppen1-0/+109
Add bindings for pin controller in SDM660 Low Power Audio SubSystem (LPASS). Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Co-developed-by: Richard Acayan <mailingradian@gmail.com> Signed-off-by: Richard Acayan <mailingradian@gmail.com> Signed-off-by: Nickolay Goppen <setotau@mainlining.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-10spi: dt-bindings: add Amlogic A113L2 SFCFeng Chen1-0/+82
The Flash Controller is derived by adding an SPI path to the original raw NAND controller. This controller supports two modes: raw mode and SPI mode. The raw mode has already been implemented in the community, and the SPI mode is described here. Add bindings for Amlogic A113L2 SPI Flash Controller. Signed-off-by: Feng Chen <feng.chen@amlogic.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Link: https://patch.msgid.link/20250910-spifc-v6-1-1574aa9baebd@amlogic.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-10dt-bindings: arm: mediatek: Add grinn,genio-510-sbcMateusz Koza1-0/+1
Add device tree bindings support for the Grinn GenioSBC-510, a single-board computer based on the MediaTek Genio 510 SoC. More details about the hardware: - https://grinn-global.com/products/grinn-geniosom-510 - https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Mateusz Koza <mateusz.koza@grinn-global.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20250908130620.2309399-5-mateusz.koza@grinn-global.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2025-09-10dt-bindings: arm: mediatek: Add grinn,genio-700-sbcMateusz Koza1-0/+1
Add device tree bindings support for the Grinn GenioSBC-700, a single-board computer based on the MediaTek Genio 700 SoC. More details about the hardware: - https://grinn-global.com/products/grinn-geniosom-700 - https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Mateusz Koza <mateusz.koza@grinn-global.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20250908130620.2309399-3-mateusz.koza@grinn-global.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
generated by cgit v1.2.3 (git 2.39.0) at 2026-05-22 01:35:53 +0300