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2025-10-25dt-bindings: net: snps,dwmac: move rk3399 line to its correct positionHeiko Stuebner1-1/+1
Move the rk3399 compatible to its alphabetically correct position. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patch.msgid.link/20251023111213.298860-2-heiko@sntech.de Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-10-24dt-bindings: npu: Add Arm Ethos-U65/U85Rob Herring (Arm)1-0/+79
Add a binding schema for Arm Ethos-U65/U85 NPU. The Arm Ethos-U NPUs are designed for edge AI inference applications. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Acked-by: Tomeu Vizoso <tomeu@tomeuvizoso.net> Link: https://patch.msgid.link/20251020-ethos-v6-1-ecebc383c4b7@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-10-24dt-bindings: interrupt-controller: Add UltraRISC DP1000 PLICCharles Mirabile1-0/+3
Add compatible strings for the PLIC found in UltraRISC DP1000 SoC. The PLIC is part of the UR-CP100 core and has a hardware bug requiring a workaround. Signed-off-by: Charles Mirabile <cmirabil@redhat.com> Signed-off-by: Lucas Zampieri <lzampier@redhat.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251024083647.475239-3-lzampier@redhat.com
2025-10-24dt-bindings: vendor-prefixes: Add UltraRISCLucas Zampieri1-0/+2
Add vendor prefix for UltraRISC Technology Co., Ltd. Signed-off-by: Lucas Zampieri <lzampier@redhat.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251024083647.475239-2-lzampier@redhat.com
2025-10-24Merge tag 'spi-fix-v6.18-rc2' of ↵Linus Torvalds2-3/+9
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "A moderately large collection of device specific changes here, mostly fixes but also including a few new quirks and device IDs. This is all fairly routine even for the affected devices" * tag 'spi-fix-v6.18-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: dt-bindings: spi-rockchip: Add RK3506 compatible spi: intel-pci: Add support for Intel Wildcat Lake SPI serial flash spi: intel-pci: Add support for Arrow Lake-H SPI serial flash spi: intel: Add support for 128M component density spi: airoha: fix reading/writing of flashes with more than one plane per lun spi: airoha: switch back to non-dma mode in the case of error spi: airoha: add support of dual/quad wires spi modes to exec_op() handler spi: airoha: return an error for continuous mode dirmap creation cases spi: amlogic: fix spifc build error spi: cadence-quadspi: Fix pm_runtime unbalance on dma EPROBE_DEFER spi: spi-nxp-fspi: limit the clock rate for different sample clock source selection spi: spi-nxp-fspi: add extra delay after dll locked spi: spi-nxp-fspi: re-config the clock rate when operation require new clock rate spi: dw-mmio: add error handling for reset_control_deassert() spi: rockchip-sfc: Fix DMA-API usage spi: dt-bindings: cadence: add soc-specific compatible strings for zynqmp and versal-net
2025-10-24dt-bindings: power: Add MT8196 GPU frequency control bindingNicolas Frattaroli1-0/+117
On the MT8196 and MT6991 SoCs, the GPU power and frequency is controlled by some integration logic, referred to as "MFlexGraphics" by MediaTek, which comes in the form of an embedded controller running special-purpose firmware. This controller takes care of the regulators and PLL clock frequencies to squeeze the maximum amount of power out of the silicon. Add a binding which models it as a power domain. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-10-24Merge drm/drm-next into drm-misc-nextThomas Zimmermann5-21/+75
Backmerging to get fixes and features of v6.18-rc2. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
2025-10-24dt-bindings: usb: qcom,snps-dwc3: Add the SM8750 compatibleKonrad Dybcio1-0/+3
Add qcom,sm8750-dwc3 compatible to flattened implementation binding. Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20251021050954.3462613-1-krishna.kurapati@oss.qualcomm.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-10-24Merge tag 'drm-misc-next-2025-10-21' of ↵Simona Vetter2-1/+5
https://gitlab.freedesktop.org/drm/misc/kernel into drm-next drm-misc-next for v6.19: UAPI Changes: amdxdna: - Support reading last hardware error Cross-subsystem Changes: dma-buf: - heaps: Create heap per CMA reserved location; Improve user-space documentation Core Changes: atomic: - Clean up and improve state-handling interfaces, update drivers bridge: - Improve ref counting buddy: - Optimize block management Driver Changes: amdxdna: - Fix runtime power management - Support firmware debug output ast: - Set quirks for each chip model atmel-hlcdc: - Set LCDC_ATTRE register in plane disable - Set correct values for plane scaler bochs: - Use vblank timer bridge: - synopsis: Support CEC; Init timer with correct frequency cirrus-qemu: - Use vblank timer imx: - Clean up ivu: - Update JSM API to 3.33.0 - Reset engine on more job errors - Return correct error codes for jobs komeda: - Use drm_ logging functions panel: - edp: Support AUO B116XAN02.0 panfrost: - Embed struct drm_driver in Panfrost device - Improve error handling - Clean up job handling panthor: - Support custom ASN_HASH for mt8196 renesas: - rz-du: Fix dependencies rockchip: - dsi: Add support for RK3368 - Fix LUT size for RK3386 sitronix: - Fix output position when clearing screens qaic: - Support dma-buf exports - Support new firmware's READ_DATA implementation - Replace kcalloc with memdup - Replace snprintf() with sysfs_emit() - Avoid overflows in arithmetics - Clean up - Fixes qxl: - Use vblank timer rockchip: - Clean up mode-setting code vgem: - Fix fence timer deadlock virtgpu: - Use vblank timer Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Thomas Zimmermann <tzimmermann@suse.de> Link: https://lore.kernel.org/r/20251021111837.GA40643@linux.fritz.box
2025-10-24dt-bindings: pinctrl: document polarfire soc iomux0 pinmuxConor Dooley2-1/+101
On Polarfire SoC, iomux0 is responsible for routing functions to either Multiprocessor Subsystem (MSS) IOs or to the FPGA fabric, where they can either interface with custom RTL or be routed to the FPGA fabric's IOs. Document it. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-10-24dt-bindings: pinctrl: document pic64gx "gpio2" pinmuxConor Dooley1-0/+74
The pic64gx has a second pinmux "downstream" of the iomux0 pinmux. The documentation for the SoC provides no name for this device, but it is used to swap pins between either GPIO controller #2 or select other functions, hence the "gpio2" name. Currently there is no documentation about what each bit actually does that is publicly available, nor (I believe) what pins are affected. That info is as follows: pin role (1/0) --- ---------- E14 MAC_0_MDC/GPIO_2_0 E15 MAC_0_MDIO/GPIO_2_1 F16 MAC_1_MDC/GPIO_2_2 F17 MAC_1_MDIO/GPIO_2_3 D19 SPI_0_CLK/GPIO_2_4 B18 SPI_0_SS0/GPIO_2_5 B10 CAN_0_RXBUS/GPIO_2_6 C14 PCIE_PERST_2#/GPIO_2_7 E18 PCIE_WAKE#/GPIO_2_8 D18 PCIE_PERST_1#/GPIO_2_9 E19 SPI_0_DO/GPIO_2_10 C7 SPI_0_DI/GPIO_2_11 D6 QSPI_SS0/GPIO_2_12 D7 QSPI_CLK (B)/GPIO_2_13 C9 QSPI_DATA0/GPIO_2_14 C10 QSPI_DATA1/GPIO_2_15 A5 QSPI_DATA2/GPIO_2_16 A6 QSPI_DATA3/GPIO_2_17 D8 MMUART_3_RXD/GPIO_2_18 D9 MMUART_3_TXD/GPIO_2_19 B8 MMUART_4_RXD/GPIO_2_20 A8 MMUART_4_TXD/GPIO_2_21 C12 CAN_1_TXBUS/GPIO_2_22 B12 CAN_1_RXBUS/GPIO_2_23 A11 CAN_0_TX_EBL_N/GPIO_2_24 A10 CAN_1_TX_EBL_N/GPIO_2_25 D11 MMUART_2_RXD/GPIO_2_26 C11 MMUART_2_TXD/GPIO_2_27 B9 CAN_0_TXBUS/GPIO_2_28 Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-10-24Merge tag 'mpfs-pinctrl-binding-base' of ↵Linus Walleij1-0/+47
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into devel mpfs pinctrl binding base The pinctrl binding patch for iomux0 mpfs adds a ref to itself to the syscon/mfd mss-top-sysreg binding, and therefore needs that file to exist. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-10-23Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski7-21/+81
Cross-merge networking fixes after downstream PR (net-6.18-rc3). No conflicts or adjacent changes. Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-10-23dt-bindings: pinctrl: toshiba,visconti: Fix number of items in groupsKrzysztof Kozlowski1-12/+14
The "groups" property can hold multiple entries (e.g. toshiba/tmpv7708-rm-mbrc.dts file), so allow that by dropping incorrect type (pinmux-node.yaml schema already defines that as string-array) and adding constraints for items. This fixes dtbs_check warnings like: toshiba/tmpv7708-rm-mbrc.dtb: pinctrl@24190000 (toshiba,tmpv7708-pinctrl): pwm-pins:groups: ['pwm0_gpio16_grp', 'pwm1_gpio17_grp', 'pwm2_gpio18_grp', 'pwm3_gpio19_grp'] is too long Fixes: 1825c1fe0057 ("pinctrl: Add DT bindings for Toshiba Visconti TMPV7700 SoC") Cc: stable@vger.kernel.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-10-23dt-bindings: pinctrl: toshiba,visconti: Drop redundant functions typeKrzysztof Kozlowski1-1/+0
Referenced pinmux-node.yaml schema already defines type for "functions" so $ref is redundant. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-10-23spi: dt-bindings: don't check node namesWolfram Sang2-2/+2
Node names are already and properly checked by the core schema. No need to do it again. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251020060951.30776-10-wsa+renesas@sang-engineering.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-23regulator: dt-bindings: qcom,rpmh: Add support for PMR735DJishnu Prakash1-0/+14
Add support for PMR735D PMIC used on Kaanapali boards. Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20251023-pmr735d_regulator-v2-1-452e1b28cd38@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-23dt-bindings: ata: snps,dwc-ahci: Allow 'iommus' propertyRob Herring (Arm)1-0/+4
The AMD Seattle DWC AHCI is behind an IOMMU and has 1-3 entries, so add the 'iommus' property. There's not a specific compatible, so we can't limit it to Seattle. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Niklas Cassel <cassel@kernel.org>
2025-10-23Merge tag 'scsi-fixes' of ↵Linus Torvalds2-0/+6
git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi Pull SCSI fixes from James Bottomley: "All driver fixes. The big change is the storvsc one to rejig the hyper-v channel handling to be more efficient for SMP virtual machines" * tag 'scsi-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi: scsi: ufs: phy: dt-bindings: Add QMP UFS PHY compatible for Kaanapali scsi: ufs: qcom: dt-bindings: Document the Kaanapali UFS controller scsi: libfc: Prevent integer overflow in fc_fcp_recv_data() scsi: qla4xxx: Fix typos in comments scsi: storvsc: Prefer returning channel with the same CPU as on the I/O issuing CPU
2025-10-23dt-bindings: cache: qcom,llcc: Document the Kaanapali LLCCJingyi Wang1-0/+2
Document the Last Level Cache Controller on Kaanapali platform. Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250924-knp-llcc-v1-1-ae6a016e5138@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-10-23Merge branch '20251014-qcom_ipq5424_nsscc-v7-2-081f4956be02@quicinc.com' ↵Bjorn Andersson1-8/+55
into clk-for-6.19 Merge binding changes for IPQ5424 network subsystem clock controllers through topic branch, to make them available for DeviceTree branch as well.
2025-10-23dt-bindings: clock: qcom: Add NSS clock controller for IPQ5424 SoCLuo Jie1-8/+54
NSS clock controller provides the clocks and resets to the networking blocks such as PPE (Packet Process Engine) and UNIPHY (PCS) on IPQ5424 devices. Add support for the compatible string "qcom,ipq5424-nsscc" based on the existing IPQ9574 NSS clock controller Device Tree binding. Additionally, update the clock names for PPE and NSS for newer SoC additions like IPQ5424 to use generic and reusable identifiers "nss" and "ppe" without the clock rate suffix. Also add master/slave ids for IPQ5424 networking interfaces, which is used by nss-ipq5424 driver for providing interconnect services using icc-clk framework. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Link: https://lore.kernel.org/r/20251014-qcom_ipq5424_nsscc-v7-7-081f4956be02@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-10-23dt-bindings: clock: Add "#interconnect-cells" property in IPQ9574 exampleLuo Jie1-0/+1
The Networking Subsystem (NSS) clock controller acts as both a clock provider and an interconnect provider. The #interconnect-cells property is needed in the Device Tree Source (DTS) to ensure that client drivers such as the PPE driver can correctly acquire ICC clocks from the NSS ICC provider. Add the #interconnect-cells property to the IPQ9574 Device Tree binding example to complete it. Fixes: 28300ecedce4 ("dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions") Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Link: https://lore.kernel.org/r/20251014-qcom_ipq5424_nsscc-v7-2-081f4956be02@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-10-22dt-bindings: touchscreen: consolidate simple touch controller to ↵Frank Li6-332/+29
trivial-touch.yaml Move azoteq,iqs5xx.yaml, himax,hx83112b.yaml, hynitron,cstxxx.yaml, ilitek_ts_i2c.yaml, semtech,sx8654.yaml, ar1021.txt to trivial-touch.yaml to consolidate simple touch yaml binding to one file. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20251021201924.2881098-2-Frank.Li@nxp.com Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2025-10-22dt-bindings: touchscreen: trivial-touch: add reset-gpios and wakeup-sourceFrank Li1-0/+5
Add optional reset-gpios and wakeup-source properties. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20251021201924.2881098-1-Frank.Li@nxp.com Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2025-10-22spi: dt-bindings: spi-rockchip: Add RK3506 compatibleHeiko Stuebner1-0/+1
The SPI controller found in the RK3506 SoC is still compatible to the original one introduced with the RK3066, so add the RK3506 compatible to the list of its variants. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patch.msgid.link/20251022004200.204276-1-heiko@sntech.de Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-22dt-bindings: pinctrl: Convert bitmain,bm1880-pinctrl to DT schemaRob Herring (Arm)2-126/+132
Convert the bitmain,bm1880-pinctrl binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-10-22dt-bindings: pinctrl: Convert brcm,ns2-pinmux to DT schemaRob Herring (Arm)2-102/+111
Convert the brcm,ns2-pinmux binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-10-22dt-bindings: pinctrl: Convert actions,s900-pinctrl to DT schemaRob Herring (Arm)2-204/+219
Convert the actions,s900-pinctrl binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-10-22dt-bindings: pinctrl: Convert actions,s700-pinctrl to DT schemaRob Herring (Arm)2-170/+204
Convert the actions,s700-pinctrl binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-10-22dt-bindings: power: rockchip: Add support for RV1126BFinley Xiao1-0/+2
Add power domain IDs for RV1126B SoC. Add a new compatible because register fields have changed. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-10-22dt-bindings: power: Add support for MT8196 power controllersAngeloGioacchino Del Regno1-0/+4
Add support for the power controllers found in the MediaTek MT8196 Chromebook SoC. This chip has three power controllers, two of which located in the SCP subsystems (where one can be directly controlled and the other can be controlled only through the HW Voter IP), and one located in the Multimedia HFRP subsystem, controllable only through the HW Voter IP. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-10-22dt-bindings: serial: sh-sci: Fix r8a78000 interruptsGeert Uytterhoeven1-0/+1
The SCIF instances on R-Car Gen5 have a single interrupt, just like on other R-Car SoCs. Fixes: 6ac1d60473727931 ("dt-bindings: serial: sh-sci: Document r8a78000 bindings") Cc: stable <stable@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/09bc9881b31bdb948ce8b69a2b5acf633f5505a4.1759920441.git.geert+renesas@glider.be Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-10-22dt-bindings: serial: samsung: add samsung,exynos8890-uart compatibleIvaylo Ivanov1-0/+1
Add dedicated samsung,exynos8890-uart compatible to the dt-schema for representing uart of the exynos8890. Like exynos8895, it has a required DT property samsung,uart-fifosize, so reuse support for it. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250914132201.2622955-1-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-10-22dt-bindings: serial: samsung: Add compatible for ARTPEC-9 SoCRavi Patel1-0/+1
Add Axis ARTPEC-9 uart compatible to the bindings documentation. It is similar to the older samsung,exynos8895-uart design. Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20250918032703.8885-1-ravi.patel@samsung.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-10-22dt-bindings: mmc: rockchip-dw-mshc: Add compatible string for RK3506Heiko Stuebner1-0/+1
The dw-mshc controller in the RK3506 is compatible to the one first found in the RK3288 SoC, so add the RK3506 to the variant list. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-10-22dt-bindings: usb: Add Apple dwc3Sven Peter1-0/+80
Apple Silicon uses Synopsys DesignWare dwc3 based USB controllers for their Type-C ports. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neal Gompa <neal@gompa.dev> Signed-off-by: Sven Peter <sven@kernel.org> Link: https://patch.msgid.link/20251015-b4-aplpe-dwc3-v2-1-cbd65a2d511a@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-10-22dt-bindings: display: bridge: renesas,dsi-csi2-tx: Allow panel@ subnodeMarek Vasut1-2/+51
This controller can have both bridges and panels connected to it. In order to describe panels properly in DT, pull in dsi-controller.yaml and disallow only unevaluatedProperties, because the panel node is optional. Include example binding with panel. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Link: https://lore.kernel.org/r/20250904210147.186728-4-marek.vasut+renesas@mailbox.org
2025-10-22dt-bindings: soc: samsung: exynos-sysreg: add gs101 hsi0 and misc compatiblesPeter Griffin1-0/+4
Add dedicated compatibles for gs101 hsi0 and misc sysreg controllers to the documentation. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: André Draszik <andre.draszik@linaro.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251013-automatic-clocks-v1-1-72851ee00300@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-10-22dt-bindings: soc: samsung: exynos-sysreg: add power-domainsAndré Draszik1-0/+13
On gs101 only, sysreg can be part of a power domain, so we need to allow the relevant property 'power-domains' for the relevant compatibles google,gs101-*-sysreg. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20251010-power-domains-dt-bindings-soc-samsung-exynos-sysreg-v2-1-552f5787a3f3@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-10-22dt-bindings: net: dsa: yt921x: Add Motorcomm YT921x switch supportDavid Yang1-0/+167
The Motorcomm YT921x series is a family of Ethernet switches with up to 8 internal GbE PHYs and up to 2 GMACs. Signed-off-by: David Yang <mmyangfl@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20251017060859.326450-2-mmyangfl@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-10-21ASoC: spacemit: add i2s support to K1 SoCMark Brown1-0/+87
Merge series from Troy Mitchell <troy.mitchell@linux.spacemit.com>: On the K1 SoC, there is a full-duplex I2S controller. The I2S is programmable, with the sample width configurable to 8, 16, 18, or 32 bits. A dedicated FIFO is provided for transmit (TXFIFO) and another for receive (RXFIFO). In non-packed mode, both FIFOs are 32 entries deep and 32 bits wide, giving a total of 32 samples each. The register definitions can be found here[1] Link: https://developer.spacemit.com/documentation?token=Rn9Kw3iFHirAMgkIpTAcV2Arnkf#18.2-spi%2Fi2s [1] Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> --- Changes in v5: - Patch 1/2: - nothing - Patch 2/2: - dont't read sspsp value in spacemit_i2s_init() - set SSPSP_FSRT bit for DSP_A mode (was missing in previous version) - Link to v4: https://lore.kernel.org/all/20250921-k1-i2s-v4-0-4f819f50e468@linux.spacemit.com/ Changes in v4: - Patch 1/2: - nothing - Patch 2/2: - Only 8k, 16k and 48k rates are supported - Only 16-bit and 32-bit are supported - Use the runtime constraint API instead of modifying dai->driver - Link to v3: https://lore.kernel.org/r/20250911-k1-i2s-v3-0-57f173732f9c@linux.spacemit.com Changes in v3: - Patch 1/2: - simplify dma-names definition - Patch 2/2 - remove empty spacemit_i2s_remove() - move FSRT setup for DSP_A into switch-case in spacemit_i2s_set_fmt() - Link to v2: https://lore.kernel.org/r/20250828-k1-i2s-v2-0-09e7b40f002c@linux.spacemit.com Changes in v2: - Patch 1/2: - modify commit message - remove unused third cell from pdma dmas property - update SPDX license in spacemit,k1-i2s.yaml to (GPL-2.0-only OR BSD-2-Clause) - Patch 2/2: - modify commit message - reset_assert in dai_ops::remove - select CMA and DMA_CMA in Kconfig - use devm_reset_control_get_exclusive - Link to v1: https://lore.kernel.org/r/20250814-k1-i2s-v1-0-c31149b29041@linux.spacemit.com --- Troy Mitchell (2): ASoC: dt-bindings: Add bindings for SpacemiT K1 ASoC: spacemit: add i2s support for K1 SoC .../devicetree/bindings/sound/spacemit,k1-i2s.yaml | 87 ++++ sound/soc/Kconfig | 1 + sound/soc/Makefile | 1 + sound/soc/spacemit/Kconfig | 16 + sound/soc/spacemit/Makefile | 5 + sound/soc/spacemit/k1_i2s.c | 458 +++++++++++++++++++++ 6 files changed, 568 insertions(+) --- base-commit: 4f010aced22532eea2ef0d9a2f5db7c64a196fec change-id: 20250813-k1-i2s-115bf65eaac8 Best regards, -- Troy Mitchell <troy.mitchell@linux.spacemit.com>
2025-10-21ASoC: amd: ps: Propagate the PCI subsystem Vendor andMark Brown4-15/+38
Merge series from Simon Trimmer <simont@opensource.cirrus.com>: This series of two patches propagates the PCI subsystem Vendor and Device IDs so that they can be used by component drivers to differentiate firmware loads.
2025-10-21dt-bindings: mfd: Add binding for the PF1550 PMICSamuel Kayode1-0/+161
Add a DT binding document for pf1550 PMIC. This describes the core MFD device along with its children: regulators, charger and onkey. Signed-off-by: Samuel Kayode <samuel.kayode@savoirfairelinux.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Sean Nyekjaer <sean@geanix.com> Link: https://patch.msgid.link/20251001-pf1550-v12-1-a3302aa41687@savoirfairelinux.com Signed-off-by: Lee Jones <lee@kernel.org>
2025-10-21ASoC: dt-bindings: don't check node namesWolfram Sang1-1/+1
Node names are already and properly checked by the core schema. No need to do it again. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251020060951.30776-9-wsa+renesas@sang-engineering.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-21dt-bindings: soc: microchip: document the simple-mfd syscon on PolarFire SoCConor Dooley1-0/+47
"mss-top-sysreg" contains clocks, pinctrl, resets, an interrupt controller and more. At this point, only the reset controller child is described as that's all that is described by the existing bindings. The clock controller already has a dedicated node, and will retain it as there are other clock regions, so like the mailbox, a compatible-based lookup of the syscon is sufficient to keep the clock driver working as before, so no child is needed. There's also an interrupt multiplexing service provided by this syscon, for which there is work in progress at [1]. Link: https://lore.kernel.org/linux-gpio/20240723-uncouple-enforcer-7c48e4a4fefe@wendy/ [1] Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-10-21dt-bindings: gpu: img,powervr-rogue: Rework the allOf sectionMarek Vasut1-16/+24
Rework the current allOf: section such that all handling of clocks/clock-names properties happens first, and all handling of power-domains/power-domain-names happens second. This allows the allOf section to limit various GPU models to matching clocks count in the first half, and apply the same for power-domains count in the second half, without conflating the two limits together. This makes addition of GPU models with different clocks and power-domains count easier. No functional change intended. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Matt Coster <matt.coster@imgtec.com> Link: https://lore.kernel.org/r/20251018130147.12831-2-marek.vasut+renesas@mailbox.org Signed-off-by: Matt Coster <matt.coster@imgtec.com>
2025-10-21dt-bindings: gpu: img,powervr-rogue: Drop useless power domains itemsMarek Vasut1-5/+2
The power-domains items: list is not very informative, replace it with plain minItems/maxItems instead. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Matt Coster <matt.coster@imgtec.com> Link: https://lore.kernel.org/r/20251018130147.12831-1-marek.vasut+renesas@mailbox.org Signed-off-by: Matt Coster <matt.coster@imgtec.com>
2025-10-21dt-bindings: power: qcom,rpmpd: document the Kaanapali RPMh Power DomainsJishnu Prakash1-0/+1
Document the RPMh Power Domains on the Kaanapali Platform. Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-10-21dt-bindings: mmc: Add support for BCM72116 and BCM74371 SD host controllerKamal Dasu1-0/+2
Updating compatibility to support BCM72116 and BCM74371 SD host controller similar to other settop SoCs. Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
generated by cgit v1.2.3 (git 2.39.0) at 2026-05-20 18:21:08 +0300