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2026-01-10dt-bindings: soc: fsl: qe: Add an interrupt controller for QUICC Engine PortsChristophe Leroy (CS GROUP)1-0/+51
The QUICC Engine provides interrupts for a few I/O ports. This is handled via a separate interrupt ID and managed via a triplet of dedicated registers hosted by the SoC. Implement an interrupt driver for it so that those IRQs can then be linked to the related GPIOs. Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/7708243d6cca21004de8b3da87369c06dbee3848.1767804922.git.chleroy@kernel.org Signed-off-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org> [moved from bindings/soc/fsl/cpm_qe/ to bindings/interrupt-controller/ while applying]
2026-01-10dt-bindings: net: rockchip-dwmac: Allow "dma-coherent"Rob Herring (Arm)1-0/+2
The GMAC is coherent on RK3576, so allow the "dma-coherent" property. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://patch.msgid.link/20260108225318.1325114-2-robh@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-01-10Merge tag 'soc-fixes-6.19' of ↵Linus Torvalds2-2/+15
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC fixes from Arnd Bergmann: "The main code change is a revert of the Raspberry Pi RP1 overlay support that was decided to not be ready. The other fixes are all for devicetree sources: - ethernet configuration on ixp42x-actiontec-mi424wr is board revision specific - validation warning fixes for imx27/imx51/imx6, hikey960 and k3 - Minor corrections across imx8 boards, addressing all types of issues with interrups, dma, ethernet and clock settings, all simple one-line changes" * tag 'soc-fixes-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (25 commits) arm64: dts: hisilicon: hikey960: Drop "snps,gctl-reset-quirk" and "snps,tx_de_emphasis*" properties Documentation/process: maintainer-soc: Mark 'make' as commands Documentation/process: maintainer-soc: Be more explicit about defconfig arm64: dts: mba8mx: Fix Ethernet PHY IRQ support arm64: dts: imx8qm-ss-dma: correct the dma channels of lpuart arm64: dts: imx8mp: Fix LAN8740Ai PHY reference clock on DH electronics i.MX8M Plus DHCOM arm64: dts: freescale: tx8p-ml81: fix eqos nvmem-cells arm64: dts: freescale: moduline-display: fix compatible dt-bindings: arm: fsl: moduline-display: fix compatible ARM: dts: imx6q-ba16: fix RTC interrupt level arm64: dts: freescale: imx95-toradex-smarc: fix SMARC_SDIO_WP label position arm64: dts: freescale: imx95-toradex-smarc: use edge trigger for ethphy1 interrupt arm64: dts: add off-on-delay-us for usdhc2 regulator arm64: dts: imx8qm-mek: correct the light sensor interrupt type to low level ARM: dts: nxp: imx: Fix mc13xxx LED node names arm64: dts: imx95: correct I3C2 pclk to IMX95_CLK_BUSWAKEUP MAINTAINERS: Fix a linusw mail address arm64: dts: broadcom: rp1: drop RP1 overlay arm64: dts: broadcom: bcm2712: fix RP1 endpoint PCI topology misc: rp1: drop overlay support ...
2026-01-09dt-bindings: arm: rockchip: Add Orange Pi CM5 BaseLaurent Pinchart1-0/+6
The Orange Pi CM5 Base board is a carrier board for the Orange Pi CM5 compute module. It has 3 ethernet ports, 2 USB ports, one HDMI output and 4 CSI-2 inputs. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251027215637.20715-2-laurent.pinchart@ideasonboard.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2026-01-09dt-bindings: display: rockchip: Add no-hpd for dw-hdmi-qp controllerChris Morgan1-0/+6
Add an attribute of "no-hpd" for the Rockchip dw-hdmi-qp controller. This is used to describe implementations where the HPD pin is not connected or used for other purposes, such as in the RK3588S based Gameforce Ace which repurposed the GPIO for an additional face button. The "no-hpd" option was chosen to be consistent with other devices which already define this parameter for broken or missing hpd functionality. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patch.msgid.link/20251119225526.70588-2-macroalpha82@gmail.com
2026-01-09dt-bindings: gpu: img: Add AM62P SoC specific compatibleMichael Walle1-0/+2
The AM62P and the J722S features the same BXS-4 GPU as the J721S2. Add a new SoC specific compatible. Signed-off-by: Michael Walle <mwalle@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Matt Coster <matt.coster@imgtec.com> Link: https://patch.msgid.link/20251223124729.2482877-2-mwalle@kernel.org Signed-off-by: Matt Coster <matt.coster@imgtec.com>
2026-01-09spi: dt-bindings: axiado,ax3000-spi: Add binding for Axiado SPI DB controllerVladimir Moravcevic1-0/+73
Add documentation for Axiado Digital Block SPI controller. Co-developed-by: Prasad Bolisetty <pbolisetty@axiado.com> Signed-off-by: Prasad Bolisetty <pbolisetty@axiado.com> Signed-off-by: Vladimir Moravcevic <vmoravcevic@axiado.com> Link: https://patch.msgid.link/20260107-axiado-ax3000-soc-spi-db-controller-driver-v3-1-726e70cf19ad@axiado.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-01-09ASoC: dt-bindings: realtek,rt5640: Document port nodeJon Hunter1-0/+4
Various boards that use the rt5640 audio codec define a 'port' child node under the codec node to describe the interface between it and the SoC that it is connected to. The binding document for the rt5640 codec does not define the 'port' child node and so this is generating warnings when running the DTB checks for these boards. Add the 'port' node to the binding document for the rt5640 codec to fix this. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260108143158.351223-4-jonathanh@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-01-09ASoC: dt-bindings: realtek,rt5640: Update jack-detectJon Hunter1-0/+1
The device-tree property 'realtek,jack-detect-source' currently only permits values from 0-6. However, commit 2b9c8d2b3c89 ("ASoC: rt5640: Add the HDA header support") updated the Realtek rt5640 to support setting the 'realtek,jack-detect-source' to 7 to support the HDA header. The Tegra234 platforms currently set 'realtek,jack-detect-source' to 7 for the HDA header and this is causing a warning when building device-tree. audio-codec@1c (realtek,rt5640): realtek,jack-detect-source: 7 is not one of [0, 1, 2, 3, 4, 5, 6] Given that the driver already supports this settings, update the binding document for the rt5640 device to add the HDA header as a valid configuration for the 'realtek,jack-detect-source' property. Fixes: 2b9c8d2b3c89 ("ASoC: rt5640: Add the HDA header support") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260108143158.351223-3-jonathanh@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-01-09ASoC: dt-bindings: realtek,rt5640: Document mclkJon Hunter1-0/+8
Commit eba5a0bac211 ("ASoC: dt-bindings: realtek,rt5640: Convert to dtschema") converted the rt5640 dt-binding to yaml format but in the process dropped 'clock' and 'clock-names' properties that are used to specify the codec 'mclk'. This is causing DTB build warnings for boards that use this codec and define an 'mclk' in device-tree. Update the rt5640 binding document to add the optional mclk. Fixes: eba5a0bac211 ("ASoC: dt-bindings: realtek,rt5640: Convert to dtschema") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260108143158.351223-2-jonathanh@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-01-09dt-bindings: pinctrl: renesas,r9a09g077-pinctrl: Document GPIO IRQCosmin Tanislav1-0/+13
The Renesas RZ/T2H (R9A09G077) and Renesas RZ/N2H (R9A09G087) SoCs have IRQ-capable pins handled by the ICU, which forwards them to the GIC. The ICU supports 16 IRQ lines, the pins map to these lines arbitrarily, and the mapping is not configurable. Document the required properties to handle GPIO IRQ. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251205150234.2958140-4-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09dt-bindings: pinctrl: intel: keembay: fix typoAkiyoshi Kurita1-1/+1
Fix a typo in the documentation ("upto" -> "up to"). Signed-off-by: Akiyoshi Kurita <weibu@redadmin.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-01-09dt-bindings: arm: at91: add lan966 pcb8385 boardHoratiu Vultur1-2/+4
Add documentation for Microchip LAN9668 PCB8385 Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Link: https://lore.kernel.org/r/20251208083545.3642168-2-horatiu.vultur@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2026-01-09dt-bindings: soc: spacemit: k3: add clock supportYixun Lan2-5/+18
Add compatible strings for clock drivers to support Spacemit K3 SoC, also includes all the defined clock IDs. The SpacemiT K3 SoC clock IP is scattered over several different blocks, which are APBC, APBS, APMU, DCIU, MPMU, all of them are capable of generating clock and reset signals. APMU and MPMU have additional Power Domain management functionality. Following is a brief list that shows devices managed in each block: APBC: UART, GPIO, PWM, SPI, TIMER, I2S, IR, DR, TSEN, IPC, CAN APBS: various PPL clocks control APMU: CCI, CPU, CSI, ISP, LCD, USB, QSPI, DMA, VPU, GPU, DSI, PCIe, EMAC.. DCID: SRAM, DMA, TCM MPMU: various PLL1 derived clocks, UART, WATCHDOG, I2S Link: https://lore.kernel.org/r/20260108-k3-clk-v5-1-42a11b74ad58@gentoo.org Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Yixun Lan <dlan@gentoo.org>
2026-01-09dt-bindings: net: dsa: microchip: Make pinctrl 'reset' optionalFrank Li1-0/+3
Commit e469b87e0fb0d ("dt-bindings: net: dsa: microchip: Add strap description to set SPI mode") required both 'default' and 'reset' pinctrl states for all compatible devices. However, this requirement should be only applicable to KSZ8463. Make the 'reset' pinctrl state optional for all other Microchip DSA devices while keeping it mandatory for KSZ8463. Fix below CHECK_DTBS warnings: arch/arm64/boot/dts/freescale/imx8mp-skov-basic.dtb: switch@5f (microchip,ksz9893): pinctrl-names: ['default'] is too short from schema $id: http://devicetree.org/schemas/net/dsa/microchip,ksz.yaml# Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260106143620.126212-1-Frank.Li@nxp.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-01-08dt-bindings: display: rockchip,vop: Add compatible for rk3506Chaoyi Chen1-0/+1
The rk3506 VOP has adopted a new implementation. Add a new compatible string for it. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patch.msgid.link/20251106020632.92-5-kernel@airkyi.com
2026-01-08dt-bindings: display: rockchip,dw-mipi-dsi: Add compatible for rk3506Chaoyi Chen1-0/+2
Document a compatible string for the rk3506 mipi-dsi. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patch.msgid.link/20251106020632.92-4-kernel@airkyi.com
2026-01-08dt-bindings: arm: mediatek: Add Ezurio Tungsten entriesGary Bisson1-0/+2
Add device tree bindings support for the Ezurio Tungsten 510 (MT8370) SMARC [1] / Ezurio Tungsten 700 (MT8390) SMARC [2] + Universal SMARC carrier board [3]. [1] https://www.ezurio.com/product/tungsten510-smarc [2] https://www.ezurio.com/product/tungsten700-smarc [3] https://www.ezurio.com/system-on-module/accessories/universal-smarc-carrier Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Gary Bisson <bisson.gary@gmail.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2026-01-08dt-bindings: vendor-prefixes: Add Ezurio LLCGary Bisson1-0/+2
Ezurio is the new name of Laird Connectivity after it acquired Boundary Devices. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Gary Bisson <bisson.gary@gmail.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2026-01-08dt-bindings: leds: Add LP5860 LED controllerSteffen Trumtrar1-0/+111
The LP5860 is a LED matrix driver with 18 constant current sinks and 11 scan switches for 198 LED dots: * Supply range from 2.7 V to 5.5 V * 0.1mA - 50mA per current sink * 1MHz I2C and 12MHz SPI control interface * 8-bit analog dimming * 8/16-bit PWM dimming * individual ON and OFF control for each LED dot * globat 3-bit Maximum Current setting for all LED dots * individual LED dot open/short detection Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251201-v6-14-topic-ti-lp5860-v6-1-be9a21218157@pengutronix.de Signed-off-by: Lee Jones <lee@kernel.org>
2026-01-08dt-bindings: soc: mediatek: dvfsrc: Document clockNicolas Frattaroli1-0/+6
The DVFSRC hardware has a clock on all platforms. Instead or proliferating the culture of omitting clock descriptions in the clock controller drivers or marking them critical instead of declaring these types of relationships, add this one to the binding. Any device that wishes to use this binding should figure out their incomplete or incorrect clock situation first before piling more features on top. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2026-01-08dt-bindings: ata: ahci-platform: Drop unnecessary select schemaRob Herring (Arm)1-20/+0
The "select" schema is not necessary. It looks like it is there to prevent matching on "generic-ahci" compatible, but that's not necessary because this is the only place "generic-ahci" compatible is present. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
2026-01-08dt-bindings: arm: aspeed: add ASRock Rack ALTRAD8 boardRebecca Cran1-0/+1
Document ASRock Rack ALTRAD8 (ALTRAD8UD-1L2T and ALTRAD8UD2-1L2Q) compatibles. Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Tan Siewert <tan.siewert@hetzner.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20251218161816.38155-2-rebecca@bsdio.com [arj: Drop erroneous Tested-by tag from Tan] Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2026-01-08dt-bindings: arm: aspeed: Add compatible for Facebook Anacapa BMCPeter Shen1-0/+1
This patch adds the compatible string for the Facebook Anacapa BMC which uses an Aspeed AST2600 SoC. This is required before adding the board's device tree source file. Signed-off-by: Peter Shen <sjg168@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> [arj: Insert provided Acked-by tag from Krzysztof, drop misspelled one] Link: https://lore.kernel.org/linux-aspeed/259e917f-0570-40d6-983f-bfe9d77444a7@kernel.org/ Link: https://patch.msgid.link/20251219091632.1598603-2-sjg168@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2026-01-07dt-bindings: i2c: atmel,at91sam: add microchip,lan9691-i2cRobert Marko1-0/+1
Document Microchip LAN969x I2C compatible. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Andi Shyti <andi.shyti@kernel.org> Signed-off-by: Andi Shyti <andi.shyti@kernel.org> Link: https://lore.kernel.org/r/20251229184004.571837-6-robert.marko@sartura.hr
2026-01-07dt-bindings: i2c: spacemit: add optional resetsEncrow Thorne1-0/+3
The I2C controller requires a reset to ensure it starts from a clean state. Add the 'resets' property to support this hardware requirement. Signed-off-by: Encrow Thorne <jyc0019@gmail.com> Reviewed-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Andi Shyti <andi.shyti@kernel.org> Link: https://lore.kernel.org/r/20251230150653.42097-1-jyc0019@gmail.com
2026-01-07Merge tag 'aspeed-6.20-devicetree-0' of ↵Arnd Bergmann1-0/+1
https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt First batch of ASPEED Arm devicetree changes for 6.20 New platforms: - NVIDIA MSX4 BMC The NVIDIA MSX4 HPM (host platform module) is a reference board for managing up to 8 PCIe connected NVIDIA GPUs via ConnectX-8 (CX8) SuperNICs. The BMC manages all GPUs and CX8s for both telemetry and firmware update via MCTP over USB. The host CPUs are dual socket Intel Granite Rapids processors. For more detail on this architecture: https://developer.nvidia.com/blog/nvidia-connectx-8-supernics-advance-ai-platform-architecture-with-pcie-gen6-connectivity/ Updated platforms: - ast2600-evb (ASPEED): Various tidy-ups to address binding warnings - bletchley (Meta): Watchdog fix, tidy-ups to address binding warnings - clemente (Meta): HDD LED fix, GPIO line names, EEPROMs - harma (Meta): fanboard presence GPIO - santabarbara (Meta): IPMB, GPIO line names, additional IO expander * tag 'aspeed-6.20-devicetree-0' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux: ARM: dts: aspeed: bletchley: Fix ADC vref property names ARM: dts: aspeed: bletchley: Remove unused i2c13 property ARM: dts: aspeed: bletchley: Remove unused pca9539 properties ARM: dts: aspeed: bletchley: Fix SPI GPIO property names ARM: dts: aspeed: bletchley: Use generic node names ARM: dts: aspeed: g6: Drop clocks property from arm,armv7-timer ARM: dts: aspeed: ast2600-evb: Tidy up A0 work-around for UART5 ARM: dts: aspeed: g6: Drop unspecified aspeed,ast2600-udma node ARM: dts: aspeed: Drop syscon compatible from EDAC in g6 dtsi ARM: dts: aspeed: Use specified wp-inverted property for AST2600 EVB ARM: dts: aspeed: Remove sdhci-drive-type property from AST2600 EVB ARM: dts: aspeed: Add NVIDIA MSX4 HPM dt-bindings: arm: aspeed: Add NVIDIA MSX4 board ARM: dts: aspeed: clemente: move hdd_led to its own gpio-leds group ARM: dts: aspeed: clemente: add gpio line name to io expander ARM: dts: aspeed: santabarbara: Enable ipmb device for OCP debug card ARM: dts: aspeed: santabarbara: Add swb IO expander and gpio line names ARM: dts: aspeed: clemente: Add EEPROMs for boot and data drive FRUs ARM: dts: aspeed: harma: add fanboard presence sgpio ARM: dts: aspeed: bletchley: remove WDTRST1 assertion from wdt1 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-07Merge tag 'imx-fixes-6.19' of ↵Arnd Bergmann1-1/+8
https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes i.MX fixes for 6.19: - A mba8mx fix from Alexander Stein to correct Ethernet PHY IRQ trigger type - An i.MX95 fix from Carlos Song to correct I3C2 pclk - A couple of imx8qm-mek changes from Haibo Chen to fix light sensor interrupt type and usdhc2 regulator configuration - An imx6q-ba16 change from Ian Ray to fix RTC interrupt level - An imx8mp-dhcom-som change from Marek Vasut to fix sporadic Ethernet link bouncing caused by interruptions on the PHY reference clock - A couple of imx8mp-tx8p changes from Maud Spierings to fix compatible and eqos nvmem-cells - An ARM i.MX fix from Rob Herring to correct mc13xxx LED node names - An imx8qm-ss-dma change from Sherry Sun to correct DMA channels for LPUART - A couple of imx95-toradex-smarc changes from Vitor Soares to fix ethphy1 interrupt and SMARC_SDIO_WP label position * tag 'imx-fixes-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: mba8mx: Fix Ethernet PHY IRQ support arm64: dts: imx8qm-ss-dma: correct the dma channels of lpuart arm64: dts: imx8mp: Fix LAN8740Ai PHY reference clock on DH electronics i.MX8M Plus DHCOM arm64: dts: freescale: tx8p-ml81: fix eqos nvmem-cells arm64: dts: freescale: moduline-display: fix compatible dt-bindings: arm: fsl: moduline-display: fix compatible ARM: dts: imx6q-ba16: fix RTC interrupt level arm64: dts: freescale: imx95-toradex-smarc: fix SMARC_SDIO_WP label position arm64: dts: freescale: imx95-toradex-smarc: use edge trigger for ethphy1 interrupt arm64: dts: add off-on-delay-us for usdhc2 regulator arm64: dts: imx8qm-mek: correct the light sensor interrupt type to low level ARM: dts: nxp: imx: Fix mc13xxx LED node names arm64: dts: imx95: correct I3C2 pclk to IMX95_CLK_BUSWAKEUP Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-07Merge branch '20260107-kaanapali-mmcc-v3-v3-0-8e10adc236a8@oss.qualcomm.com' ↵Bjorn Andersson5-0/+76
into clk-for-6.20 Merge the Kaanapali camera, display, GPU, and video clock controller bindings through a topic branch, to allow making them available to the DeviceTree branch as well.
2026-01-07dt-bindings: clock: qcom: document the Kaanapali GPU Clock ControllerTaniya Das2-0/+65
Qualcomm GX(graphics) is a clock controller which has PLLs, clocks and Power domains (GDSC), but the requirement from the SW driver is to use the GDSC power domain from the clock controller to recover the GPU firmware in case of any failure/hangs. The rest of the resources of the clock controller are being used by the firmware of GPU. This module exposes the GDSC power domains which helps the recovery of Graphics subsystem. Add bindings documentation for the Kaanapali Graphics Clock and Graphics power domain Controller for Kaanapali SoC. Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260107-kaanapali-mmcc-v3-v3-7-8e10adc236a8@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-07dt-bindings: clock: qcom: Add Kaanapali video clock controllerTaniya Das1-0/+3
Add device tree bindings for the video clock controller on Qualcomm Kaanapali SoC. Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260107-kaanapali-mmcc-v3-v3-6-8e10adc236a8@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-07dt-bindings: clock: qcom: Add support for CAMCC for KaanapaliTaniya Das1-0/+6
Update the compatible and the bindings for CAMCC support on Kaanapali SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260107-kaanapali-mmcc-v3-v3-5-8e10adc236a8@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-07dt-bindings: clock: qcom: document Kaanapali DISPCC clock controllerTaniya Das1-0/+2
Document device tree bindings for display clock controller for Qualcomm Kaanapali SoC. Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260107-kaanapali-mmcc-v3-v3-4-8e10adc236a8@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-07Merge branch '20251202-sm8750_camcc-v1-2-b3f7ef6723f1@oss.qualcomm.com' into ↵Bjorn Andersson1-0/+5
clk-for-6.20 Merge the SM8750 camera clock controller binding through a topic branch, in order to allow the defines to made availabe to the DeviceTree branch as well.
2026-01-07dt-bindings: clock: qcom: Add camera clock controller for SM8750 SoCTaniya Das1-0/+5
Add device tree bindings for the camera clock controller on Qualcomm SM8750 platform. The camera clock controller is split between camcc and cambist. The cambist controls the mclks of the camera clock controller. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251202-sm8750_camcc-v1-2-b3f7ef6723f1@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-07dt-bindings: clock: qcom: Add SDM439 Global Clock ControllerBarnabás Czémán1-2/+3
Add devicetree bindings for the global clock controller on Qualcomm SDM439 platform. Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20251117-gcc-msm8940-sdm439-v2-3-4af57c8bc7eb@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-07dt-bindings: clock: qcom: Add MSM8940 Global Clock ControllerBarnabás Czémán1-2/+3
Add devicetree bindings for the global clock controller on Qualcomm MSM8940 platform. Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20251117-gcc-msm8940-sdm439-v2-1-4af57c8bc7eb@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-07dt-bindings: remoteproc: Add HSM M4F core on TI K3 SoCsBeleswar Padhi1-0/+72
Some of the TI K3 family of SoCs have a HSM (High Security Module) M4F core in the Wakeup Voltage Domain which could be used to run secure services like Authentication. Add the device tree bindings document for this HSM M4F core. The added example illustrates the DT node for the HSM core present on K3 J722S SoC. Signed-off-by: Beleswar Padhi <b-padhi@ti.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260106104755.948086-2-b-padhi@ti.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
2026-01-07dt-bindings: usb: qcom,dwc3: Correct MSM8994 interruptsKrzysztof Kozlowski2-2/+2
According to the reference manual, MSM8994 does have QUSB2 PHY and does not have DP/DM IRQs interrupts. It is also logical it has the same constraints as similar device: MSM8996. This fixes dtbs_check warnings like: msm8994-sony-xperia-kitakami-karin.dtb: usb@f92f8800 (qcom,msm8994-dwc3): interrupt-names:1: 'hs_phy_irq' was expected msm8994-sony-xperia-kitakami-karin.dtb: usb@f92f8800 (qcom,msm8994-dwc3): interrupt-names:2: 'dp_hs_phy_irq' was expected msm8994-sony-xperia-kitakami-karin.dtb: usb@f92f8800 (qcom,msm8994-dwc3): interrupt-names:3: 'dm_hs_phy_irq' was expected Fixes: 53c6d854be4e ("dt-bindings: usb: dwc3: Clean up hs_phy_irq in binding") Fixes: 6e762f7b8edc ("dt-bindings: usb: Introduce qcom,snps-dwc3") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260106185012.19551-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-01-07dt-bindings: usb: qcom,dwc3: Correct IPQ5018 interruptsKrzysztof Kozlowski2-2/+2
According to reference manual, IPQ5018 does not have QUSB2 PHY and its interrupts should rather match ones used in IPQ5332 (so power_event, eud_dmse_int_mx, eud_dpse_int_mx). Fixes: 53c6d854be4e ("dt-bindings: usb: dwc3: Clean up hs_phy_irq in binding") Fixes: 6e762f7b8edc ("dt-bindings: usb: Introduce qcom,snps-dwc3") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260106185012.19551-3-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-01-07dt-bindings: usb: Add Socionext Uniphier DWC3 controllerRob Herring (Arm)1-0/+89
The Socionext Uniphier DWC3 controller binding is already in use, but undocumented. It's a straight-forward binding similar to other DWC3 bindings. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://patch.msgid.link/20260105162418.2842825-1-robh@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-01-07dt-bindings: usb: Add Microchip LAN969x supportRobert Marko1-0/+66
Microchip LAN969x has DWC3 compatible controller, though limited to 2.0(HS) speed, so document it. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251229184004.571837-2-robert.marko@sartura.hr Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-01-07dt-bindings: pinctrl: sunxi: Allow pinmux sub-pattern with leading numbersChen-Yu Tsai1-1/+1
The pattern for pinmux node names is typically the peripheral name and instance number, followed by pingroup name if there are multiple options. Normally the instance number is directly appended to the peripheral name, like "mmc0" or "i2c2". But if the peripheral name ends with a number, then it becomes confusing. On the A20, the PS2 interface controller has two instances. This produces pinmux node names like "ps2-0-pins". Make the sub-pattern "[0-9]-" valid to fit this pattern. Avoid having to confusing "ps20-pins" name. Signed-off-by: Chen-Yu Tsai <wens@kernel.org> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-01-07dt-bindings: pinctrl: spacemit: add K3 SoC supportYixun Lan1-1/+9
Add new compatible string for SpacemiT K3 SoC, the pinctrl IP shares almost same logic with previous K1 generation, but has different register offset and pin configuration, for example the drive strength and schmitter trigger settings has been changed. Signed-off-by: Yixun Lan <dlan@gentoo.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-01-07dt-bindings: pinctrl: spacemit: convert drive strength to schema formatYixun Lan1-4/+8
In order to better extend the pinctrl support for future new SoC, convert drive strength setting from free form text to more standard schema format. Signed-off-by: Yixun Lan <dlan@gentoo.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-01-07dt-bindings: PCI: mediatek-gen3: Add MT7981 PCIe compatibleSjoerd Simons1-0/+1
Add compatible string for MediaTek MT7981 PCIe Gen3 controller. The MT7981 PCIe controller is compatible with the MT8192 PCIe controller. Signed-off-by: Sjoerd Simons <sjoerd@collabora.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251223-openwrt-one-network-v5-1-7d1864ea3ad5@collabora.com
2026-01-07regulator: dt-bindings: qcom,wcn3990-pmu: describe PMUs on WCN39xxDmitry Baryshkov1-0/+100
WCN3990 and other similar WiFi/BT chips incorporate a simple on-chip PMU (clearly described as such in the documentation). Provide DT schema covering other Qualcomm WiFi/BT chips to cover these devices too. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Acked-by: Mark Brown <broonie@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260106-wcn3990-pwrctl-v2-1-0386204328be@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-01-06ASoC: ES8389: Add some members and updateMark Brown1-0/+12
Merge series from Zhang Yi <zhangyi@everest-semi.com>: To improve the codec's performance, add members related to power and version, and modify the configuration.
2026-01-06dt-bindings: arm: rockchip: fix description for Radxa CM5FUKAUMI Naoki1-7/+7
"Radxa CM5" is the correct name[1], so fix the description. While at it, move the CM5 entry after the CM3I. [1] https://dl.radxa.com/cm5/radxa_cm5_product_brief.pdf Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251229045838.2917-2-naoki@radxa.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2026-01-06dt-bindings: arm: rockchip: fix description for Radxa CM3IFUKAUMI Naoki1-1/+1
"Radxa CM3I" is the correct name[1], so fix the description. [1] https://dl.radxa.com/cm3i/docs/hw/radxa_cm3i_product_brief.pdf Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251229045838.2917-1-naoki@radxa.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
generated by cgit v1.2.3 (git 2.39.0) at 2026-05-17 13:01:06 +0300