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2026-03-10dt-bindings: display: simple: Add Powertip PH800480T032-ZHC19 panelFlorijan Plohl1-0/+2
Add Powertip PH800480T032-ZHC19 7" LCD-TFT RGB panel compatible string. Signed-off-by: Florijan Plohl <florijan.plohl@norik.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260217123759.169317-1-florijan.plohl@norik.com
2026-03-10dt-bindings: display: simple: add EDT ET057023UDBA panelMarco Felsch1-0/+2
Add EDT ET057023UDBA 5.7" 24-bit 640x480 DPI panel. Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260119-v6-18-topic-panel-simple-et057023udba-v2-1-3c73f0c9d87a@pengutronix.de
2026-03-10dt-bindings: leds: sun50i-a100: Add compatible for Allwinner A523 SoCChen-Yu Tsai1-0/+1
The Allwinner A523 SoC family features an identical LED controller as found on the A100. Add a SoC-specific compatible for it, with fallback to the A100 one. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20260302152724.3197587-2-wens@kernel.org Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2026-03-10ASoC: ti: davinci-mcasp: McASP code cleanup and clkMark Brown4-1/+3
Merge series from Sen Wang <sen@ti.com>: Just two minor patches that aim to tidy up the code a little bit, as well as fix the aux_div selection in davinci_mcasp_calc_clk_div() for mid-range dividers (33 <= div <= 4096). Sen Wang (2): ASoC: ti: davinci-mcasp: extract mcasp_is_auxclk_enabled() helper ASoC: ti: davinci-mcasp: improve aux_div selection for mid-range dividers sound/soc/ti/davinci-mcasp.c | 45 +++++++++++++++++++++++++----------- 1 file changed, 31 insertions(+), 14 deletions(-) -- 2.43.0
2026-03-10dt-bindings: pinctrl: qcom: Add Milos LPASS LPI pinctrlLuca Weiss1-0/+109
Add bindings for pin controller in Milos Low Power Audio SubSystem (LPASS). Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-03-10dt-bindings: thermal: lmh: Add SDM670 compatibleRichard Acayan1-0/+3
Document the SDM670 LMh. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260310002037.1863-3-mailingradian@gmail.com Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
2026-03-10dt-bindings: thermal: tsens: add SDM670 compatibleRichard Acayan1-0/+1
Add the compatible for the thermal sensors on the SDM670. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260310002037.1863-2-mailingradian@gmail.com Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
2026-03-10dt-bindings: arm: ti: Drop Kontron SMARC-sAM67 moduleMichael Walle1-1/+0
I was just informed that this product is discontinued (without being ever released to the market). Pull the plug and let's not waste any more maintainers time and revert commit 22e1d0d8cda7 ("dt-bindings: arm: ti: Add Kontron SMARC-sAM67 module"). Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://patch.msgid.link/20260302122540.1377444-5-mwalle@kernel.org Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-03-10dt-bindings: mfd: sl28cpld: Drop sa67mcu compatibleMichael Walle1-6/+1
I was just informed that this product is discontinued (without being ever released to the market). Pull the plug and let's not waste any more maintainers time and revert commit a598ae45f48d ("dt-bindings: mfd: sl28cpld: Add sa67mcu compatible"). Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://patch.msgid.link/20260302122540.1377444-4-mwalle@kernel.org Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2026-03-10dt-bindings: leds: sc2731: Add compatible for SC2730Otto Pflüger1-1/+6
The LED controller found in the SC2730 PMIC is compatible with the one found in the SC2731 PMIC. Signed-off-by: Otto Pflüger <otto.pflueger@abscue.de> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260222-sc27xx-mfd-cells-v1-2-69526fe74c77@abscue.de Signed-off-by: Lee Jones <lee@kernel.org>
2026-03-10dt-bindings: gpio: realtek-otto: add rtl9607 compatibleRustam Adilov1-0/+1
Add the "realtek,rtl9607-gpio" compatible for GPIO nodes on the RTL9607C SoC series. Signed-off-by: Rustam Adilov <adilov@disroot.org> Reviewed-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Sander Vanheule <sander@svanheule.net> Link: https://patch.msgid.link/20260305161106.15999-2-adilov@disroot.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-03-10dt-bindings: clk: tenstorrent: Add tenstorrent,atlantis-prcm-rcpuAnirudh Srinivasan1-0/+54
Document bindings for Tenstorrent Atlantis PRCM that manages clocks and resets. This block is instantiated multiple times in the SoC. This commit documents the clocks from the RCPU PRCM block. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com> Reviewed-by: Drew Fustini <fustini@kernel.org> Signed-off-by: Drew Fustini <fustini@kernel.org>
2026-03-09dt-bindings: arm: fsl: add bindings for TQMa8xAlexander Stein1-0/+10
TQMa8x is a SOM family using NXP i.MX8QM CPU family MBa8x is an evaluation mainboard for this SOM. Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-03-09dt-bindings: fsl: imx7ulp-smc1: Add #clock-cells propertyPeng Fan1-0/+5
The SMC1 block on i.MX7ULP is already used as a clock provider in imx7ulp.dtsi, but the corresponding dt-binding schema does not define the required '#clock-cells' property. This results in CHECK_DTBS schema validation errors. Functionally, SMC1 controls the CPU run mode configuration: - 00b: Normal Run (RUN) - 10b: Very-Low-Power Run (VLPR) - 11b: High-Speed Run (HSRUN) These run modes determine the effective CPU operating point, and their programming is tied to the OPP table. Add the missing `#clock-cells` definition so the dt-binding schema is consistent with the DTS and validates correctly. Fixes: 8ba41d6bd9893 ("dt-bindings: fsl: Convert i.MX7ULP PM to json-schema") Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-03-09dt-bindings: mmc: fsl-imx-esdhc: add S32N79 supportCiprian Marian Costea1-0/+1
Add compatible string "nxp,s32n79-usdhc" for the uSDHC controller found in NXP S32N79 series automotive SoCs. Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-09dt-bindings: mmc: loongson,ls2k0500-mmc: Add compatible for Loongson-2K0300Binbin Zhou1-0/+1
Add "loongson,ls2k0300-mmc" dedicated compatible to represent the eMMC/SD/SDIO controller interface of the Loongson-2K0300 chip. Its hardware design is similar to that of the Loongson-2K2000, but it suffers from hardware defects such as missing CMD48 interrupts. Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-09mmc: Merge the immutable mux branch into nextUlf Hansson1-0/+6
The mux branch contains updates to the mux core along with some corresponding changes for a couple of consumer drivers, including an mmc driver. Let's merge it into the next branch to get it tested and queued for the next release. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-09dt-bindings: mmc: renesas,sdhi: Add mux-states propertyJosua Mayer1-0/+6
Add mux controller support for data or control lines that are muxed between a host and multiple cards. There are several devices supporting a choice of eMMC or SD on a single board by both dip switch and gpio, e.g. Renesas RZ/G2L SMARC SoM and SolidRun RZ/G2L SoM. In-tree dts for the Renesas boards currently rely on preprocessor macros and gpio hogs to describe the respective cards. By adding mux-states property to sdhi controller description, boards can correctly describe the mux that already exists in hardware - and drivers can coordinate between mux selection and probing for cards. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-09dt-bindings: i2c: dw: Update maintainerMika Westerberg1-1/+1
Jarkko does now work for Intel anymore and since I'm currently maintaining this driver, update my contact information here to make sure patches get Cc'd to me as well. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> (internally) Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
2026-03-09dt-bindings: dma: renesas,rz-dmac: document RZ/{T2H,N2H}Cosmin Tanislav1-18/+82
The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have three DMAC instances. Compared to the previously supported RZ/V2H, these SoCs are missing the error interrupt line and the reset lines, and they use a different ICU IP. Document them, and use RZ/T2H as a fallback for RZ/N2H as the DMACs are entirely compatible. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260105114445.878262-4-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dt-bindings: soc: cix: document the syscon on Sky1 SoCGary Yang1-0/+42
There are two system control on Cix sky1 Soc. One is located in S0 domain, and the other is located in S5 domain. The system control contains resets, usb typeC and more. At this point, only the reset controller is embedded as usb typeC uses it by phandle. Signed-off-by: Gary Yang <gary.yang@cixtech.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2026-03-09ASoC: dt-bindings: cirrus,cs42l43: Add CS42L43B variantMaciej Strozek1-0/+3
CS42L43B variant adds dedicated PDM interface, SoundWire Clock Gearing support and more decimators to ISRCs. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Maciej Strozek <mstrozek@opensource.cirrus.com> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://patch.msgid.link/20260306152829.3130530-3-mstrozek@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-03-09dt-bindings: gpio: gpio-delay: Use Alexander's emailKrzysztof Kozlowski1-1/+1
Group/anonymous mailboxes are not accepted for bindings maintainers, so switch from such linux @TQ mailbox to Alexander's email. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> Link: https://patch.msgid.link/20260212110905.52842-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-03-08dt-bindings: firmware: arm,scmi: Document arm,no-completion-irq propertyMarek Vasut1-0/+10
Document new property arm,no-completion-irq . This optional property is intended for hardware that does not generate completion interrupts and can be used to unconditionally enable forced polling mode of operation. With this property set, such implementations which do not generate interrupts can be interacted with, until they are fixed to generate interrupts properly. Note that, because the original base protocol exchange also requires some sort of completion mechanism, it is not possible to query SCMI itself for this property and it must be described in DT. While this does look a bit like policy, the SCMI provider is part of the hardware, hence DT. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Cristian Marussi <cristian.marussi@arm.com> Message-Id: <20260117010241.186685-1-marek.vasut+renesas@mailbox.org> Signed-off-by: Sudeep Holla <sudeep.holla@kernel.org>
2026-03-07Merge tag 'hwmon-for-v7.0-rc3' of ↵Linus Torvalds1-1/+0
git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging Pull hwmon fixes from Guenter Roeck: - Fix initialization commands for AHT20 - Correct a malformed email address (emc1403) - Check the it87_lock() return value - Fix inverted polarity (max6639) - Fix overflows, underflows, sign extension, and other problems in macsmc - Fix stack overflow in debugfs read (pmbus/q54sj108a2) - Drop support for SMARC-sAM67 (discontinued and never released to market) * tag 'hwmon-for-v7.0-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging: hwmon: (pmbus/q54sj108a2) fix stack overflow in debugfs read hwmon: (max6639) fix inverted polarity dt-bindings: hwmon: sl28cpld: Drop sa67mcu compatible hwmon: (it87) Check the it87_lock() return value Revert "hwmon: add SMARC-sAM67 support" hwmon: (aht10) Fix initialization commands for AHT20 hwmon: (emc1403) correct a malformed email address hwmon: (macsmc) Fix overflows, underflows, and sign extension hwmon: (macsmc) Fix regressions in Apple Silicon SMC hwmon driver
2026-03-07dt-bindings: arm: atmel,at91rm9200-sdramc: convert to DT schemaAkhila YS2-20/+66
Convert RAMC SDRAM/DDR controller binding to YAML format. Signed-off-by: Akhila YS <akhilayalmati@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20260227-arm-microchip-v4-5-7e2ae1c5b5d6@gmail.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2026-03-07dt-bindings: arm: atmel,at91rm9200-st: convert to DT schemaAkhila YS2-9/+69
Convert System Timer binding to YAML format. Changes during conversion: - Add "#address-cells" and "#size-cells" to the properties and required as watchdog is defined as a child node to the timer parent node. - Define watchdog as a pattern property along with unit address in examples. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Akhila YS <akhilayalmati@gmail.com> Link: https://lore.kernel.org/r/20260227-arm-microchip-v4-4-7e2ae1c5b5d6@gmail.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2026-03-07dt-bindings: arm: microchip,sam9x60-pit64b : convert to DT schemaAkhila YS2-8/+68
Convert Atmel Periodic interval timer of 64bit (PIT64b) binding to YAML format. Changes during conversion: - Add missing compatible "microchip,sama7g5-pit64b" along with a fallback compatible "microchip,sam9x60-pit64b". Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Akhila YS <akhilayalmati@gmail.com> Link: https://lore.kernel.org/r/20260227-arm-microchip-v4-3-7e2ae1c5b5d6@gmail.com [claudiu.beznea: alphanumerically sort the enum entries] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2026-03-07dt-bindings: arm: atmel,at91sam9260-pit: convert to DT schemaAkhila YS2-6/+49
Convert Atmel Periodic interval timer (PIT) binding to YAML format. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Akhila YS <akhilayalmati@gmail.com> Link: https://lore.kernel.org/r/20260227-arm-microchip-v4-2-7e2ae1c5b5d6@gmail.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2026-03-07dt-bindings: arm: microchip,sama7g5-chipid : convert to DT schemaAkhila YS2-5/+41
Convert Atmel system registers binding to YAML format. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Akhila YS <akhilayalmati@gmail.com> Link: https://lore.kernel.org/r/20260227-arm-microchip-v4-1-7e2ae1c5b5d6@gmail.com [claudiu.beznea: alphanumerically sort the enum entries] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2026-03-07dt-bindings: powerpc: Add Freescale/NXP MPC83xx SoCsJ. Neuschäfer1-0/+93
Add a new binding for MPC83xx platforms, describing the board compatible strings used in currently existing device trees. Note that the SoC bus is called immr@... in many existing devicetrees, but this contradicts the simple-bus binding. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: J. Neuschäfer <j.ne@posteo.net> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Link: https://patch.msgid.link/20260303-ppcyaml-soc-v5-1-2982d5a857bc@posteo.net
2026-03-07dt-bindings: crypto: qcom,inline-crypto-engine: Document the Eliza ICEAbel Vesa1-0/+1
Document the Inline Crypto Engine (ICE) on the Eliza platform. Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2026-03-06Merge tag 'sound-7.0-rc3' of ↵Linus Torvalds2-0/+2
git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound Pull sound fixes from Takashi Iwai: "Again a collection of device-specific fixes. Most of changes are fairly small device-specific quirks of fixes for HD- and USB-audio, ASoC Intel, AMD, fsl, Cirrus and co. The only large LOC is for plumbing ASoC ACP driver to add the Cirrus Logic codec support, so this one is also just adding some tables" * tag 'sound-7.0-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (21 commits) ALSA: us122l: drop redundant interface references ASoC: amd: yc: Add DMI quirk for ASUS EXPERTBOOK PM1503CDA ASoC: dt-bindings: renesas,rz-ssi: Document RZ/G3L SoC ASoC: SDCA: Add allocation failure check for Entity name ALSA: hda/senary: Ensure EAPD is enabled during init ALSA: hda/senary: Use codec->core.afg for GPIO access ALSA: doc: usb-audio: Add doc for QUIRK_FLAG_SKIP_IFACE_SETUP ASoC: dt-bindings: tegra: Add compatible for Tegra238 sound card ALSA: hda/hdmi: Add Tegra238 HDA codec device ID ASoC: cs35l56: Suppress pointless warning about number of GPIO pulls ASoC: amd: acp: Add ACP6.3 match entries for Cirrus Logic parts ASoC: Intel: sof_sdw: Add quirk for Alienware Area 51 (2025) 0CCD SKU ASoC: rt1321: fix DMIC ch2/3 mask issue ASoC: cs35l56: Only patch ASP registers if the DAI is part of a DAIlink ASoC: fsl_easrc: Fix event generation in fsl_easrc_iec958_set_reg() ASoC: fsl_easrc: Fix event generation in fsl_easrc_iec958_put_bits() ALSA: firewire: dice: Fix printf warning with W=1 ALSA: hda/tas2781: A workaround solution to lower-vol issue among lower calibrated-impedance micro-speaker on TAS2781 ALSA: hda/realtek: Add quirk for HP Pavilion 15-eh1xxx to enable mute LED ALSA: usb-audio: Add iface reset and delay quirk for AB13X USB Audio ...
2026-03-06Merge branch 'icc-qcs8300' into icc-nextGeorgi Djakov1-0/+63
This series enables QoS configuration for QNOC type device which can be found on QCS8300 platform. It enables QoS configuration for master ports with predefined priority and urgency forwarding. This helps in prioritizing the traffic originating from different interconnect masters at NOC (Network On Chip). The system may function normally without this feature. However, enabling QoS helps optimize latency and bandwidth across subsystems like CPU, GPU, and multimedia engines, which becomes important in high-throughput scenarios. This is a feature aimed at performance enhancement to improve system performance under concurrent workloads. * icc-qcs8300 dt-bindings: interconnect: qcom,qcs8300-rpmh: add clocks property to enable QoS interconnect: qcom: qcs8300: enable QoS configuration Link: https://msgid.link/20260127090116.1438780-1-odelu.kukatla@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06dt-bindings: soc: renesas: renesas,rzg2l-sysc: Document RZ/G3L SoCBiju Das1-0/+1
Document RZ/G3L (R9A08G046) SYSC bindings. The SYSC block found on the RZ/G3L SoC is similar to the one found on RZ/G3S. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260203103031.247435-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-03-06dt-bindings: soc: renesas: Document RZ/G3L SoC variants, SMARC SoM and ↵Biju Das1-0/+13
Carrier-II EVK Document Renesas RZ/G3L (R9A08G046) SoC variants and the Renesas RZ/G3L SMARC Carrier-II EVK board which is based on the Renesas RZ/G3L SMARC SoM. The RZ/G3L SMARC Carrier-II EVK consists of an RZ/G3L SoM module and a SMARC Carrier-II carrier board. The SoM module sits on top of the carrier board. Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260203103031.247435-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-03-06Merge branch 'icc-mahua' into icc-nextGeorgi Djakov1-25/+111
Mahua is a derivative of the Glymur SoC and shares a significant portion of its interconnect topology with Glymur. As such, this series extends the existing Glymur interconnect driver to support Mahua, reusing common definitions where possible and adding SoC-specific configurations where necessary. * icc-mahua dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Mahua SoC interconnect: qcom: glymur: Add Mahua SoC support Link: https://msgid.link/20260209-mahua_icc-v3-0-c65f3dfd72c8@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06Merge branch 'icc-eliza' into icc-nextGeorgi Djakov2-0/+143
Add interconnect support for the Qualcomm Eliza SoC. * icc-eliza dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Eliza SoC interconnect: qcom: Add Eliza interconnect provider driver dt-bindings: interconnect: OSM L3: Add Eliza EPSS L3 compatible Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in ↵Odelu Kukatla1-0/+142
Eliza SoC Document the RPMh Network-On-Chip Interconnect of the Eliza platform. Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://msgid.link/20260224-eliza-interconnect-v4-1-ad75855d5018@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06interconnect: qcom: Add Eliza interconnect provider driverOdelu Kukatla0-0/+0
Add driver for the Qualcomm interconnect buses found in Eliza based platforms. The topology consists of several NoCs that are controlled by a remote processor that collects the aggregated bandwidth for each master-slave pairs. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://msgid.link/20260224-eliza-interconnect-v4-2-ad75855d5018@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06dt-bindings: interconnect: OSM L3: Add Eliza EPSS L3 compatibleAbel Vesa1-0/+1
Eliza, similarly to SM8650, uses EPSS hardware for L3 scaling. Document it. Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://msgid.link/20260302-eliza-bindings-interconnect-epss-l3-v2-1-05b1848b98cc@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06dt-bindings: interconnect: qcom,glymur-rpmh: De-acronymize SoC nameKrzysztof Kozlowski1-1/+1
Glymur is a codename of Qualcomm SoC, not an acronym. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://msgid.link/20260217130035.281752-3-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06dt-bindings: interconnect: OSM L3: Document sm8550 OSM L3 compatibleAaron Kling1-0/+1
Document the OSM L3 found in the Qualcomm SM8550 platform. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://msgid.link/20260219-sm8550-ddr-bw-scaling-v3-1-75c19152e921@gmail.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06dt-bindings: interconnect: qcom,qcs8300-rpmh: add clocks property to enable QoSOdelu Kukatla1-0/+63
Some QCS8300 interconnect nodes have QoS registers located inside a block whose interface is clock-gated. For those nodes, driver must enable the corresponding clock(s) before accessing the registers. Add the 'clocks' property so the driver can obtain and enable the required clock(s). Only interconnects that have clock‑gated QoS register interface use this property; it is not applicable to all interconnect nodes. Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://msgid.link/20260127090116.1438780-2-odelu.kukatla@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in ↵Raviteja Laggyshetty1-25/+111
Mahua SoC Document the RPMh Network-on-Chip (NoC) interconnect for the Qualcomm Mahua platform. Mahua is a derivative of the Glymur SoC. Many interconnect nodes are identical and continue to use Glymur fallback compatibles. Mahua introduces SoC-specific configurations and topologies for several NoC blocks, including CNOC, HSCNOC, PCIe West ANoC/Slave NoCs. This updates the existing Glymur yaml schema to include Mahua-specific compatible strings, using two-cell "fallback" compatibles wherever the hardware is identical with Glymur. Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://msgid.link/20260209-mahua_icc-v3-1-c65f3dfd72c8@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06dt-bindings: arm: stm32: Modify STM32MP15x Phytec board items typesChristophe Parant1-3/+5
As Phytec manages different SoM configurations with different STM32MP15 SoC versions, modify the phyBOARD and SoM compatible items to "enum" instead of "const". The description concerns PHYTEC SoM equipped with STM32MP157 ("st,stm32mp157" is "const"). Also add comments in front of the enum items to be able to identify the compatible string with the phyBOARD/phyCORE names. Signed-off-by: Christophe Parant <c.parant@phytec.fr> Link: https://lore.kernel.org/r/20251210101611.27008-4-c.parant@phytec.fr Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2026-03-06dt-bindings: arm: mediatek: audsys: fix formatting issuesLouis-Alexis Eyraud1-32/+31
Fix indentation and drop duplicate newline to resolve the following 'make dt_binding_check' warnings: ``` ./Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml:52:2: [warning] wrong indentation: expected 2 but found 1 (indentation) ./Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml:84:1: [warning] too many blank lines (2 > 1) (empty-lines) ``` Fixes: a8e3d66ff5c0 ("dt-bindings: arm: mediatek: audsys: Support mt8192-audsys variant") Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2026-03-06dt-bindings: omap: Add Samsung Galaxy Tab 2 7.0 and 10.1Mithil Bavishi1-0/+2
Add samsung-espresso7 codename for the 7 inch variant Add samsung-espresso10 codename for the 10 inch variant Signed-off-by: Mithil Bavishi <bavishimithil@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Andreas Kemnade <andreas@kemnade.info> Link: https://patch.msgid.link/20260303203017.511-7-bavishimithil@gmail.com Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2026-03-06dt-bindings: display: panel-lvds: Add compatibles for Samsung LTN070NL01 and ↵Mithil Bavishi1-0/+4
LTN101AL03 panels The LTN070NL01 is a 7.0 inch 1024x600, 24 bit, VESA Compatible, TFT display panel The LTN101AL03 is a 10.1 inch 800x1280, 24 bit, VESA Compatible, TFT display panel Signed-off-by: Mithil Bavishi <bavishimithil@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20260303203017.511-5-bavishimithil@gmail.com Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2026-03-06dt-bindings: display: bridge: lvds-codec: add doestek,dtc34lm85amMithil Bavishi1-0/+1
Add compatible strings for the Doestek DTC34LM85AM Flat Panel Display Transmitter Signed-off-by: Mithil Bavishi <bavishimithil@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20260303203017.511-4-bavishimithil@gmail.com Signed-off-by: Kevin Hilman <khilman@baylibre.com>
generated by cgit v1.2.3 (git 2.39.0) at 2026-05-15 04:34:43 +0300