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2026-01-21dt-bindings: pinctrl: qcom,glymur-tlmm: Document Mahua TLMM blockGopikrishna Garmidi1-2/+4
Document the pinctrl compatible for the Mahua SoC, a 12-core variant of Glymur. The PDC wake IRQ map differs since PDC handles the interrupt for GPIO 155 instead of GPIO 143 as seen on Glymur. Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-01-21media: dt-bindings: add rockchip mipi csi-2 receiverMichael Riesch1-0/+141
Add documentation for the Rockchip MIPI CSI-2 Receiver. Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Michael Riesch <michael.riesch@collabora.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
2026-01-21dt-bindings: display: bridge: simple: document the Algoltek AG6311 ↵Val Packett1-0/+1
DP-to-HDMI bridge The Algoltek AG6311 is a transparent DisplayPort to HDMI bridge. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Val Packett <val@packett.cool> Link: https://patch.msgid.link/20260120234029.419825-7-val@packett.cool Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-01-21dt-bindings: vendor-prefixes: Add AlgolTekVal Packett1-0/+2
AlgolTek is a Taiwanese chip manufacturer specialized in high-speed signal and power transmission and conversion. Signed-off-by: Val Packett <val@packett.cool> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260120234029.419825-4-val@packett.cool Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-01-21dt-bindings: interconnect: qcom-bwmon: Document Glymur BWMONsPragnesh Papaniya1-0/+1
Document Glymur BWMONs, which has multiple (one per cluster) BWMONv4 instances for the CPU->DDR path. Signed-off-by: Pragnesh Papaniya <pragnesh.papaniya@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260120-glymur_bwmon_binding-v1-1-57848445eccf@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-01-21dt-bindings: eeprom: at24: Add compatible for Puya P24C128FLuca Weiss1-0/+1
Add the compatible for an 128Kb EEPROM from Puya. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260116-milos-cci-v1-1-28e01128da9c@fairphone.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-01-21dt-bindings: phy: renesas,usb2-phy: Document RZ/G3E SoCTommaso Merciai1-1/+3
Document USB2.0 phy bindings for RZ/G3E ("R9A09G047") SoC. The RZ/G3E USB2.0 phy is functionally identical to the one found on the RZ/V2H(P), so no driver changes are needed. The existing "renesas,usb2-phy-r9a09g057" will be used as a fallback compatible for this IP. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://patch.msgid.link/4f2454708428b48e03faabe79e383999fb1ab458.1766405010.git.tommaso.merciai.xr@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-21dt-bindings: phy: renesas,usb2-phy: Document mux-states propertyTommaso Merciai1-0/+5
Some Renesas SoCs, such as RZ/G3E, provide a USB2.0 OTG PHY with configurable VBUS control through a multiplexed hardware register. This register allows selecting the VBUS source via a mux control line exposed by the PHY. To represent this hardware configuration, support the standard `mux-states` property in the Renesas USB2 PHY binding. This allows the DeviceTree to model the VBUS source selection as a mux, consistent with generic binding conventions. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://patch.msgid.link/36d448dd10bbb2bbfa5b1b6b6e3fee86c34d01aa.1766405010.git.tommaso.merciai.xr@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-21dt-bindings: phy: renesas,usb2-phy: Document USB VBUS regulatorTommaso Merciai1-0/+6
Document the 'vbus-regulator' child node in the Renesas USB2 PHY binding to describe the internal USB VBUS regulator. Require this regulator node on OTG channels to accurately represent hardware dependencies in the device tree. Documenting this regulator allows device trees to model the VBUS power requirements of these SoCs properly. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://patch.msgid.link/aaa8044283eb736817afd43d4fba3aa93b50b1dd.1766405010.git.tommaso.merciai.xr@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-21media: dt-bindings: media: renesas,fcp: Allow three clocks for RZ/V2N SoCLad Prabhakar1-0/+1
Update the FCP DT schema to permit three clock inputs for the RZ/V2N SoC. The FCP block on this SoC requires three separate clocks, unlike other variants which use only one. Fixes: f42eddf44fbf ("media: dt-bindings: media: renesas,fcp: Document RZ/V2N SoC") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251103194554.54313-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
2026-01-21dt-bindings: net: micrel: Convert micrel-ksz90x1.txt to DT schemaStefan Eichenberger2-228/+253
Convert the micrel-ksz90x1.txt to DT schema. Create a separate YAML file for this PHY series. The old naming of ksz90x1 would be misleading in this case, so rename it to gigabit, as it contains ksz9xx1 and lan8xxx gigabit PHYs. Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/20260116130948.79558-3-eichest@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-01-21dt-bindings: net: micrel: Convert to DT schemaStefan Eichenberger2-57/+131
Convert the devicetree bindings for the Micrel PHYs and switches to DT schema. Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260116130948.79558-2-eichest@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-01-21dt-bindings: net: sparx5: do not require phys when RGMII is usedRobert Marko1-1/+14
LAN969x has 2 dedicated RGMII ports, so regular SERDES lanes are not used for RGMII. So, lets not require phys to be defined when any of the rgmii phy-modes are set. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260115114021.111324-11-robert.marko@sartura.hr Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-01-21dt-bindings: display/msm: qcom, kaanapali-mdss: Add KaanapaliYuanjie Yang1-0/+297
Kaanapali introduces DPU 13.0.0 and DSI 2.10. Compared to SM8750, Kaanapali has significant register changes, making it incompatible with SM8750. So add MDSS/MDP display subsystem for Qualcomm Kaanapali. Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/698700/ Link: https://lore.kernel.org/r/20260115092749.533-5-yuanjie.yang@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-01-21dt-bindings: display/msm: dsi-controller-main: Add KaanapaliYuanjie Yang1-0/+2
The DSI registers on the Kaanapali platform differ from those on SM8750. So add DSI for Kaanapali to compatible these changes. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/698698/ Link: https://lore.kernel.org/r/20260115092749.533-4-yuanjie.yang@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-01-21dt-bindings: display/msm: dsi-phy-7nm: Add Kaanapali DSI PHYYuanjie Yang1-0/+1
The DSI PHY registers on the Kaanapali platform differ from those on SM8750. So add DSI PHY for Kaanapali to compatible these changes. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/698696/ Link: https://lore.kernel.org/r/20260115092749.533-3-yuanjie.yang@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-01-21dt-bindings: display/msm: qcom, kaanapali-dpu: Add KaanapaliYuanjie Yang1-0/+1
Add DPU version 13.0 for Qualcomm Kaanapali Soc. The Kaanapali DPU and SM8750 have significant differences, including additions and removals of registers, as well as changes in register addresses. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/698694/ Link: https://lore.kernel.org/r/20260115092749.533-2-yuanjie.yang@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-01-21Merge tag 'v6.19-rc1' into msm-nextDmitry Baryshkov690-5977/+16303
Merge Linux 6.19-rc1 in order to catch up with other changes (e.g. UBWC config database defining UBWC_6). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-01-20dt-bindings: input: google,goldfish-events-keypad: Convert to DT schemaKuan-Wei Chiu2-17/+41
Convert the Android Goldfish Events Keypad binding to DT schema format. Move the file to the input directory to match the subsystem. Update the example node name to 'keypad' to comply with generic node naming standards. Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260113092602.3197681-4-visitorckw@gmail.com Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-01-20dt-bindings: thermal: mediatek: Add LVTS thermal controller definition for ↵Frank Wunderlich1-0/+1
MT7987 Add thermal controller definition for MT7987. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251223175710.25850-2-linux@fw-web.de Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2026-01-20dt-bindings: nvmem: mediatek: efuse: Add support for MT8196Laura Nao1-0/+1
The MT8196 eFuse layout is compatible with MT8186 and shares the same decoding scheme for the gpu-speedbin cell. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Laura Nao <laura.nao@collabora.com> Link: https://patch.msgid.link/20251125-mt8196-lvts-v4-v5-8-6db7eb903fb7@collabora.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2026-01-20dt-bindings: thermal: mediatek: Add LVTS thermal controller support for MT8196Laura Nao1-0/+2
Add LVTS thermal controller binding for MediaTek MT8196. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Laura Nao <laura.nao@collabora.com> Link: https://patch.msgid.link/20251125-mt8196-lvts-v4-v5-1-6db7eb903fb7@collabora.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2026-01-20dt-bindings: input: touchscreen: edt-ft5x06: Add FocalTech FT3518Yedaya Katsman1-0/+1
Document FocalTech FT3518 support by adding the compatible. Co-developed-by: Kamil Gołda <kamil.golda@protonmail.com> Signed-off-by: Kamil Gołda <kamil.golda@protonmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Yedaya Katsman <yedaya.ka@gmail.com> Link: https://patch.msgid.link/20260118-touchscreen-patches-v3-1-1c6a729c5eb4@gmail.com Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-01-20ASoC: renesas: rz-ssi: CleanupsMark Brown8-22/+35
Merge series from Claudiu <claudiu.beznea@tuxon.dev>: This series adds cleanups for the Renesas RZ SSI driver.
2026-01-20spi: xilinx: make IRQs optionalMark Brown9-23/+35
Merge series from Abdurrahman Hussain <abdurrahman@nexthop.ai>: Additionally, make interrupts optional to allow the driver to fall back to its existing polling mode on systems where interrupts are either missing or broken.
2026-01-20dt-bindings: pwm: nxp,lpc32xx-pwm: Specify clocks property as mandatoryVladimir Zapolskiy1-0/+4
Both described in the binding PWM controllers depend on supply clocks, thus it's necessary to specify 'clocks' property in the correspondent device tree nodes. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251228224907.1729627-2-vz@mleia.com Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
2026-01-20dt-bindings: mfd: Add rk801 bindingJoseph Chen1-0/+197
Add DT binding document for Rockchip's RK801 PMIC Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260112124351.17707-2-chenjh@rock-chips.com Signed-off-by: Lee Jones <lee@kernel.org>
2026-01-20dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindingsGuodong Xu1-0/+5
Add DT binding documentation for the SpacemiT K3 SoC and the board Pico-ITX which is a 2.5-inch single-board computer. Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Signed-off-by: Guodong Xu <guodong@riscstar.com> Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-5-6990ac9f4308@riscstar.com Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-01-20dt-bindings: interrupt-controller: add SpacemiT K3 IMSICGuodong Xu1-0/+1
Add compatible string for SpacemiT K3 IMSIC. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Guodong Xu <guodong@riscstar.com> Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-4-6990ac9f4308@riscstar.com Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-01-20dt-bindings: interrupt-controller: add SpacemiT K3 APLICGuodong Xu1-0/+1
Add compatible string for SpacemiT K3 APLIC. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Guodong Xu <guodong@riscstar.com> Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-3-6990ac9f4308@riscstar.com Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-01-20dt-bindings: timer: add SpacemiT K3 CLINTGuodong Xu1-0/+1
Add compatible string for SpacemiT K3 CLINT. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Guodong Xu <guodong@riscstar.com> Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-2-6990ac9f4308@riscstar.com Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-01-20dt-bindings: riscv: add SpacemiT X100 CPU compatibleGuodong Xu1-0/+1
Add compatible string for the SpacemiT X100 core. [1] The X100 is a 64-bit RVA23-compliant RISC-V core from SpacemiT. X100 supports the RISC-V vector and hypervisor extensions and all mandatory extersions as required by the RVA23U64 and RVA23S64 profiles, per the definition in 'RVA23 Profile, Version 1.0'. [2] From a microarchieture viewpoint, the X100 features a 4-issue out-of-order pipeline. X100 is used in SpacemiT K3 SoC. Acked-by: Paul Walmsley <pjw@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://www.spacemit.com/en/spacemit-x100-core/ [1] Link: https://docs.riscv.org/reference/profiles/rva23/_attachments/rva23-profile.pdf [2] Reviewed-by: Yixun Lan <dlan@gentoo.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Guodong Xu <guodong@riscstar.com> Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-1-6990ac9f4308@riscstar.com Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-01-20spi: dt-bindings: nxp,imx94-xspi: add nxp,imx952-xspiHaibo Chen1-0/+4
Document i.MX952 XSPI compatible, which is derived from i.MX94 XSPI. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Link: https://patch.msgid.link/20260114-xspi-imx952-v1-1-acc60a5a2a9d@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-01-20dt-bindings: display: panel: Add compatible for Anbernic RG-DSChris Morgan1-0/+2
The Anbernic RG-DS uses two (mostly) identical panels as a top and bottom panel which appear to use the same controller as the Jadard JD9365DA-H3. The panels differ with a parameter defined differently in the init sequence. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patch.msgid.link/20260113195721.151205-3-macroalpha82@gmail.com
2026-01-20dt-bindings: media: st: dcmipp: add 'power-domains' propertyAlain Volmat1-0/+3
STM32 DCMIPP may be in a power domain which is the case for the STM32MP2x based boards. Allow a single 'power-domains' entry for STM32 DCMIPP. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251219-stm32-mp2x-dcmipp-csi-power-domain-v1-4-a6edb2aa8154@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2026-01-20dt-bindings: media: st: csi: add 'power-domains' propertyAlain Volmat1-0/+3
STM32 CSI may be in a power domain which is the case for the STM32MP2x based boards. Allow a single 'power-domains' entry for STM32 CSI. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251219-stm32-mp2x-dcmipp-csi-power-domain-v1-1-a6edb2aa8154@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2026-01-20dt-bindings: i2c: st,stm32-i2c: add 'power-domains' propertyAlain Volmat1-0/+3
STM32 I2C may be in a power domain which is the case for the STM32MP2x based boards. Allow a single 'power-domains' entry for STM32 I2C. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251215-stm32-i2c-mp2x-dt-updates-v1-1-2738a05a7af8@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2026-01-20dt-bindings: pinctrl: spacemit: add syscon propertyTroy Mitchell1-0/+5
In order to access the protected IO power domain registers, a valid unlock sequence must be performed by writing the required keys to the AIB Secure Access Register (ASAR). The ASAR register resides within the APBC register address space. A corresponding syscon property is added to allow the pinctrl driver to access this register. Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-01-20spi: dt-bindings: xilinx: make interrupts optionalAbdurrahman Hussain1-1/+0
Both the hardware and driver already support polling mode. By removing the mandatory IRQ requirement during probe, the driver can now fall back to polling when an interrupt is unavailable, ensuring compatibility with a wider range of systems. Signed-off-by: Abdurrahman Hussain <abdurrahman@nexthop.ai> Link: https://patch.msgid.link/20260119-spi-xilinx-v3-1-4566c33bac0d@nexthop.ai Signed-off-by: Mark Brown <broonie@kernel.org>
2026-01-19dt-bindings: watchdog: Document X1E80100 compatibleAbel Vesa1-0/+1
Document the compatible for the X1E80100 platform to the Qualcomm watchdog binding. The HW implementation is compatible with the KPSS WDT. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251224-arm64-dts-qcom-x1e80100-el2-add-apss-wdt-v3-1-1801c55d2883@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-19dt-bindings: net: dsa: lantiq,gswip: add MaxLinear R(G)MII slew rateAlexander Sverdlin1-0/+22
Add new maxlinear,slew-rate-txc and maxlinear,slew-rate-txd uint32 properties. The properties are only applicable for ports in R(G)MII mode and allow for slew rate reduction in comparison to "normal" default configuration with the purpose to reduce radiated emissions. Signed-off-by: Alexander Sverdlin <alexander.sverdlin@siemens.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260114104509.618984-2-alexander.sverdlin@siemens.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-01-19dt-bindings: display: mediatek: Fix typo 'hardwares' to 'hardware'Nauman Sabir1-1/+1
Fix incorrect plural form of the uncountable noun 'hardware' in the MediaTek DP binding description. Signed-off-by: Nauman Sabir <officialnaumansabir@gmail.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patchwork.kernel.org/project/dri-devel/patch/20260112160759.19027-1-officialnaumansabir@gmail.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2026-01-19dt-bindings: regulator: mark regulator-suspend-microvolt as deprecatedPeng Fan1-0/+1
The Documentation/devicetree/bindings/regulator/regulator.yaml already states in its description that regulator-suspend-microvolt is deprecated, but the schema did not formally mark it as such. Add the `deprecated: true` annotation to regulator-suspend-microvolt so that this is enforced at the schema level. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://patch.msgid.link/20260119-regulator-binding-v1-1-e55d33b4c3e3@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-01-19ASoC: dt-bindings: fsl,sai: Add support for i.MX952 platformShengjiu Wang1-0/+1
Add a new compatible string 'fsl,imx952-sai' for i.MX952 platform, which is fallback compatible with 'fsl,imx95-sai'. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260115061418.4131432-1-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-01-19dt-bindings: arm: mediatek: audsys: Support mt8192-audsys variantAngeloGioacchino Del Regno1-13/+33
Add support for the mediatek,mt8192-audsys compatible, which uses a different audio controller (mt8192-afe-pcm) compared to mt8183 and mt2701. This resolves a dtbs_check warning on all MT8192 devicetrees. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2026-01-19dt-bindings: arm: qcom: Add Coresight Interconnect TNOCYuanfang Zhang1-0/+90
Add device tree binding for Qualcomm Coresight Interconnect Trace Network On Chip (ITNOC). This TNOC acts as a CoreSight graph link that forwards trace data from a subsystem to the Aggregator TNOC, without aggregation or ATID functionality. Signed-off-by: Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20251203-itnoc-v5-1-5b97c63f2268@oss.qualcomm.com
2026-01-19dt-bindings: mtd: st,spi-fsm: convert to DT schemaAkhila YS2-25/+68
Convert STMicroelectronics SPI FSM Serial NOR Flash Controller binding to DT Schema. Signed-off-by: Akhila YS <akhilayalmati@gmail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2026-01-19dt-bindings: mtd: microchip,mchp23k256: convert to DT schemaAkhila YS2-18/+49
Convert Microchip 23K256 SPI SRAM MTD binding to YAML format. Changes during conversion: - Remove "address-cells" and "size-cells" from properties and required sections as there is no child node for sram. Signed-off-by: Akhila YS <akhilayalmati@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2026-01-19dt-bindings: mtd: nvidia,tegra20-nand: convert to DT schemaCharan Pedumuru2-64/+102
Convert NVIDIA Tegra NAND Flash Controller binding to YAML format. Changes during Conversion: - Define new properties `power-domains` and `operating-points-v2` because the existing in tree DTS uses them. - Modify MAINTAINERS references to point the created YAML file. Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2026-01-19Merge 6.19-rc6 usb-nextGreg Kroah-Hartman11-25/+51
We need the USB fixes in here as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
generated by cgit v1.2.3 (git 2.39.0) at 2026-05-16 18:38:39 +0300