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Add interrupts and interrupt-names protperties for PRU and RTU cores.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230814095141.3526684-1-danishanwar@ti.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Documentation/process/license-rules.rst and checkpatch expect the SPDX
identifier syntax for multiple licenses to use capital "OR". Correct it
to keep consistent format and avoid copy-paste issues.
Correct also the format // -> .* in few Allwinner binding headers as
pointed out by checkpatch:
WARNING: Improper SPDX comment style for 'include/dt-bindings/reset/sun50i-h6-ccu.h', please use '/*' instead
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20230823084540.112602-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Rob Herring <robh@kernel.org>
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Update the PRU remoteproc bindings for the PRU cores on AM62x SoCs.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220602101920.12504-3-kishon@ti.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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Re-arrange "compatible" string in alphabetic order to decrease the
chance of conflicts.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220602101920.12504-2-kishon@ti.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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The K3 AM64x SoCs have an ICSSG IP that is similar to the IP revisions
used on K3 AM65x SR2.0 and J721E SoCs. The ICSSG IP on K3 AM64x SoCs
have the same set of two PRU cores, two RTU cores and two auxiliary PRU
cores called Transmit PRUs (Tx_PRUs). There are some minor differences
surrounding the PRU cores like different Broadside RAM (BSRAM) sizes
w.r.t AM65x SR1.0 SoCs.
Update the PRU remoteproc bindings for these PRU cores on AM64x SoCs.
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20210623173243.7862-2-s-anna@ti.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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The Programmable Real-Time Unit and Industrial Communication Subsystem
(PRU-ICSS or simply PRUSS) on various TI SoCs consists of dual 32-bit
RISC cores (Programmable Real-Time Units, or PRUs) for program execution.
The K3 AM65x amd J721E SoCs have the next generation of the PRU-ICSS IP,
commonly called ICSSG. The ICSSG IP on AM65x SoCs has two PRU cores,
two auxiliary custom PRU cores called Real Time Units (RTUs). The K3
AM65x SR2.0 and J721E SoCs have a revised version of the ICSSG IP, and
include two additional custom auxiliary PRU cores called Transmit PRUs
(Tx_PRUs).
This patch adds the bindings for these PRU cores. The binding covers the
OMAP architecture SoCs - AM33xx, AM437x and AM57xx; Keystone 2 architecture
based 66AK2G SoC; and the K3 architecture based SoCs - AM65x and J721E. The
Davinci based OMAPL138 SoCs will be covered in a future patch.
Reviewed-by: Rob Herring <robh@kernel.org>
Co-developed-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
Link: https://lore.kernel.org/r/20201208141002.17777-2-grzegorz.jaszczyk@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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