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2024-07-02dt-bindings: phy: airoha: Add dtime and Rx AEQ IO registersLorenzo Bianconi1-2/+13
Introduce Tx-Rx detection time and Rx AEQ mappings in Airoha EN7581 PCIe-PHY binding. This change is not introducing any backward compatibility issue since the EN7581 dts is not upstream yet. Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/a018329ff9678f3360bc6381294f95c62d34f3e3.1719682943.git.lorenzo@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-02dt-bindings: phy: rockchip-emmc-phy: Convert to dtschemaShresth Prasad2-43/+64
Convert txt bindings of Rockchip EMMC PHY to dtschema to allow for validation. Signed-off-by: Shresth Prasad <shresthprasad7@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240620212806.3011-2-shresthprasad7@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-02dt-bindings: phy: qcom,qmp-usb: fix spelling errorYijie Yang1-1/+1
Correct the spelling error, changing 'com' to 'qcom'. Cc: stable@vger.kernel.org Fixes: f75a4b3a6efc ("dt-bindings: phy: qcom,qmp-usb: Add QDU1000 USB3 PHY") Signed-off-by: Yijie Yang <quic_yijiyang@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240624021916.2033062-1-quic_yijiyang@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-02dt-bindings: phy: samsung,usb3-drd-phy: add gs101 compatibleAndré Draszik1-2/+75
Add a dedicated google,gs101-usb31drd-phy compatible for Google Tensor gs101 SoC. It needs additional clocks enabled for register access, and additional memory regions (PCS & PMA) are required for successful configuration. It also requires various power supplies (regulators) for the internal circuitry to work. The required voltages are: * pll-supply: 0.85V * dvdd-usb20-supply: 0.85V (+10%, -7%) * vddh-usb20-supply: 1.8V (+10%, -7%) * vdd33-usb20-supply: 3.3V (+10%, -7%) * vdda-usbdp-supply: 0.85V * vddh-usbdp-supply: 1.8V Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240617-usb-phy-gs101-v3-1-b66de9ae7424@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-20dt-bindings: phy: airoha: Add PCIe PHY controllerLorenzo Bianconi1-0/+58
Introduce device-tree binding documentation for Airoha EN7581 PCIe PHY controller. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/656133f865433c1d02f00a3abbb1aa9312d2a24e.1718485860.git.lorenzo@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-15dt-bindings: phy: Add i.MX8Q HSIO SerDes PHY bindingRichard Zhu1-0/+164
Add i.MX8QM and i.MX8QXP HSIO SerDes PHY binding. Introduce one HSIO configuration 'fsl,hsio-cfg', which need be set at initialization according to board design. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/1716962565-2084-2-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-15dt-bindings: phy: Add starfive,jh7110-dphy-txShengyang Chen1-0/+68
StarFive SoCs like the jh7110 use a MIPI D-PHY TX controller based on a M31 IP. Add a binding for it. Signed-off-by: Shengyang Chen <shengyang.chen@starfivetech.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240418035020.47876-2-shengyang.chen@starfivetech.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-15dt-bindings: phy: qcom,usb-hs-phy: Add compatibleHerman van Hazendonk1-0/+2
Adds qcom,usb-hs-phy-msm8660 compatible Used by HP Touchpad (tenderloin) for example. Signed-off-by: Herman van Hazendonk <github.com@herrie.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240417065454.3599824-1-github.com@herrie.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-15dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: drop second output clock nameDmitry Baryshkov1-6/+1
There is no need to specify exact name for the second (AUX) output clock. It has never been used for the lookups based on the system clock name. Partially revert commit 72bea132f368 ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on SM8[456]50 SoCs"), returning compatibility with the existing device tree: reduce clock-output-names to always contain a single entry. Fixes: 72bea132f368 ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on SM8[456]50 SoCs") Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240614-fix-pcie-phy-compat-v3-2-730d1811acf4@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-12dt-bindings: phy: g12a-usb2-phy: add optional power-domainsNeil Armstrong1-0/+3
On newer SoCs, the USB2 PHY can require a power-domain to operate, add it as optional. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240605-topic-amlogic-upstream-bindings-fixes-power-domains-phy-v1-1-c819b0ecd8c8@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-12dt-bindings: phy: armada-cp110-utmi: add optional swap-dx-lanes propertyJosua Mayer1-0/+6
Armada CP110 UTMI supports swapping D+ and D- signals. usb251xb.yaml already describes a suitable device-tree property for the same purpose but as child usb controller node. Add optional swap-dx-lanes device-tree property to armada cp110 utmi phy with same semantics as usb251xb: The property lists all ports that swap D+ and D-, unlisted ports are considered correct. Signed-off-by: Josua Mayer <josua@solid-run.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240602-cn9130-som-v6-4-89393e86d4c7@solid-run.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-03dt-bindings: phy: qcom,ipq8074-qmp-pcie: Document the IPQ9574 QMP PCIe PHYsdevi priya1-0/+2
Document the QMP PCIe PHYs on IPQ9574 platform. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: devi priya <quic_devipriy@quicinc.com> Link: https://lore.kernel.org/r/20240516032436.2681828-2-quic_devipriy@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-03dt-bindings: phy: qcom,sc8280xp-qmp-usb3-uni: Add sc8180x USB3 compatibleBjorn Andersson1-0/+3
The SC8180X has two USB3 UNIPHY QMP blocks, add a compatible for these. Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20240525-sc8180x-usb-mp-v1-1-60a904392438@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-05-21Merge tag 'phy-for-6.10' of ↵Linus Torvalds11-9/+351
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull generic phy updates from Vinod Koul: "New HW Support: - Support for Embedded DisplayPort and DisplayPort submodes and driver support on Qualcomm X1E80100 edp driver - Qualcomm QMP UFS PHY for SM8475, QMP USB phy for QDU1000/QRU1000 and eusb2-repeater for SMB2360 - Samsung HDMI PHY for i.MX8MP, gs101 UFS phy - Mediatek XFI T-PHY support for mt7988 - Rockchip usbdp combo phy driver Updates: - Qualcomm x4 lane EP support for sa8775p, v4 ad v6 support for X1E80100, SM8650 tables for UFS Gear 4 & 5 and correct voltage swing tables - Freescale imx8m-pci pcie link-up updates - Rockchip rx-common-refclk-mode support - More platform remove callback returning void conversions" * tag 'phy-for-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (43 commits) dt-bindings: phy: qcom,usb-snps-femto-v2: use correct fallback for sc8180x dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: fix msm899[68] power-domains dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: fix x1e80100-gen3x2 schema phy: qcpm-qmp-usb: Add support for QDU1000/QRU1000 dt-bindings: phy: qcom,qmp-usb: Add QDU1000 USB3 PHY dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for QDU1000 phy: qcom-qmp-pcie: add x4 lane EP support for sa8775p phy: samsung-ufs: ufs: exit on first reported error phy: samsung-ufs: ufs: remove superfluous mfd/syscon.h header phy: rockchip: fix CONFIG_TYPEC dependency phy: rockchip: usbdp: fix uninitialized variable phy: rockchip-snps-pcie3: add support for rockchip,rx-common-refclk-mode dt-bindings: phy: rockchip,pcie3-phy: add rockchip,rx-common-refclk-mode phy: rockchip: add usbdp combo phy driver dt-bindings: phy: add rockchip usbdp combo phy document phy: add driver for MediaTek XFI T-PHY dt-bindings: phy: mediatek,mt7988-xfi-tphy: add new bindings phy: freescale: fsl-samsung-hdmi: Convert to platform remove callback returning void phy: qcom: qmp-ufs: update SM8650 tables for Gear 4 & 5 MAINTAINERS: Add phy-gs101-ufs file to Tensor GS101. ...
2024-05-18Merge tag 'devicetree-for-6.10' of ↵Linus Torvalds1-4/+4
git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree updates from Rob Herring: "DT Bindings: - Convert samsung,exynos5-dp, atmel,lcdc, aspeed,ast2400-wdt bindings to schemas - Add bindings for Allwinner H616 NMI controller, Renesas r8a779g0 irqc, Renesas R-Car V4M TMU and CMT timers, Freescale S32G3 linflexuart, and Mediatek MT7988 XHCI - Add 'reg' constraints on DSI and SPI display panels - More dropping of unnecessary quotes in schemas - Use full paths rather than relative paths in schema $refs - Drop redundant storing of phandle for reserved memory DT Core: - Use scope based cleanups for kfree() and of_node_put() - Track interrupt-map and power-supplies for fw_devlink - Add buffer overflow check in of_modalias() - Add and use __of_prop_free() helper for freeing struct property" * tag 'devicetree-for-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (25 commits) of: property: Add fw_devlink support for interrupt-map property dt-bindings: display: panel: constrain 'reg' in DSI panels dt-bindings: display: panel: constrain 'reg' in SPI panels dt-bindings: display: samsung,ams495qa01: add missing SPI properties ref dt-bindings: Use full path to other schemas dt-bindings: PCI: qcom,pcie-sm8350: Drop redundant 'oneOf' sub-schema of: module: add buffer overflow check in of_modalias() dt-bindings: PCI: microchip: increase number of items in ranges property dt-bindings: Drop unnecessary quotes on keys dt-bindings: interrupt-controller: mediatek,mt6577-sysirq: Drop unnecessary quotes of: property: Use scope based cleanup on port_node of: reserved_mem: Remove the use of phandle from the reserved_mem APIs of: property: fw_devlink: Add support for "power-supplies" binding dt-bindings: watchdog: aspeed,ast2400-wdt: Convert to DT schema dt-bindings: irq: sun7i-nmi: Add binding for the H616 NMI controller dt-bindings: interrupt-controller: renesas,irqc: Add r8a779g0 support dt-bindings: timer: renesas,tmu: Add R-Car V4M support dt-bindings: timer: renesas,cmt: Add R-Car V4M support of: Use scope based of_node_put() cleanups of: Use scope based kfree() cleanups ...
2024-05-04dt-bindings: phy: qcom,usb-snps-femto-v2: use correct fallback for sc8180xDmitry Baryshkov1-3/+1
The qcom,sc8180x-usb-hs-phy device uses qcom,usb-snps-hs-7nm-phy fallback. Correct the schema for this platform. Fixes: 9160fb7c39a1 ("dt-bindings: phy: qcom,usb-snps-femto-v2: use fallback compatibles") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-3-f1fd15c33fb3@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-05-04dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: fix msm899[68] power-domainsDmitry Baryshkov1-1/+15
The Qualcomm MSM8996 and MSM8998 platforms don't have separate power domain for the UFS PHY. Replace required:power-domains with the conditional schema. Fixes: dc5cb63592bd ("dt-bindings: phy: migrate QMP UFS PHY bindings to qcom,sc8280xp-qmp-ufs-phy.yaml") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-2-f1fd15c33fb3@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-05-04dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: fix x1e80100-gen3x2 schemaDmitry Baryshkov1-1/+0
The qcom,x1e80100-qmp-gen3x2-pcie-phy device doesn't have second reset, drop it from the clause enforcing second reset to be used. Fixes: e94b29f2bd73 ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHYs") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-1-f1fd15c33fb3@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-05-04dt-bindings: phy: qcom,qmp-usb: Add QDU1000 USB3 PHYKomal Bajaj1-0/+2
Add dt-bindings for USB3 PHY found on Qualcomm QDU/QRU1000 SoC. Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240502082017.13777-3-quic_kbajaj@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-05-04dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for QDU1000Komal Bajaj1-0/+1
Document the compatible string for USB phy found in Qualcomm QDU/QRU1000 SoC. Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240502082017.13777-2-quic_kbajaj@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-05-03dt-bindings: Drop unnecessary quotes on keysRob Herring (Arm)1-4/+4
The yamllint quoted-strings check wasn't checking keys for quotes, but support for checking keys was added in 1.34 release. Fix all the errors found when enabling the check. Clean-up the xilinx-versal-cpm formatting while we're here. Acked-by: Mark Brown <broonie@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20240426202239.2837516-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2024-04-13dt-bindings: phy: rockchip,pcie3-phy: add rockchip,rx-common-refclk-modeNiklas Cassel1-0/+10
>From the RK3588 Technical Reference Manual, Part1, section 6.19 PCIe3PHY_GRF Register Description: "rxX_cmn_refclk_mode" RX common reference clock mode for lane X. This mode should be enabled only when the far-end and near-end devices are running with a common reference clock. The hardware reset value for this field is 0x1 (enabled). Note that this register field is only available on RK3588, not on RK3568. The link training either fails or is highly unstable (link state will jump continuously between L0 and recovery) when this mode is enabled while using an endpoint running in Separate Reference Clock with No SSC (SRNS) mode or Separate Reference Clock with SSC (SRIS) mode. (Which is usually the case when using a real SoC as endpoint, e.g. the RK3588 PCIe controller can run in both Root Complex and Endpoint mode.) Add a rockchip specific property to enable/disable the rxX_cmn_refclk_mode per lane. (Since this PHY supports bifurcation.) Signed-off-by: Niklas Cassel <cassel@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20240412125818.17052-2-cassel@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-04-12dt-bindings: phy: add rockchip usbdp combo phy documentSebastian Reichel1-0/+148
Add device tree binding document for Rockchip USBDP Combo PHY with Samsung IP block. Co-developed-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20240408225109.128953-2-sebastian.reichel@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-04-12dt-bindings: phy: mediatek,mt7988-xfi-tphy: add new bindingsDaniel Golle1-0/+80
Add bindings for the MediaTek XFI Ethernet SerDes T-PHY found in the MediaTek MT7988 SoC which can operate at various interfaces modes: via USXGMII PCS: * USXGMII * 10GBase-R * 5GBase-R via LynxI SGMII PCS: * 2500Base-X * 1000Base-X * Cisco SGMII (MAC side) Signed-off-by: Daniel Golle <daniel@makrotopia.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Link: https://lore.kernel.org/r/da5498096f71a40ca1eac4124b7bb601c82396fb.1712625857.git.daniel@makrotopia.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-04-06dt-bindings: phy: samsung,ufs-phy: Add dedicated gs101-ufs-phy compatiblePeter Griffin1-0/+1
Update dt schema to include the gs101 ufs phy compatible. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20240404122559.898930-5-peter.griffin@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-04-06dt-bindings: phy: qmp-ufs: Fix PHY clocks for SC7180Danila Tikhonov1-0/+1
QMP UFS PHY used in SC7180 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC This change obviously breaks the ABI, but it is inevitable since the clock topology needs to be accurately described in the binding. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240401182240.55282-2-danila@jiaxyga.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-04-05dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on ↵Neil Armstrong1-3/+24
SM8[456]50 SoCs The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which is muxed & gated then returned to the PHY as an input. Document the clock IDs to select the PIPE clock or the AUX clock, also enforce a second clock-output-names and a #clock-cells value of 1 for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-1-3ec0a966d52f@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-04-05dt-bindings: treewide: add access-controllers descriptionGatien Chevallier1-0/+4
access-controllers is an optional property that allows a peripheral to refer to one or more domain access controller(s). Description of this property is added to all peripheral binding files of the peripheral under the STM32 firewall controller. It allows an accurate representation of the hardware, where various peripherals are connected to a firewall bus. The firewall can then check the peripheral accesses before allowing its device to probe. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-03-29dt-bindings: phy: Add QMP UFS PHY comptible for SM8475Danila Tikhonov1-0/+2
Document the QMP UFS PHY compatible for SM8475. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240327180642.20146-2-danila@jiaxyga.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-03-28dt-bindings: phy: qcom-edp: Add X1E80100 PHY compatiblesAbel Vesa1-0/+1
The Qualcomm X1E80100 platform has multiple PHYs that can work in both eDP or DP mode, so document their compatible. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240221-phy-qualcomm-edp-x1e80100-v4-1-4e5018877bee@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-03-28dt-bindings: phy: qcom,snps-eusb2-repeater: Add compatible for SMB2360Abel Vesa1-1/+3
Add a dt-bindings compatible string for the Qualcomm's SMB2360 PMIC. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240220-phy-qualcomm-eusb2-repeater-smb2360-v2-1-213338ca1d5f@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-03-28dt-bindings: phy: add binding for the i.MX8MP HDMI PHYLucas Stach1-0/+62
Add a DT binding for the HDMI PHY found on the i.MX8MP SoC. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Link: https://lore.kernel.org/r/20240227220444.77566-2-aford173@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-02-16dt-bindings: phy: Add Rockchip HDMI/eDP Combo PHY schemaCristian Ciocaltea1-0/+91
Add dt-binding schema for the HDMI/eDP Transmitter Combo PHY found on Rockchip RK3588 SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20240214-phy-hdptx-v4-1-e7974f46c1a7@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-02-07dt-bindings: phy: add mediatek MIPI CD-PHY module v0.5Florian Sylvestre1-0/+79
This adds the bindings, for the MIPI CD-PHY module v0.5 embedded in some Mediatek soc, such as the mt8365 Signed-off-by: Florian Sylvestre <fsylvestre@baylibre.com> Signed-off-by: Julien Stephan <jstephan@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240111101504.468169-2-jstephan@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-02-07dt-bindings: phy: cadence-torrent: Add a separate compatible for TI J7200Swapnil Jakhade1-0/+1
TI J7200 uses Torrent SD0805 version which is a special version derived from Torrent SD0801 with some differences in register configurations. Add a separate compatible for TI J7200 platforms. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20240104133013.2911035-5-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-02-07dt-bindings: phy: cadence-torrent: Add optional input reference clock for PLL1Swapnil Jakhade1-3/+7
Add a new optional input reference clock (pll1_refclk) for PLL1. Update bindings to support dual reference clock multilink configurations. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20240104133013.2911035-2-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-02-07dt-bindings: phy: qmp-ufs: Fix PHY clocksManivannan Sadhasivam1-27/+21
All QMP UFS PHYs except MSM8996 require 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC or TCSR (since SM8550) MSM8996 only requires 'ref' and 'qref' clocks. Hence, fix the binding to reflect the actual clock topology. This change obviously breaks the ABI, but it is inevitable since the clock topology needs to be accurately described in the binding. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-1-58a49d2f4605@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-01-24dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe ↵Abel Vesa1-0/+6
PHYs Document the QMP PCIe PHYs on the X1E80100 platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20231223-x1e80100-phy-pcie-v2-1-223c0556908a@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-01-23dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: support SDM660Dmitry Baryshkov1-0/+2
Declare the USB-C QMP PHY present on the Qualcomm SDM660 / SDM630 platforms. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240116-sdm660-usb3-support-v1-1-2fbd683aea77@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-01-23dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: add TCSR registersDmitry Baryshkov1-0/+11
The QMP USB PHYs on msm8998, qcm2290 and some other platforms don't have the PCS_MISC_CLAMP_ENABLE register. Instead they need to toggle the register in the TCSR space. Declare the registers accessible through the TCSR space. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240117-usbc-phy-vls-clamp-v2-2-a950c223f10f@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-01-23dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: support USB-C dataDmitry Baryshkov1-0/+39
Extend the Qualcomm USB-C QMP PHY schema with the USB-C related entry points: orientation-switch property and USB-C connection graph. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240113-pmi632-typec-v2-4-182d9aa0a5b3@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-01-23dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: split from sc8280xp PHY schemaDmitry Baryshkov2-22/+132
In preparation to defining the USB-C handling on MSM8998, QCM2290 and SM6115 split existing QMP USB3 PHY schema into pure USB3 and USB-C schema definitions. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240113-pmi632-typec-v2-3-182d9aa0a5b3@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-01-23dt-bindings: phy: Add QMP UFS PHY compatible for SC7180David Wronek1-0/+2
Document the QMP UFS PHY compatible for SC7180 Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: David Wronek <davidwronek@gmail.com> Link: https://lore.kernel.org/r/20240121-sm7125-upstream-v4-3-f7d1212c8ebb@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-12-21dt-bindings: phy: qcom,sc8280xp-qmp-usb3-uni: Add X1E80100 USB PHY bindingAbel Vesa1-0/+3
Add compatible string for Qualcomm QMP Super Speed (SS) UNI PHY found in X1E80100. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20231122-phy-qualcomm-usb3-uniphy-x1e80100-v3-1-273814c300f8@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-12-21dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Document X1E80100 compatibleAbel Vesa1-0/+2
Add the X1E80100 compatible to the list. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231201-x1e80100-phy-combo-v1-1-6938ec41f3ac@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-12-21dt-bindings: phy: qcom: snps-eusb2: Document the X1E80100 compatibleAbel Vesa1-0/+1
Add the X1E80100 compatible to the list of supported PHYs. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231122-phy-qualcomm-eusb2-x1e80100-v2-1-3ba9a8e5ade4@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-12-21dt-bindings: phy: mediatek: tphy: add a property for force-mode switchChunfeng Yun1-0/+9
Due to some old SoCs with shared t-phy between usb3 and pcie only support force-mode switch, and shared and non-shared t-phy may exist at the same time on a SoC, can't use compatible to distinguish between shared and non-shared t-phy, add a property to supported it. Currently, only support switch from default pcie mode to usb3 mode. But now prefer to use "mediatek,syscon-type" on new SoC as far as possible. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231211025624.28991-1-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-12-21dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: fix path to headerKrzysztof Kozlowski1-2/+2
Fix the path to bindings header in description. Fixes: e1c4c5436b4a ("dt-bindings: phy: qcom,qmp-usb3-dp: fix sc8280xp binding") Cc: stable@vger.kernel.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20231218130553.45893-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-11-27dt-bindings: phy: add compatible for Mediatek MT8195Michael Walle1-0/+1
Add the compatible string for MediaTek MT8195 SoC, using the same MIPI D-PHY block as the MT8183. Signed-off-by: Michael Walle <mwalle@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231123133749.2030661-3-mwalle@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-11-27dt-bindings: phy: amlogic,g12a-mipi-dphy-analog: drop unneeded reg property ↵Neil Armstrong1-12/+0
and example The amlogic,g12a-mipi-dphy-analog is a feature of the simple-mfd amlogic,meson-axg-hhi-sysctrl system control register zone which is an intermixed registers zone, thus it's very hard to define clear ranges for each SoC controlled features even if possible. The amlogic,g12a-mipi-dphy-analog was wrongly documented as an independent register range, which is not the reality, thus fix the bindings by dropping the reg property now it's referred from amlogic,meson-gx-hhi-sysctrl.yaml and documented as a subnode of amlogic,meson-axg-hhi-sysctrl. Also drop the unnecessary example, the top level bindings example should be enough. Fixes: 76ab79f9726c ("dt-bindings: phy: add Amlogic G12A Analog MIPI D-PHY bindings") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231124-amlogic-v6-4-upstream-dsi-ccf-vim3-v9-4-95256ed139e6@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-01-17 21:32:53 +0300