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2021-01-13spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spiRamuthevar Vadivel Murugan1-67/+0
Move the Documentation/devicetree/bindings/mtd/cadence-quadspi.txt to Documentation/devicetree/bindings/spi/ Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201124041840.31066-5-vadivel.muruganx.ramuthevar@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-06-27dt-bindings: cadence-quadspi: add options reset propertyDinh Nguyen1-0/+5
The QSPI module can have an optional reset signals that will hold the module in a reset state. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-02-13dt-bindings: cadence-quadspi: Add new compatible for AM654 SoCVignesh R1-0/+1
AM654 SoC has Cadence Octal SPI controller, which is similar to Cadence QSPI controller but supports Octal IO(x8 data lines) and Double Data Rate(DDR) mode. Add new compatible to support OSPI controller on TI's AM654 SoCs. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2017-10-17mtd: spi-nor: cadence-quadspi: Add new binding to enable loop-back circuitVignesh R1-0/+3
Cadence QSPI IP has a adapted loop-back circuit which can be enabled by setting BYPASS field to 0 in READCAPTURE register. It enables use of QSPI return clock to latch the data rather than the internal QSPI reference clock. For high speed operations, adapted loop-back circuit using QSPI return clock helps to increase data valid window. Add DT parameter cdns,rclk-en to help enable adapted loop-back circuit for boards which do have QSPI return clock provided. Update binding documentation for the same. Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
2017-10-17mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatibleVignesh R1-1/+3
Update binding documentation to add a new compatible for TI 66AK2G SoC, to handle TI SoC specific quirks in the driver. Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
2016-07-18mtd: spi-nor: Bindings for Cadence Quad SPI Flash Controller driverGraham Moore1-0/+56
Add binding document for the Cadence QSPI controller. Signed-off-by: Graham Moore <grmoore@opensource.altera.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alan Tull <atull@opensource.altera.com> Cc: Brian Norris <computersforpeace@gmail.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Graham Moore <grmoore@opensource.altera.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Yves Vandervennet <yvanderv@opensource.altera.com> Cc: devicetree@vger.kernel.org Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>