| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2013-12-29 | clk: sunxi: Allwinner A20 output clock support | Chen-Yu Tsai | 1 | -0/+1 |
| 2013-12-29 | clk: sunxi: mod0 support | Emilio López | 1 | -1/+4 |
| 2013-12-29 | clk: sunxi: add PLL5 and PLL6 support | Emilio López | 1 | -0/+2 |
| 2013-12-29 | clk: sunxi: add gating support to PLL1 | Emilio López | 1 | -1/+1 |
| 2013-10-11 | Documentation: dt: Remove clock gates IDs list for Allwinner SoCs | Maxime Ripard | 1 | -2/+2 |
| 2013-08-26 | clk: sunxi: Add Allwinner A20 gates | Maxime Ripard | 1 | -0/+3 |
| 2013-08-26 | clk: sunxi: Add A31 clocks support | Maxime Ripard | 1 | -0/+6 |
| 2013-08-26 | clk: sunxi: Add A10s gates | Maxime Ripard | 1 | -0/+3 |
| 2013-05-29 | clk: sun5i: Add compatibles for Allwinner A13 | Maxime Ripard | 1 | -104/+13 |
| 2013-04-05 | clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates | Emilio López | 1 | -1/+108 |
| 2013-03-27 | clk: sunxi: rename compatible strings | Emilio López | 1 | -11/+11 |
| 2013-03-27 | clk: arm: sunxi: Add a new clock driver for sunxi SOCs | Emilio López | 1 | -0/+44 |
 |
index : kernel/linux.git | |
| Linux kernel stable tree (mirror) | Andrey V.Kosteltsev |
| summaryrefslogtreecommitdiff |