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2022-03-29drm/i915: Use DRM_MODE_FMT+DRM_MODE_ARG()Ville Syrjälä7-37/+37
2022-03-29drm/i915: Pass intel_connector to intel_panel_{init,fini}()Ville Syrjälä9-15/+15
2022-03-29drm/i915: Split pipe+output CSC programming to noarm+arm pairVille Syrjälä1-13/+23
2022-03-29drm/i915: Split color_commit() into noarm+arm pairVille Syrjälä3-28/+56
2022-03-29drm/i915: Make ilk+ pfit regiser unlockedVille Syrjälä1-9/+9
2022-03-29drm/i915: Remove locks around skl+ scaler programmingVille Syrjälä1-10/+0
2022-03-29docs: gpu: i915.rst: Fix DRRS documentationJosé Roberto de Souza1-13/+1
2022-03-29drm/i915: Add a DP1.2 compatible way to read LTTPR capabilitiesImre Deak3-31/+60
2022-03-28drm/i915/display: Extend DP HDR support to hsw+Uma Shankar1-1/+20
2022-03-28drm/i915/intel_combo_phy: Print I/O voltage infoAnkit Nautiyal1-10/+25
2022-03-28drm/i915/display: Remove check for low voltage sku for max dp source rateAnkit Nautiyal1-29/+3
2022-03-22drm/i915: s/enable/active/ for DRRSVille Syrjälä4-20/+27
2022-03-21drm/i915: Add "maximum pipe read bandwidth" checksVille Syrjälä2-5/+32
2022-03-21drm/i915: Fix DBUF bandwidth vs. cdclk handlingVille Syrjälä4-89/+147
2022-03-21drm/i915: Properly write lock bw_state when it changesVille Syrjälä1-1/+23
2022-03-21drm/i915: Round up when calculating display bandwidth requirementsVille Syrjälä1-2/+2
2022-03-21drm/i915: Nuke intel_bw_calc_min_cdclk()Ville Syrjälä3-76/+5
2022-03-21drm/i915: Remove total[] and uv_total[] from ddb allocationVille Syrjälä1-60/+62
2022-03-21drm/i915: Pre-calculate plane relative data rateVille Syrjälä4-154/+108
2022-03-21drm/i915: Split plane data_rate into data_rate+data_rate_yVille Syrjälä5-38/+42
2022-03-21drm/i915: Tweak plane ddb allocation trackingVille Syrjälä6-91/+74
2022-03-21drm/i915/display/adlp: More voltage swing table updatesJosé Roberto de Souza1-4/+18
2022-03-21drm/i915/sdvo: prefer __packed over __attribute__((packed))Jani Nikula1-1/+1
2022-03-18drm/i915: Rename QGV request/response bitsVille Syrjälä2-10/+17
2022-03-18drm/i915: Unconfuses QGV vs. PSF point masksVille Syrjälä2-19/+19
2022-03-18drm/i915: Fix PSF GV point mask when SAGV is not possibleVille Syrjälä1-1/+2
2022-03-18drm/i915: Rename pre-icl SAGV enable/disable functionsVille Syrjälä1-18/+14
2022-03-18drm/i915: Reject excessive SAGV block timeVille Syrjälä1-0/+6
2022-03-18drm/i915: Probe whether SAGV works on pre-iclVille Syrjälä1-0/+14
2022-03-18drm/i915: Rework SAGV block time probingVille Syrjälä1-15/+21
2022-03-18drm/i915: Treat SAGV block time 0 as SAGV disabledVille Syrjälä1-4/+6
2022-03-17drm/i915: include uapi/drm/i915_drm.h directly where neededJani Nikula6-4/+8
2022-03-17drm/i915: move i915_gem_object_needs_bit17_swizzle() to i915_gem_tiling.[ch]Jani Nikula5-10/+13
2022-03-16drm/i915: Reject unsupported TMDS rates on ICL+Ville Syrjälä1-0/+9
2022-03-16drm/i915: Deal with bigjoiner vs. DRRSVille Syrjälä1-1/+15
2022-03-16drm/i915: Do DRRS disable/enable during pre/post_plane_update()Ville Syrjälä4-50/+10
2022-03-16drm/i915: Schedule DRRS work from intel_drrs_enable()Ville Syrjälä1-2/+8
2022-03-16drm/i915: Don't cancel/schedule drrs work if the pipe wasn't affectedVille Syrjälä1-9/+8
2022-03-16drm/i915: Determine DRRS frontbuffer_bits ahead of timeVille Syrjälä2-1/+11
2022-03-16drm/i915: Fix DRRS frontbuffer_bits handlingVille Syrjälä1-2/+4
2022-03-16drm/i915: Add missing tab to DRRS debugfsVille Syrjälä1-1/+1
2022-03-16drm/i915: Put the downclock_mode check back into can_enable_drrs()Ville Syrjälä1-3/+5
2022-03-16drm/i915: Use drm_mode_copy()Ville Syrjälä1-5/+10
2022-03-15drm/i915/display: Do not re-enable PSR after it was marked as not reliableJosé Roberto de Souza1-0/+4
2022-03-15drm/i915/display: Fix HPD short pulse handling for eDPJosé Roberto de Souza3-5/+5
2022-03-15drm/i915: Convert fixed_mode/downclock_mode into a listVille Syrjälä5-46/+50
2022-03-15drm/i915: Implement static DRRSVille Syrjälä2-3/+30
2022-03-15drm/i915: Enable eDP DRRS on ilk/snb port AVille Syrjälä2-7/+4
2022-03-15drm/i915: Move DRRS enable/disable higher upVille Syrjälä2-3/+4
2022-03-15drm/i915: Stash DRRS state under intel_crtcVille Syrjälä8-224/+141
generated by cgit v1.2.3 (git 2.39.0) at 2026-04-23 22:13:55 +0300