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2021-09-28arm64: dts: qcom: sc7280: Update reserved memory mapSibi Sankar1-0/+34
Add missing reserved regions as described in v1 of SC7280 memory map. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1631886935-14691-7-git-send-email-sibis@codeaurora.org
2021-09-28arm64: dts: qcom: msm8998-fxtec-pro1: Add tlmm keyboard keysAngeloGioacchino Del Regno1-0/+64
This device has a physical matrix keyboard, connected to a GPIO expander, for which there's still no support yet. Though, some of the keys are connected to the MSM8998 GPIOs and not as a matrix, so these can be added. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210909123823.368199-4-angelogioacchino.delregno@somainline.org
2021-09-28arm64: dts: qcom: msm8998-fxtec-pro1: Add Goodix GT9286 touchscreenAngeloGioacchino Del Regno1-0/+48
This smartphone has a Goodix GT8296 touch IC, reachable at address 0x14 on blsp2 i2c-1. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210909123823.368199-3-angelogioacchino.delregno@somainline.org
2021-09-28arm64: dts: qcom: msm8998-fxtec-pro1: Add physical keyboard ledsAngeloGioacchino Del Regno1-0/+22
Add configuration for the physical keyboard LEDs, including the caps lock indicator and keyboard backlight. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210909123823.368199-2-angelogioacchino.delregno@somainline.org
2021-09-28arm64: dts: qcom: Add support for MSM8998 F(x)tec Pro1 QX1000AngeloGioacchino Del Regno2-0/+186
Add device tree support for the F(x)tec Pro 1 (QX1000) smartphone; this is a minimal configuration to boot to serial console. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210909123823.368199-1-angelogioacchino.delregno@somainline.org
2021-09-28arm64: dts: qcom: msm8916: Fix Secondary MI2S bit clockStephan Gerhold1-1/+7
At the moment, playing audio on Secondary MI2S will just end up getting stuck, without actually playing any audio. This happens because the wrong bit clock is configured when playing audio on Secondary MI2S. The PRI_I2S_CLK (better name: SPKR_I2S_CLK) is used by the SPKR audio mux block that provides both Primary and Secondary MI2S. The SEC_I2S_CLK (better name: MIC_I2S_CLK) is used by the MIC audio mux block that provides Tertiary MI2S. Quaternary MI2S is also part of the MIC audio mux but has its own clock (AUX_I2S_CLK). This means that (quite confusingly) the SEC_I2S_CLK is not actually used for Secondary MI2S as the name would suggest. Secondary MI2S needs to have the same clock as Primary MI2S configured. Fix the clock list for the lpass node in the device tree and add a comment to clarify this confusing naming. With these changes, audio can be played correctly on Secondary MI2S. Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Fixes: 3761a3618f55 ("arm64: dts: qcom: add lpass node") Tested-by: Vincent Knecht <vincent.knecht@mailoo.org> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210816181810.2242-1-stephan@gerhold.net
2021-09-28arm64: dts: qcom: msm8916-longcheer-l8150: Add missing sensor interruptsStephan Gerhold1-4/+39
So far there were no interrupts set up for the BMC150 accelerometer + magnetometer combo because they were broken for some reason. It turns out Longcheer L8150 actually has a BMC156 which is very similar to BMC150, but only has an INT2 pin for the accelerometer part. This requires some minor changes in the bmc150-accel driver which is now supported by using the more correct bosch,bmc156_accel compatible. Unfortunately it looks like even INT2 is not functional on most boards because the interrupt line is not actually connected to the BMC156. However, there are two pads next to the chip that can be shorted to make it work if needed. While at it, add the missing interrupts for the magnetometer part and extra BMG160 gyroscope, those seem to work without any problems. Also correct the magnetometer compatible to bosch,bmc156_magn for clarity (no functional difference for the magnetometer part). Tested-by: Nikita Travkin <nikita@trvn.ru> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210816123544.14027-1-stephan@gerhold.net
2021-09-28arm64: dts: qcom: sc7180: Add IMEM and pil info regionsSai Prakash Ranjan1-0/+15
Add IMEM and pil info DT nodes for SC7180 SoC which will help in the post-mortem debug. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> [bjorn: Dropped dload-mode subnode, as no agreement was reached on this binding] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/39064a2db95ccc2cb5eef003569bef2de651c8ed.1628757036.git.saiprakash.ranjan@codeaurora.org
2021-09-28arm64: dts: qcom: pm6150l: Add missing includeKonrad Dybcio1-0/+1
Add missing include to make it compile. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-17-konrad.dybcio@somainline.org
2021-09-28arm64: dts: qcom: sm6350: Add device tree for Sony Xperia 10 IIIKonrad Dybcio2-0/+58
Add initial SM6350 SoC and Sony Xperia 10 III (PDX213, Lena platform) device trees. There is no sign of another Lena devices on the horizon, so a common DTSI is not created for now. 10 III features a Full HD OLED display and 5G support, among other nice things like USB3. The bootloader is VERY unpleasant, to get a bootable setup you have to run: mkbootimg --kernel arch/arm64/boot/Image.gz --ramdisk [some initrd] \ --dtb arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dtb \ --cmdline "[some cmdline]" --base 0 --kernel_offset 0x8000 \ --ramdisk_offset 0x1000000 --dtb_offset 0x1f00000 --os_version 11 \ --os_patch_level "2021-08" --tags_offset 0x100 --pagesize 4096 \ --header_version 2 -o mainline.img adb reboot bootloader // You have to either pull vbmeta{"","_system"} from // /dev/block/bootdevice/by-name/ or build one as a part of AOSP build process fastboot --disable-verity --disable-verification flash vbmeta vbmeta.img fastboot --disable-verity --disable-verification flash vbmeta_system \ vbmeta_system.img fastboot flash boot mainline.img fastboot erase dtbo // This will take approx 70s... fastboot reboot Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-16-konrad.dybcio@somainline.org
2021-09-28arm64: dts: qcom: sm6350: Add apps_smmu and assign iommus prop to USB1Konrad Dybcio1-0/+89
Add a node for the APPS SMMU to allow for managing memory access to peripherals such as the USB controller. While at it, add iommus property to the USB1 node to make sure its registers can be accessed, as they seem to be gated by default. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-15-konrad.dybcio@somainline.org
2021-09-28arm64: dts: qcom: sm6350: Add SDHCI1/2 nodesKonrad Dybcio1-0/+81
Add SDHCI1/2 nodes for eMMC and uSD card respectively. Do note that most SM6350 devices seem to come with UFS. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> [bjorn: Replaced SM6350_CX with its constant value] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-14-konrad.dybcio@somainline.org
2021-09-28arm64: dts: qcom: sm6350: Add RPMHPD and BCM voterKonrad Dybcio1-0/+54
Add RPMHPD node, its OPP table and BCM voter to prepare for performance level voting. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-13-konrad.dybcio@somainline.org
2021-09-28arm64: dts: qcom: sm6350: Add PRNG nodeKonrad Dybcio1-0/+7
Add a node for the PRNG to enable hw-accelerated pseudo-random number generation. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-12-konrad.dybcio@somainline.org
2021-09-28arm64: dts: qcom: sm6350: Add SPMI busKonrad Dybcio1-0/+18
Add a node for SPMI to allow for communication with on-board PMICs. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-11-konrad.dybcio@somainline.org
2021-09-28arm64: dts: qcom: sm6350: Add AOSS_QMPKonrad Dybcio1-0/+11
Add a node for AOSS_QMP in preparation for remote processor enablement. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-10-konrad.dybcio@somainline.org
2021-09-28arm64: dts: qcom: sm6350: Add TSENS nodesKonrad Dybcio1-0/+22
Add nodes required for TSENS block using the common qcom,tsens-v2 binding. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-9-konrad.dybcio@somainline.org
2021-09-28arm64: dts: qcom: sm6350: Add cpufreq-hw supportKonrad Dybcio1-0/+18
Add cpufreq-hw node and assign qcom,freq-domain properties to CPUs to enable CPU clock scaling. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-8-konrad.dybcio@somainline.org
2021-09-28arm64: dts: qcom: sm6350: Add USB1 nodesKonrad Dybcio1-0/+101
Add nodes required for USB1 to function. SM6350 (thankfully) resuses SDM845 and SC7180 IP, so no additional code porting is required. Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> [bjorn: Renamed dwc3 node "usb"] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-7-konrad.dybcio@somainline.org
2021-09-28arm64: dts: qcom: sm6350: Add TLMM block nodeKonrad Dybcio1-0/+19
Add TLMM pinctrl node to enable referencing the SoC pins in other nodes. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-6-konrad.dybcio@somainline.org
2021-09-28arm64: dts: qcom: sm6350: Add GCC nodeKonrad Dybcio1-0/+16
Add and configure GCC node to allow for referencing GCC-controlled clocks in other nodes. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-5-konrad.dybcio@somainline.org
2021-09-28arm64: dts: qcom: sm6350: Add RPMHCC nodeKonrad Dybcio1-0/+7
Add RPMHCC node to allow for referencing RPMH-controlled clocks in other nodes. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-4-konrad.dybcio@somainline.org
2021-09-28arm64: dts: qcom: sm6350: Add LLCC nodeKonrad Dybcio1-0/+6
Add a node for LLCC with SM6350-specific compatible. Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-3-konrad.dybcio@somainline.org
2021-09-28arm64: dts: qcom: Add SM6350 device treeKonrad Dybcio1-0/+485
Add a base DT for SM6350 SoC Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-2-konrad.dybcio@somainline.org
2021-09-28dt-bindings: arm: cpus: Add Kryo 560 CPUsKonrad Dybcio1-0/+1
Document Kryo 560 CPUs found in Qualcomm Snapdragon 690 (SM6350). Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-1-konrad.dybcio@somainline.org
2021-09-27arm64: dts: qcom: sm8350: Use QMP property to control load stateSibi Sankar1-14/+16
Use the Qualcomm Mailbox Protocol (QMP) property to control the load state resources on SM8350 SoCs and drop deprecated power-domains exposed by AOSS QMP node. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1631800770-371-11-git-send-email-sibis@codeaurora.org
2021-09-27arm64: dts: qcom: sm8250: Use QMP property to control load stateSibi Sankar1-11/+11
Use the Qualcomm Mailbox Protocol (QMP) property to control the load state resources on SM8250 SoCs and drop deprecated power-domains exposed by AOSS QMP node. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1631800770-371-10-git-send-email-sibis@codeaurora.org
2021-09-27arm64: dts: qcom: sm8150: Use QMP property to control load stateSibi Sankar1-14/+14
Use the Qualcomm Mailbox Protocol (QMP) property to control the load state resources on SM8150 SoCs and drop deprecated power-domains exposed by AOSS QMP node. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1631800770-371-9-git-send-email-sibis@codeaurora.org
2021-09-27arm64: dts: qcom: sdm845: Use QMP property to control load stateSibi Sankar1-4/+8
Use the Qualcomm Mailbox Protocol (QMP) property to control the load state resources on SDM845 SoCs and drop deprecated power-domains exposed by AOSS QMP node. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1631800770-371-8-git-send-email-sibis@codeaurora.org
2021-09-27arm64: dts: qcom: sc7280: Use QMP property to control load stateSibi Sankar1-2/+0
Use the Qualcomm Mailbox Protocol (QMP) property to control the load state resources on SC7280 SoCs and drop deprecated power-domains exposed by AOSS QMP node. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1631800770-371-7-git-send-email-sibis@codeaurora.org
2021-09-27arm64: dts: qcom: sc7180: Use QMP property to control load stateSibi Sankar1-5/+4
Use the Qualcomm Mailbox Protocol (QMP) property to control the load state resources on SC7180 SoCs and drop deprecated power-domains exposed by AOSS QMP node. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1631800770-371-6-git-send-email-sibis@codeaurora.org
2021-09-25arm64: dts: qcom: sc7180: Base homestar's power coefficients in realityDouglas Anderson1-1/+1
The commit 82ea7d411d43 ("arm64: dts: qcom: sc7180: Base dynamic CPU power coefficients in reality") and the commit be0416a3f917 ("arm64: dts: qcom: Add sc7180-trogdor-homestar") passed each other in the tubes that make up the Internet. Despite the fact the patches didn't cause a merge conflict, they need to account for each other. Do that. Fixes: 82ea7d411d43 ("arm64: dts: qcom: sc7180: Base dynamic CPU power coefficients in reality") Fixes: be0416a3f917 ("arm64: dts: qcom: Add sc7180-trogdor-homestar") Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923081352.1.I2a2ee0ac428a63927324d65022929565aa7d8361@changeid
2021-09-25arm64: dts: qcom: msm8998-xperia: Add audio clock and its pinAngeloGioacchino Del Regno1-0/+19
All smartphones of this platform are equipped with a WCD9335 audio codec, getting its MCLK from PM8998 gpio13: add this clock to DT. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210909123733.367248-7-angelogioacchino.delregno@somainline.org
2021-09-25arm64: dts: qcom: msm8998-xperia: Add camera regulatorsAngeloGioacchino Del Regno1-0/+56
All of the machines of the Sony Yoshino platform are equipped with two cameras, sharing the same regulators configuration. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210909123733.367248-6-angelogioacchino.delregno@somainline.org
2021-09-25arm64: dts: qcom: msm8998-xperia: Configure display boost regulatorsAngeloGioacchino Del Regno4-0/+58
Add configuration for the LAB and IBB regulators (in boost mode): this platform has smartphones with three different display sizes, hence different displays requiring different voltage. The common configuration parameters have been put in the common device-tree, while specific voltage specs and soft-start-us are variant specific, so they have been put into the machine specific dts file. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210909123733.367248-5-angelogioacchino.delregno@somainline.org
2021-09-25arm64: dts: qcom: msm8998-xperia: Add support for gpio vibratorAngeloGioacchino Del Regno1-0/+19
All smartphones in the Sony Yoshino platforms have got a simple vibrator hooked to a GPIO: add support for that and add its own pin configuration. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210909123733.367248-4-angelogioacchino.delregno@somainline.org
2021-09-25arm64: dts: qcom: msm8998-xperia: Add support for wcn3990 BluetoothAngeloGioacchino Del Regno1-0/+16
This platform uses the WCN3990 Bluetooth chip, reachable on UART-3. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210909123733.367248-3-angelogioacchino.delregno@somainline.org
2021-09-25arm64: dts: qcom: msm8998-xperia: Add RMI4 touchscreen supportAngeloGioacchino Del Regno1-0/+60
All of the devices in the Sony Yoshino platform are using a Synaptics RMI4-compatible touch IC with identical pins and supplies: enable the I2C-5 bus and add the rmi4-i2c node along with the required pin configurations. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210909123733.367248-2-angelogioacchino.delregno@somainline.org
2021-09-25arm64: dts: qcom: msm8998: Introduce support for Sony Yoshino platformAngeloGioacchino Del Regno5-0/+564
This commit introduces support for the Sony Yoshino platform, using the MSM8998 SoC, including: - Sony Xperia XZ1 (codename Poplar), - Sony Xperia XZ1 Compact (codename Lilac), - Sony Xperia XZ Premium (codename Maple). All of the three aforementioned smartphones are sharing a 99% equal board configuration, with very small differences between each other, which is the reason for the introduction of a common msm8998-sony-xperia-yoshino DT. This base configuration includes regulators and project-wide pin configurations and it's made to boot to a serial console. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210909123733.367248-1-angelogioacchino.delregno@somainline.org
2021-09-25arm64: dts: qcom: pm660: Add reboot mode supportShawn Guo1-2/+3
It turns out that the pm660 PON is a GEN2 device. Update the compatible to "qcom,pm8998-pon" and add reboot mode support, so that devices can be rebooted into bootloader and recovery mode. Tested on Xiaomi Redmi Note 7 phone. While at it, drop the unnecessary newline between 'compatible' and 'reg' property. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210824021918.17271-1-shawn.guo@linaro.org
2021-09-25arm64: dts: qcom: sc7280: Add aliases for I2C and SPIRajesh Patil1-0/+32
Add aliases for i2c and spi for sc7280 soc. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1632399378-12229-9-git-send-email-rajpat@codeaurora.org
2021-09-25arm64: dts: qcom: sc7280: Add QUPv3 wrapper_1 nodesRoja Rani Yarubandi2-0/+753
Add QUPv3 wrapper_1 DT nodes for SC7280 SoC. Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1632399378-12229-8-git-send-email-rajpat@codeaurora.org
2021-09-25arm64: dts: qcom: sc7280: Configure uart7 to support bluetooth on sc7280-idpRajesh Patil1-0/+85
Add bluetooth uart pin configuration for sc7280-idp. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1632399378-12229-7-git-send-email-rajpat@codeaurora.org
2021-09-25arm64: dts: qcom: sc7280: Update QUPv3 UART5 DT nodeRoja Rani Yarubandi2-16/+33
Uart5 is treated as dedicated debug uart.Change the compatible as "qcom,geni-uart" in SoC DT to make it generic and later update it as "qcom,geni-debug-uart" in sc7280-idp Add interconnects and power-domains. Split the pinctrl functions and correct the gpio pins. Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1632399378-12229-6-git-send-email-rajpat@codeaurora.org
2021-09-25arm64: dts: qcom: sc7280: Add QUPv3 wrapper_0 nodesRoja Rani Yarubandi1-2/+722
Add QUPv3 wrapper_0 DT nodes for SC7280 SoC. Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1632399378-12229-5-git-send-email-rajpat@codeaurora.org
2021-09-25arm64: dts: qcom: sc7280: Configure SPI-NOR FLASH for sc7280-idpRajesh Patil1-0/+27
Add spi-nor flash node and pinctrl configurations for the SC7280 IDP. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1632399378-12229-4-git-send-email-rajpat@codeaurora.org
2021-09-25arm64: dts: qcom: sc7280: Add QSPI nodeRoja Rani Yarubandi1-0/+61
Add QSPI DT node and qspi_opp_table for SC7280 SoC. Move qspi_opp_table to / because SPI nodes assume any child node is a spi device and so we can't put the table underneath the spi controller. Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1632399378-12229-3-git-send-email-rajpat@codeaurora.org
2021-09-24arm64: dts: qcom: sm6125: Remove leading zeroesFabio Estevam1-3/+3
dtc complains about the leading zeroes: arch/arm64/boot/dts/qcom/sm6125.dtsi:497.19-503.6: Warning (unit_address_format): /soc/timer@f120000/frame@0f121000: unit name should not have leading 0s arch/arm64/boot/dts/qcom/sm6125.dtsi:505.19-510.6: Warning (unit_address_format): /soc/timer@f120000/frame@0f123000: unit name should not have leading 0s arch/arm64/boot/dts/qcom/sm6125.dtsi:512.19-517.6: Warning (unit_address_format): /soc/timer@f120000/frame@0f124000: unit name should not have leading 0 Remove them. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Martin Botka <martin.botka@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210922195208.1734936-1-festevam@gmail.com
2021-09-23arm64: dts: qcom: sc7180: Use maximum drive strength values for eMMCShaik Sajida Bhanu1-2/+2
The current drive strength values are not sufficient on non discrete boards and this leads to CRC errors during switching to HS400 enhanced strobe mode. Hardware simulation results on non discrete boards shows up that use the maximum drive strength values for data and command lines could helps in avoiding these CRC errors. So, update data and command line drive strength values to maximum. Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1629132650-26277-1-git-send-email-sbhanu@codeaurora.org
2021-09-22arm64: dts: qcom: sc7180-trogdor: Enable IPA on LTE only SKUsSujit Kautkar2-11/+11
Enable the IPA node for LTE and skip for wifi-only SKUs Signed-off-by: Sujit Kautkar <sujitka@chromium.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210920113220.v1.1.I904da9664f294fcf222f6f378d37eaadd72ca92e@changeid
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-27 14:32:29 +0300