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2021-10-17arm64: dts: rockchip: change gpio nodenamesJohan Jonker5-22/+22
Currently all gpio nodenames are sort of identical to there label. Nodenames should be of a generic type, so change them all. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20211007144019.7461-3-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-10-16arm64: dts: rockchip: add 'chassis-type' propertyArnaud Ferraris4-0/+5
A new 'chassis-type' root node property has recently been approved for the device-tree specification, in order to provide a simple way for userspace to detect the device form factor and adjust their behavior accordingly. This patch fills in this property for end-user devices (such as laptops, smartphones and tablets) based on Rockchip ARM64 processors. Signed-off-by: Arnaud Ferraris <arnaud.ferraris@collabora.com> Link: https://lore.kernel.org/r/20211016102025.23346-5-arnaud.ferraris@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-10-16arm64: dts: rockchip: add powerdomains to rk3368Heiko Stuebner1-0/+178
Add the core io-domain node for rk3368. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20210925090405.2601792-3-heiko@sntech.de
2021-10-16dt-bindings: arm: rockchip: add rk3368 compatible string to pmu.yamlHeiko Stuebner1-0/+2
Add the compatible for the pmu mfd on rk3368. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210925090405.2601792-1-heiko@sntech.de
2021-10-16arm64: dts: rockchip: enable spdif on Quartz64 ANicolas Frattaroli1-0/+22
Add the necessary nodes to enable the spdif output on the RK3566-Quartz-A board. Co-developed-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Link: https://lore.kernel.org/r/20211015111303.1365328-2-frattaroli.nicolas@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-10-16arm64: dts: rockchip: add spdif node to rk356xPeter Geis1-0/+14
This adds the spdif node to the rk356x device tree. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Link: https://lore.kernel.org/r/20211015111303.1365328-1-frattaroli.nicolas@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-28arm64: dts: rockchip: add pwm nodes for rk3568Liang Chen1-0/+176
Add the pwm controller nodes to the core rk3568 dtsi. Signed-off-by: Liang Chen <cl@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20210726090355.1548483-2-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-23arm64: dts: rockchip: add phandles to muxed i2c buses on rk3368-lionJakob Unterwurzacher1-6/+6
Other DTS files that include the dtsi will want to to add children to the i2c buses from the i2c-mus. Without a label they would have to specify the full path. Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> [add phandles for first mux as well] Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20210922230429.2162535-3-heiko@sntech.de
2021-09-23arm64: dts: rockchip: define iodomains for rk3368-lionJakob Unterwurzacher1-0/+18
This is not strictly needed, as 3.3V is the default, but good to have for descriptive purposes nevertheless. Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> [fixed ordering] Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20210922230429.2162535-2-heiko@sntech.de
2021-09-23arm64: dts: rockchip: fix LDO_REG4 / LDO_REG7 confusion on rk3368-lionJakob Unterwurzacher1-8/+9
LDO_REG7 is used for generating VCC_18. LDO_REG4 is not connected to anything - delete it. Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20210922230429.2162535-1-heiko@sntech.de
2021-09-20arm64: dts: rockchip: align operating-points table name with dtschemaKrzysztof Kozlowski6-11/+11
Align the name of operating-points node to dtschema to fix warnings like: opp-table0: $nodename:0: 'opp-table0' does not match '^opp-table(-[a-z0-9]+)?$' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20210819182311.223443-2-krzysztof.kozlowski@canonical.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-20arm64: dts: rockchip: hook up camera on px30-evbHeiko Stuebner1-0/+52
Enable the isp and csi phy on px30-evb and connect it to the board's ov5695 camera. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20210830141318.66744-2-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-20arm64: dts: rockchip: add isp node for px30Heiko Stuebner1-0/+41
Add the rkisp1 node and iommu for the px30 soc. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20210830141318.66744-1-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-20arm64: dts: rockchip: add Coresight debug range for RK3399Brian Norris1-0/+48
Per Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt. This IP block can be used for sampling the PC of any given CPU, which is useful in certain panic scenarios where you can't get the CPU to stop cleanly (e.g., hard lockup). Reviewed-by: Leo Yan <leo.yan@linaro.org> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Brian Norris <briannorris@chromium.org> Link: https://lore.kernel.org/r/20210908111337.v2.3.Ibc87b4785709543c998cc852c1edaeb7a08edf5c@changeid Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-20arm64: dts: rockchip: Correct regulator for USB host on Odroid-Go2Chris Morgan1-1/+11
When writing a battery driver, I noticed that the USB voltage was ~3.7V while running off of battery on a mainline kernel. After consulting the schematics for the Odroid Go Advance, it appears that the BOOST regulator is involved in the process of powering the USB host. Power for the USB host goes from the vccsys regulator into the PMIC, then out from the PMIC BOOST regulator into the FC9516A (which is controlled by GPIO), which then feeds power into the USB host. I named the regulator usb_midu because on the datasheet the pin is described as "MIDU/BOOST - middle point of USB power supply / boost output". Making these changes solved the USB power issue on battery and I'm now reading approximately 5v. Note that on my board at least there is a difference in time from the USB PHY probing and the regulators being powered on. This causes the USB port to be undervolted for a few seconds during boot up. The solutions to this problem are either 1) to add the proper phy-supply on the host port, or to 2) add regulator-boot-on to the regulator. I chose to add regulator-boot-on because there is an issue with the phy clk that causes a warning when booting (see v1 of this patch series). Basically the clock usb480m is a child of the usb480m_phy clock (used by the USB PHY) and also a critical clock. Setting the phy-supply causes this driver to be EPROBE_DEFERed until the regulator is ready, however upon unregistering the driver to be probed later the system cannot remove the usb480m_phy clock due to a child being marked critical. Changes since v2: - Added notes about clk problem and regulator voltage at boot. - Added regulator-boot-on as a workaround for the voltage at boot. - Removed note about fixed regulator warning, as that has been fixed upstream. Changes since v1: - Removed phy-supply, as this generated a warning in dmesg. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Link: https://lore.kernel.org/r/20210916190938.6175-1-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-20arm64: dts: rockchip: fix PCI reg address warning on rk3399-gruTommaso Merciai1-1/+1
Warning (pci_device_reg): /pcie@f8000000/pcie@0,0:reg: PCI reg address is not configuration space Signed-off-by: Tommaso Merciai <tomm.merciai@gmail.com> Link: https://lore.kernel.org/r/20210918164153.207146-1-tomm.merciai@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: add saradc to rk3568-evb1-v10Michael Riesch1-0/+5
Add the SARADC to the device tree of the RK3568 EVB1. Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20210823110716.10038-1-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: Fix GPU register width for RK3328Alex Bee1-1/+1
As can be seen in RK3328's TRM the register range for the GPU is 0xff300000 to 0xff330000. It would (and does in vendor kernel) overlap with the registers of the HEVC encoder (node/driver do not exist yet in upstream kernel). See already existing h265e_mmu node. Fixes: 752fbc0c8da7 ("arm64: dts: rockchip: add rk3328 mali gpu node") Signed-off-by: Alex Bee <knaerzche@gmail.com> Link: https://lore.kernel.org/r/20210623115926.164861-1-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: Re-add interrupt-names for RK3399's vpuAlex Bee1-0/+1
Commit 53a05c8f6e8e ("arm64: dts: rockchip: remove interrupt-names from iommu nodes") intended to remove the interrupt-names property for mmu nodes, but it also removed it for the vpu node in rk3399.dtsi. That makes the driver fail probing currently. Fix this by re-adding the property for this node. Fixes: 53a05c8f6e8e ("arm64: dts: rockchip: remove interrupt-names from iommu nodes") Signed-off-by: Alex Bee <knaerzche@gmail.com> Link: https://lore.kernel.org/r/20210822115755.3171937-1-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: add missing rockchip,grf property to rk356xMichael Riesch1-0/+1
This commit fixes the error messages rockchip_clk_register_muxgrf: regmap not available rockchip_clk_register_branches: failed to register clock clk_ddr1x: -524 during boot by providing the missing rockchip,grf property. Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Tested-by: Peter Geis <pgwipeout@gmail.com> Link: https://lore.kernel.org/r/20210823123911.12095-2-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: add RK3399 Gru gpio-line-namesBrian Norris2-0/+356
It's convenient to get nice names for GPIOs. In particular, Chrome OS tooling looks for "AP_FLASH_WP" and "AP_FLASH_WP_L". The rest are provided for convenience. Gru-Bob and Gru-Kevin share the gru-chromebook.dtsi, and for the most part they share pin meanings. I omitted a few areas where components were available only on one or the other. Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210820133829.1.Ica46f428de8c3beb600760dbcd63cf879ec24baf@changeid Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: Enable SFC for Odroid Go AdvanceChris Morgan1-0/+16
This enables the Rockchip Serial Flash Controller for the Odroid Go Advance. Note that while the attached SPI NOR flash and the controller both support quad read mode, only 2 of the required 4 pins are present. The rx bus width is set to 2 for this reason, and tx bus width is set to 1 for compatibility reasons. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Link: https://lore.kernel.org/r/20210812134639.31586-2-jon.lin@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: Add SFC to RK3308Chris Morgan1-0/+37
Add a devicetree entry for the Rockchip SFC for the RK3308 SOC. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Link: https://lore.kernel.org/r/20210812134639.31586-1-jon.lin@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: Add SFC to PX30Chris Morgan1-0/+38
Add a devicetree entry for the Rockchip SFC for the PX30 SOC. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Link: https://lore.kernel.org/r/20210812134546.31340-4-jon.lin@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: add thermal support to Quartz64 Model APeter Geis1-0/+33
Add the thermal nodes for the Quartz64 Model A. The Model A supports a single speed gpio fan. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Link: https://lore.kernel.org/r/20210728180034.717953-9-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: add rk3568 tsadc nodesPeter Geis2-0/+79
Add the thermal and tsadc nodes to the rk3568 device tree. There are two sensors, one for the cpu, one for the gpu. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Link: https://lore.kernel.org/r/20210728180034.717953-6-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: add rk356x gpio debounce clocksPeter Geis1-5/+5
The rk356x added a debounce clock to the gpio devices. This clock is necessary for the new v2 gpio driver to bind. Add the clocks to the rk356x device tree. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Link: https://lore.kernel.org/r/20210728180034.717953-4-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: add pinctrl and alias to emmc node to rk3568-evb1-v10Michael Riesch1-0/+3
Since the EMMC pins can be used for other functions as well, we need to configure the pinctrl. Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20210805120107.27007-8-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: add node for sd card to rk3568-evb1-v10Michael Riesch1-0/+14
Add the SD card reader to the device tree of the RK3568 EVB1. Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20210805120107.27007-7-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: add regulators of rk809 pmic to rk3568-evb1-v10Michael Riesch1-0/+221
Add the regulators of the RK809 PMIC to the device tree of the RK3568 EVB1. Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20210805120107.27007-6-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: enable io domains on rk3568-evb1-v10Michael Riesch1-0/+13
Enable the PMU IO domains in the device tree for the RK3568 EVB1. Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20210805120107.27007-5-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: add core io domains node for rk356xMichael Riesch1-0/+5
Enable the PMU IO domains for the RK3566 and the RK3568. Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20210805120107.27007-4-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: add thermal fan control to rockpro64Peter Geis1-0/+29
The rockpro64 had a fan node since commit 5882d65c1691 ("arm64: dts: rockchip: Add PWM fan for RockPro64") however it was never tied into the thermal driver for automatic control. Add the links to the thermal node to permit the kernel to handle this automatically. Borrowed from the (rk3399-khadas-edge.dtsi). Signed-off-by: Peter Geis <pgwipeout@gmail.com> Link: https://lore.kernel.org/r/20210730151727.729822-1-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: Setup USB typec port as datarole on for Pinebook ProDan Johansen1-1/+1
Some chargers try to put the charged device into device data role. Before this commit this condition caused the tcpm state machine to issue a hard reset due to a capability missmatch. Signed-off-by: Dan Johansen <strit@manjaro.org> Link: https://lore.kernel.org/r/20210805220426.2693062-1-strit@manjaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: Add gru-scarlet-dumo boardChen-Yu Tsai2-0/+42
Dumo is another variant of Scarlet, also known as the ASUS Chromebook Tablet CT100. This is almost the same as Scarlet-Innolux, but uses a board-specific calibration variant for the WiFi module. Add a new device tree for it. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210812094753.2359087-3-wenst@chromium.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15dt-bindings: arm: rockchip: Add gru-scarlet-dumo boardChen-Yu Tsai1-0/+28
Dumo is another variant of Scarlet, also known as the ASUS Chromebook Tablet CT100. This is almost the same as Scarlet-Innolux, but uses a specific calibration variant for the WiFi module. Add an entry for the board compatibles. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210812094753.2359087-2-wenst@chromium.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: rk3568-evb1-v10: add ethernet supportMichael Riesch1-0/+57
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20210729093913.8917-3-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: add gmac0 node to rk3568Michael Riesch1-0/+49
While both RK3566 and RK3568 feature the gmac1 node, the gmac0 node is exclusive to the RK3568. Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20210729093913.8917-2-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: enable gmac node on quartz64-aPeter Geis1-0/+38
Enable the gmac controller on the Pine64 Quartz64 Model A. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Link: https://lore.kernel.org/r/20210728180034.717953-8-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: adjust rk3568 pll clocksPeter Geis1-0/+2
The rk3568 gpll should run at 1200mhz and the ppll should run at 200mhz. These are set incorrectly by the bootloader, so fix them here. gpll boots at 1188mhz, but to get most accurate dividers for all gpll_dividers it needs to run at 1200mhz, otherwise everyone downstream isn't quite right. ppll feeds the combophys, which has a divide by 2 clock, so 200mhz is required to reach a 100mhz clock input for them. The vendor-kernel also makes this fix. Signed-off-by: Peter Geis <pgwipeout@gmail.com> [pulled deeper explanation from discussion into commit message] Link: https://lore.kernel.org/r/20210728180034.717953-7-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: add rk356x gmac1 nodePeter Geis1-0/+47
Add the gmac1 controller to the rk356x device tree. This is the controller common to both the rk3568 and rk3566. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Link: https://lore.kernel.org/r/20210728180034.717953-5-pgwipeout@gmail.com [adjusted sorting a bit] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: fix rk3568 mbi-aliasPeter Geis1-1/+1
The mbi-alias incorrectly points to 0xfd100000 when it should point to 0xfd410000. This fixes MSIs on rk3568. Fixes: a3adc0b9071d ("arm64: dts: rockchip: add core dtsi for RK3568 SoC") Signed-off-by: Peter Geis <pgwipeout@gmail.com> Link: https://lore.kernel.org/r/20210728180034.717953-2-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: Add VPU support for the PX30Paul Kocialkowski1-0/+22
The PX30 has a VPU (both decoder and encoder) with a dedicated IOMMU. Describe these two entities in device-tree. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Link: https://lore.kernel.org/r/20210728230040.17368-1-ezequiel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: add watchdog to rk3568Liang Chen1-0/+8
Add the watchdog node to rk3568. Signed-off-by: Liang Chen <cl@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20210622102907.99242-2-heiko@sntech.de
2021-09-15arm64: dts: rockchip: add isp1 node on rk3399Heiko Stuebner1-0/+26
ISP1 is supplied by the tx1rx1 dphy, that is controlled from inside the dsi1 controller, so include the necessary phy-link for it. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Tested-by: Sebastian Fricke <sebastian.fricke@posteo.net> Acked-by: Helen Koike <helen.koike@collabora.com> Link: https://lore.kernel.org/r/20210210111020.2476369-7-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: add cif clk-control pinctrl for rk3399Heiko Stuebner1-0/+12
This enables variant a of the clkout signal for camera applications and also the cifclkin pinctrl setting. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Tested-by: Sebastian Fricke <sebastian.fricke@posteo.net> Acked-by: Helen Koike <helen.koike@collabora.com> Link: https://lore.kernel.org/r/20210210111020.2476369-6-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: add #phy-cells to mipi-dsi1 on rk3399Heiko Stuebner1-0/+1
The dsi controller includes access to the dphy which might be used not only for dsi output but also for csi input on dsi1, so add the necessary #phy-cells to allow it to be used as phy. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Tested-by: Sebastian Fricke <sebastian.fricke@posteo.net> Acked-by: Helen Koike <helen.koike@collabora.com> Link: https://lore.kernel.org/r/20210210111020.2476369-5-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: add basic dts for Pine64 Quartz64-APeter Geis3-0/+432
Add a basic dts for the Pine64 Quartz64 Model A Single Board Computer. This board outputs on uart2 for debug. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210710151034.32857-5-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: add rk3566 dtsiPeter Geis1-0/+20
Add the rk3566 dtsi which includes the soc specific changes for this chip. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Link: https://lore.kernel.org/r/20210710151034.32857-4-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-15arm64: dts: rockchip: split rk3568 device treePeter Geis2-36/+48
In preparation for the rk3566 inclusion, split apart the rk3568 specific nodes into a separate device tree. This allows us to create the rk3566 device tree without deleting nodes. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Link: https://lore.kernel.org/r/20210710151034.32857-3-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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