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2019-09-11mmc: mmc_spi: Convert to use for_each_sg()Andy Shevchenko1-1/+1
Use for_each_sg() macro instead of open coded variant. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhi: fill in actual_clockTamás Szűcs1-5/+8
Save set clock in mmc_host actual_clock enabling exporting it via debugfs. This will indicate the precise SD clock in I/O settings rather than only the sometimes misleading requested clock. Signed-off-by: Tamás Szűcs <tszucs@protonmail.ch> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci: use lower/upper_32_bits() macros for DMA addressesMasahiro Yamada1-14/+13
Currently, the DMA addresses are casted to (u64) for the upper 32bits to avoid "right shift count >= width of type" warning. <linux/kernel.h> provides macros to address this, and I like the macro names are self-documenting. I introduced a new helper, sdhci_set_adma_addr() to avoid the code duplication. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-cadence: override spec versionMasahiro Yamada1-0/+2
The datasheet of the IP (sd4hc) says it is compiatible with SDHCI v4, but the spec version field in the version register is read as 2 (i.e. SDHCI_SPEC_300) based on the RTL provided by Cadence. Socionext did not fix it up when it integrated the IP into the SoCs. So, it is working as SDHCI v3. It is not a real problem because there is no difference in the program flow in sdhci.c between SDHCI_SPEC_300/400, but set the real version just in case. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci: constify references of parameters to __sdhci_read_caps()Masahiro Yamada2-3/+4
__sdhci_read_caps() does not modify *ver, *caps, or *caps1. Probably, the caller of this function will want to constifythe parameters passed in. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: mediatek: enable SDIO IRQ low level trigger functionyong mao1-0/+2
SDIO IRQ is not defaultly triggered by low level, but by falling edge. It needs to set related register to enable SDIO IRQ low level trigger function. Otherwise the SDIO IRQ may be lost in some specail condition. Signed-off-by: Yong Mao <yong.mao@mediatek.com> Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci: Export sdhci_abort_tuning function symbolBen Chuang2-1/+3
Export sdhci_abort_tuning() function symbols which are used by other SD Host controller driver modules. Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Co-developed-by: Michael K Johnson <johnsonm@danlj.org> Signed-off-by: Michael K Johnson <johnsonm@danlj.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11PCI: Add Genesys Logic, Inc. Vendor IDBen Chuang1-0/+2
Add the Genesys Logic, Inc. vendor ID to pci_ids.h. Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Co-developed-by: Michael K Johnson <johnsonm@danlj.org> Signed-off-by: Michael K Johnson <johnsonm@danlj.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci: Add PLL Enable support to internal clock setupBen Chuang2-0/+24
The GL9750 and GL9755 chipsets, and possibly others, require PLL Enable setup as part of the internal clock setup as described in 3.2.1 Internal Clock Setup Sequence of SD Host Controller Simplified Specification Version 4.20. Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Co-developed-by: Michael K Johnson <johnsonm@danlj.org> Signed-off-by: Michael K Johnson <johnsonm@danlj.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci: Change timeout of loop for checking internal clock stableBen Chuang1-2/+2
According to section 3.2.1 internal clock setup in SD Host Controller Simplified Specifications 4.20, the timeout of loop for checking internal clock stable is defined as 150ms. Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Co-developed-by: Michael K Johnson <johnsonm@danlj.org> Signed-off-by: Michael K Johnson <johnsonm@danlj.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-of-arasan: Add Support for Intel LGM eMMCRamuthevar Vadivel Muruganx1-0/+15
The current arasan sdhci PHY configuration isn't compatible with the PHY on Intel's LGM(Lightning Mountain) SoC devices. Therefore, add a new compatible, to adapt the Intel's LGM eMMC PHY with arasan-sdhc controller to configure the PHY. Signed-off-by: Ramuthevar Vadivel Muruganx <vadivel.muruganx.ramuthevar@linux.intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11dt-bindings: mmc: sdhci-of-arasan: Add new compatible for Intel LGM eMMCRamuthevar Vadivel Murugan1-0/+17
Add a new compatible to use the sdhc-arasan host controller driver with the eMMC PHY on Intel's Lightning Mountain SoC. Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-of-aspeed: Fix return value check in aspeed_sdc_probe()Wei Yongjun1-2/+2
In case of error, the function of_platform_device_create() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11dt-bindings: mmc: sdhci-of-aspeed: Update example ranges propertyAndrew Jeffery1-1/+2
The example node in the binding uses the AST2500 compatible string for the SD controller with a 64kiB ranges property, but the SD controller is allocated 128kiB of MMIO space according to the AST2500 datasheet. Fix the example to correctly reflect the hardware in the AST2500, however it should be noted that the MMIO region is reduced to 64kiB in the AST2600 where a second SD controller block has been introduced into the address space. Also add the IBM copyright header that I left out of the initial patch. Suggested-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: bcm2835: Take SWIOTLB memory size limitation into accountStefan Wahren1-1/+1
Make sure the sdhost driver doesn't use requests bigger than SWIOTLB can handle. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-of-aspeed: Add support for the ASPEED SD controllerAndrew Jeffery3-0/+345
Add a minimal driver for ASPEED's SD controller, which exposes two SDHCIs. The ASPEED design implements a common register set for the SDHCIs, and moves some of the standard configuration elements out to this common area (e.g. 8-bit mode, and card detect configuration which is not currently supported). The SD controller has a dedicated hardware interrupt that is shared between the slots. The common register set exposes information on which slot triggered the interrupt; early revisions of the patch introduced an irqchip for the register, but reality is it doesn't behave as an irqchip, and the result fits awkwardly into the irqchip APIs. Instead I've taken the simple approach of using the IRQ as a shared IRQ with some minor performance impact for the second slot. Ryan was the original author of the patch - I've taken his work and massaged it to drop the irqchip support and rework the devicetree integration. The driver has been smoke tested under qemu against a minimal SD controller model and lightly tested on an ast2500-evb. Signed-off-by: Ryan Chen <ryanchen.aspeed@gmail.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11dt-bindings: mmc: sdhci-of-aspeed: Document Aspeed SD controllerAndrew Jeffery1-0/+105
The ASPEED SD/SDIO/MMC controller exposes two slots implementing the SDIO Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit data bus if only a single slot is enabled. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: mediatek: support 24bits segment sizeChaotian Jing1-3/+13
MSDC IP which support 64G DRAM will support 24bits BDMA buffer length, so add support it. Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: mediatek: fix controller busy when plug out SDChaotian Jing1-3/+5
when plug out SD card, may get data CRC error, the MMC core will issue CMD13 to get card status, then CMD13 timeout(due to card plug out) will trigger CMD19 tuning, first CMD19 timeout has not call msdc_reset_hw() and cause the next CMD19 gets controller busy. Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: renesas_sdhi_sys_dmac: Remove all R-Car Gen3 SoCsYoshihiro Shimoda1-36/+0
All R-Car Gen3 SoCs with any ES version cannot use this DMAC actually. So, this patch removes the compatibles of R-Car Gen3 SoCs from renesas_sdhi_sys_dmac_of_match. Since the previous code has an empty whitelist to prevent probing of R-Car Gen3 SoCs, no behavior changes. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: jz4740: Drop dependency on arch headerPaul Cercueil1-4/+0
We don't need to set the 'slave_id' anymore - that field is never read by the DMA driver. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: jz4740: Code cleanupPaul Cercueil1-7/+7
Fix wrong code indentation which made the code hard to read, and fix return with value in void function. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-cadence: use struct_size() helperGustavo A. R. Silva1-3/+2
One of the more common cases of allocation size calculations is finding the size of a structure that has a zero-sized array at the end, along with memory for some number of elements for that array. For example: struct sdhci_cdns_priv { ... struct sdhci_cdns_phy_param phy_params[0]; }; Make use of the struct_size() helper instead of an open-coded version in order to avoid any potential type mistakes. So, replace the following form: sizeof(*priv) + sizeof(priv->phy_params[0]) * nr_phy_params with: struct_size(priv, phy_params, nr_phy_params) Also, notice that, in this case, variable priv_size is not necessary, hence it is removed. This code was detected with the help of Coccinelle. Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-of-esdhc: add erratum A011334 support in ls1028a 1.0 SoCYinbo Zhu1-0/+1
This patch is to add erratum A011334 support in ls1028a 1.0 SoC Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: Remove dev_err() usage after platform_get_irq()Stephen Boyd10-19/+4
We don't need dev_err() messages when platform_get_irq() fails now that platform_get_irq() prints an error message itself when something goes wrong. Let's remove these prints with a simple semantic patch. // <smpl> @@ expression ret; struct platform_device *E; @@ ret = ( platform_get_irq(E, ...) | platform_get_irq_byname(E, ...) ); if ( \( ret < 0 \| ret <= 0 \) ) { ( -if (ret != -EPROBE_DEFER) -{ ... -dev_err(...); -... } | ... -dev_err(...); ) ... } // </smpl> While we're here, remove braces on if statements that only have one statement (manually). Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: linux-mmc@vger.kernel.org Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-pci: Add another Id for Intel CMLAdrian Hunter2-0/+2
Add another PCI Id for Intel CML. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-s3c: Mark expected switch fall-throughGustavo A. R. Silva1-0/+1
Mark switch cases where we are expecting to fall through. This patch fixes the following warnings: drivers/mmc/host/sdhci-s3c.c: In function 'sdhci_s3c_probe': drivers/mmc/host/sdhci-s3c.c:613:19: warning: this statement may fall through [-Wimplicit-fallthrough=] host->mmc->caps |= MMC_CAP_8_BIT_DATA; drivers/mmc/host/sdhci-s3c.c:614:2: note: here case 4: ^~~~ Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: atmel-mci: Mark expected switch fall-throughsGustavo A. R. Silva1-0/+4
Mark switch cases where we are expecting to fall through. This patch fixes the following warnings: drivers/mmc/host/atmel-mci.c: In function 'atmci_get_cap': drivers/mmc/host/atmel-mci.c:2415:30: warning: this statement may fall through [-Wimplicit-fallthrough=] host->caps.has_odd_clk_div = 1; ~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~ drivers/mmc/host/atmel-mci.c:2416:2: note: here case 0x400: ^~~~ drivers/mmc/host/atmel-mci.c:2422:28: warning: this statement may fall through [-Wimplicit-fallthrough=] host->caps.has_highspeed = 1; ~~~~~~~~~~~~~~~~~~~~~~~~~^~~ drivers/mmc/host/atmel-mci.c:2423:2: note: here case 0x200: ^~~~ drivers/mmc/host/atmel-mci.c:2426:40: warning: this statement may fall through [-Wimplicit-fallthrough=] host->caps.need_notbusy_for_read_ops = 1; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~ drivers/mmc/host/atmel-mci.c:2427:2: note: here case 0x100: ^~~~ Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Reviewed-by: Kees Cook <keescook@chromium.org> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-pltfm: Use devm_platform_ioremap_resource() to simplify codeJisheng Zhang1-3/+1
devm_platform_ioremap_resource() wraps platform_get_resource() and devm_ioremap_resource() in a single helper, let's use that helper to simplify the code. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: mmci: Clarify comments and some code for busy detectionUlf Hansson1-32/+37
The code dealing with busy detection is somewhat complicated. In a way to make it a bit clearer, let's try to clarify the comments in the code about it. Additionally, move the part for clearing the so called busy start IRQ, to the place where the IRQ is actually delivered. Ideally, this should make the code a bit more robust. Finally, to improve understanding of the code and the sequence of the busy detection, move the corresponding code around a bit in mmci_cmd_irq(). Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Jean Nicolas GRAUX <jean-nicolas.graux@st.com> Reviewed-by: Jean Nicolas GRAUX <jean-nicolas.graux@st.com>
2019-09-11memstick: r592: Use dev_get_drvdataChuhong Yuan1-4/+2
Instead of using to_pci_dev + pci_get_drvdata, use dev_get_drvdata to make code simpler. Signed-off-by: Chuhong Yuan <hslester96@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-pci: Use dev_get_drvdataChuhong Yuan1-8/+4
Instead of using to_pci_dev + pci_get_drvdata, use dev_get_drvdata to make code simpler. Signed-off-by: Chuhong Yuan <hslester96@gmail.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-iproc: Add support for emmc2 of the BCM2711Stefan Wahren1-0/+9
The additional emmc2 interface of the BCM2711 is an improved version of the old emmc controller, which is able to provide DDR50 mode on the Raspberry Pi 4. Except 32 bit only register access no other quirks are known yet. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Reviewed-by: Matthias Brugger <mbrugger@suse.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11dt-bindings: mmc: sdhci-iproc: Add brcm,bcm2711-emmc2Stefan Wahren1-1/+3
Add a new compatible for the additional emmc2 controller on BCM2711 and clearify usage. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Reviewed-by: Matthias Brugger <mbrugger@suse.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11dt-bindings: mmc: sunxi: Add H5 compatiblesMaxime Ripard1-0/+6
The conversion to the YAML binding left out two compatibles. Add them. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11dt-bindings: mmc: sunxi: reorder MMC compatiblesMaxime Ripard1-4/+4
The MMC compatibles in the bindings are not ordered as they should, so let's make sure it's sorted. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: mxs: use devm_platform_ioremap_resource() to simplify codeAnson Huang1-3/+1
Use the new helper devm_platform_ioremap_resource() which wraps the platform_get_resource() and devm_ioremap_resource() together, to simplify the code. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: usdhi6rol0: Add maintainersLars Persson1-0/+1
The usdhi6rol0 driver is exclusively used for the ARTPEC family of SoCs. Other SoCs with the same IP of Panasonic origin use the tmio_mmc driver. Therefore we assigner maintainer responsibility to us at Axis until the two drivers become unified. Signed-off-by: Lars Persson <larper@axis.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11Revert "mmc: sdhci: Remove unneeded quirk2 flag of O2 SD host controller"Daniel Drake1-1/+1
This reverts commit 414126f9e5abf1973c661d24229543a9458fa8ce. This commit broke eMMC storage access on a new consumer MiniPC based on AMD SoC, which has eMMC connected to: 02:00.0 SD Host controller: O2 Micro, Inc. Device 8620 (rev 01) (prog-if 01) Subsystem: O2 Micro, Inc. Device 0002 During probe, several errors are seen including: mmc1: Got data interrupt 0x02000000 even though no data operation was in progress. mmc1: Timeout waiting for hardware interrupt. mmc1: error -110 whilst initialising MMC card Reverting this commit allows the eMMC storage to be detected & usable again. Signed-off-by: Daniel Drake <drake@endlessm.com> Fixes: 414126f9e5ab ("mmc: sdhci: Remove unneeded quirk2 flag of O2 SD host controller") Cc: stable@vger.kernel.org # v5.1+ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11Revert "mmc: bcm2835: Terminate timeout work synchronously"Stefan Wahren1-1/+1
The commit 37fefadee8bb ("mmc: bcm2835: Terminate timeout work synchronously") causes lockups in case of hardware timeouts due the timeout work also calling cancel_delayed_work_sync() on its own. So revert it. Fixes: 37fefadee8bb ("mmc: bcm2835: Terminate timeout work synchronously") Cc: stable@vger.kernel.org Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11Merge tag 'mac80211-next-for-davem-2019-09-11' of ↵David S. Miller19-161/+274
git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211-next Johannes Berg says: ==================== We have a number of changes, but things are settling down: * a fix in the new 6 GHz channel support * a fix for recent minstrel (rate control) updates for an infinite loop * handle interface type changes better wrt. management frame registrations (for management frames sent to userspace) * add in-BSS RX time to survey information * handle HW rfkill properly if !CONFIG_RFKILL * send deauth on IBSS station expiry, to avoid state mismatches * handle deferred crypto tailroom updates in mac80211 better when device restart happens * fix a spectre-v1 - really a continuation of a previous patch * advertise NL80211_CMD_UPDATE_FT_IES as supported if so * add some missing parsing in VHT extended NSS support * support HE in mac80211_hwsim * let mac80211 drivers determine the max MTU themselves along with the usual cleanups etc. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2019-09-11gpio: creg-snps: use devm_platform_ioremap_resource() to simplify codeYueHaibing1-3/+1
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20190906131032.22148-1-yuehaibing@huawei.com Acked-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-11gpio: devres: Switch to EXPORT_SYMBOL_GPL()Geert Uytterhoeven1-14/+14
Change all exported symbols for managed GPIO functions from EXPORT_SYMBOL() to EXPORT_SYMBOL_GPL(), like is used for their non-managed counterparts. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20190906084539.21838-5-geert+renesas@glider.be Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-11gpio: of: Switch to EXPORT_SYMBOL_GPL()Geert Uytterhoeven1-4/+4
All exported functions provide genuine Linux-specific functionality. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20190906084539.21838-4-geert+renesas@glider.be Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-11gpio: of: Make of_gpio_simple_xlate() privateGeert Uytterhoeven2-14/+3
Since commit 9a95e8d25a140ba9 ("gpio: remove etraxfs driver"), there are no more users of of_gpio_simple_xlate() outside gpiolib-of.c. All GPIO drivers that need it now rely on of_gpiochip_add() setting it up as the default translate function. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20190906084539.21838-3-geert+renesas@glider.be Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-11gpio: of: Make of_get_named_gpiod_flags() privateGeert Uytterhoeven2-8/+1
Since commit f626d6dfb7098525 ("gpio: of: Break out OF-only code"), there are no more users of of_get_named_gpiod_flags() outside gpiolib-of.c. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20190906084539.21838-2-geert+renesas@glider.be Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-11KVM: x86: Return to userspace with internal error on unexpected exit reasonLiran Alon3-5/+17
Receiving an unexpected exit reason from hardware should be considered as a severe bug in KVM. Therefore, instead of just injecting #UD to guest and ignore it, exit to userspace on internal error so that it could handle it properly (probably by terminating guest). In addition, prefer to use vcpu_unimpl() instead of WARN_ONCE() as handling unexpected exit reason should be a rare unexpected event (that was expected to never happen) and we prefer to print a message on it every time it occurs to guest. Furthermore, dump VMCS/VMCB to dmesg to assist diagnosing such cases. Reviewed-by: Mihai Carabas <mihai.carabas@oracle.com> Reviewed-by: Nikita Leshenko <nikita.leshchenko@oracle.com> Reviewed-by: Joao Martins <joao.m.martins@oracle.com> Signed-off-by: Liran Alon <liran.alon@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-09-11Merge branches 'arm/omap', 'arm/exynos', 'arm/smmu', 'arm/mediatek', ↵Joerg Roedel63-1472/+3851
'arm/qcom', 'arm/renesas', 'x86/amd', 'x86/vt-d' and 'core' into next
2019-09-11iommu/vt-d: Declare Broadwell igfx dmar support snafuChris Wilson1-9/+35
Despite the widespread and complete failure of Broadwell integrated graphics when DMAR is enabled, known over the years, we have never been able to root cause the issue. Instead, we let the failure undermine our confidence in the iommu system itself when we should be pushing for it to be always enabled. Quirk away Broadwell and remove the rotten apple. References: https://bugs.freedesktop.org/show_bug.cgi?id=89360 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Lu Baolu <baolu.lu@linux.intel.com> Cc: Martin Peres <martin.peres@linux.intel.com> Cc: Joerg Roedel <joro@8bytes.org> Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2019-09-11iommu/vt-d: Add Scalable Mode fault informationKyung Min Park2-4/+75
Intel VT-d specification revision 3 added support for Scalable Mode Translation for DMA remapping. Add the Scalable Mode fault reasons to show detailed fault reasons when the translation fault happens. Link: https://software.intel.com/sites/default/files/managed/c5/15/vt-directed-io-spec.pdf Reviewed-by: Sohil Mehta <sohil.mehta@intel.com> Signed-off-by: Kyung Min Park <kyung.min.park@intel.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-03 18:48:46 +0300