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2016-05-03Merge branches 'pci/dpc', 'pci/resource' and 'pci/thunderbolt' into nextBjorn Helgaas11-12/+213
* pci/dpc: PCI: Add Downstream Port Containment driver PCI: Add Downstream Port Containment portdrv service type PCI: Widen portdrv service type from 4 bits to 8 bits * pci/resource: alpha/PCI: Call iomem_is_exclusive() for IORESOURCE_MEM, but not IORESOURCE_IO PCI: Supply CPU physical address (not bus address) to iomem_is_exclusive() * pci/thunderbolt: thunderbolt: Fix double free of drom buffer
2016-05-03Merge branches 'pci/host-armada', 'pci/host-designware', 'pci/host-hv', ↵Bjorn Helgaas21-131/+673
'pci/host-imx6', 'pci/host-keystone', 'pci/host-mvebu', 'pci/host-rcar', 'pci/host-thunder' and 'pci/host-vmd' into next * pci/host-armada: PCI: armada: Add driver for Marvell Armada 7K/8K PCIe controller dt-bindings: pci: add DT binding for Marvell Armada 7K/8K PCIe controller * pci/host-designware: PCI: designware: Remove incorrect RC memory base/limit configuration PCI: designware: Move Root Complex setup code to dw_pcie_setup_rc() * pci/host-hv: PCI: hv: Report resources release after stopping the bus * pci/host-imx6: ARM: dts: imx6qp: Specify imx6qp version of PCIe core PCI: imx6: Implement reset sequence for i.MX6+ PCI: imx6: Use enum instead of bool for variant indicator PCI: imx6: Add DT property for link gen, default to Gen1 PCI: imx6: Add reset-gpio-active-high boolean property to DT ARM: dts: imx6: Fix PCIe reset GPIO polarity on Toradex Apalis Ixora PCI: imx6: Add initial imx6sx support PCI: imx6: Factor out ref clock enable Revert "PCI: imx6: Add support for active-low reset GPIO" * pci/host-keystone: PCI: keystone: Remove unnecessary goto statement PCI: keystone: Add error IRQ handler * pci/host-mvebu: PCI: mvebu: Use SET_NOIRQ_SYSTEM_SLEEP_PM_OPS for mvebu_pcie_pm_ops PCI: mvebu: Constify mvebu_pcie_pm_ops structure * pci/host-rcar: PCI: rcar: Select PCI_MSI_IRQ_DOMAIN * pci/host-thunder: PCI: thunder: Don't clobber read-only bits in bridge config registers * pci/host-vmd: PCI: Remove return values from pcie_port_platform_notify() and relatives PCI/ACPI: Allow all PCIe services on non-ACPI host bridges
2016-05-03PCI: Add Downstream Port Containment driverKeith Busch4-0/+196
Add driver for the PCI Express Downstream Port Containment extended capability. DPC is an optional capability to contain uncorrectable errors below a port. For more information on DPC, please see PCI Express Base Specification Revision 4, section 7.31, or view the PCI-SIG DPC ECN here: https://pcisig.com/sites/default/files/specification_documents/ECN_DPC_2012-02-09_finalized.pdf When a DPC event is triggered, the hardware disables downstream links, so the DPC driver schedules removal for all devices below this port. This may happen concurrently with a PCIe hotplug driver if enabled. When all downstream devices are removed and the link state transitions to disabled, the DPC driver clears the DPC status and interrupt bits so the link may retrain for a newly connected device. [bhelgaas: clear (not set) DPC_CTL bits on remove, whitespace cleanup] Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Lukas Wunner <lukas@wunner.de>
2016-05-03PCI: Add Downstream Port Containment portdrv service typeKeith Busch5-4/+9
Add the Downstream Port Containment (PCIE_PORT_SERVICE_DPC) portdrv service type, available if the device has the DPC extended capability. [bhelgaas: split to separate patch, changelog] Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-05-03PCI: Widen portdrv service type from 4 bits to 8 bitsKeith Busch2-2/+2
The names of port service devices previously used one nibble to encode the port type and another nibble to encode the service type. We're about to add a fifth service type, so change device names to use one *byte* to encode the service type. For example, a hotplug port service on a downstream bridge was previously called "pcie24" and is now called "pcie204". The "2" encodes the device type (PCI_EXP_TYPE_DOWNSTREAM - 4), and the "4" (now "04") encodes the service (PCIE_PORT_SERVICE_HP). Based on Lukas Wunner's patch: https://github.com/l1k/linux/commit/b688d6e4873ab082e5916b1a993bc1d38c6f4178 [bhelgaas: split to separate patch, expand changelog] Based-on-patch-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-05-03PCI: designware: Remove incorrect RC memory base/limit configurationGabriele Paoloni1-8/+0
Currently dw_pcie_setup_rc() configures memory base and memory limit in the type1 configuration header for the root complex. In doing so it uses the CPU address (pp->mem_base) rather than the bus address (pp->mem_bus_addr). This is wrong and it is useless since the configuration is overwritten later on when pci_bus_assign_resources() is called. Remove this configuration from dw_pcie_setup_rc(). Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
2016-05-02PCI: hv: Report resources release after stopping the busVitaly Kuznetsov1-5/+5
Kernel hang is observed when pci-hyperv module is release with device drivers still attached. E.g., when I do 'rmmod pci_hyperv' with BCM5720 device pass-through-ed (tg3 module) I see the following: NMI watchdog: BUG: soft lockup - CPU#1 stuck for 22s! [rmmod:2104] ... Call Trace: [<ffffffffa0641487>] tg3_read_mem+0x87/0x100 [tg3] [<ffffffffa063f000>] ? 0xffffffffa063f000 [<ffffffffa0644375>] tg3_poll_fw+0x85/0x150 [tg3] [<ffffffffa0649877>] tg3_chip_reset+0x357/0x8c0 [tg3] [<ffffffffa064ca8b>] tg3_halt+0x3b/0x190 [tg3] [<ffffffffa0657611>] tg3_stop+0x171/0x230 [tg3] ... [<ffffffffa064c550>] tg3_remove_one+0x90/0x140 [tg3] [<ffffffff813bee59>] pci_device_remove+0x39/0xc0 [<ffffffff814a3201>] __device_release_driver+0xa1/0x160 [<ffffffff814a32e3>] device_release_driver+0x23/0x30 [<ffffffff813b794a>] pci_stop_bus_device+0x8a/0xa0 [<ffffffff813b7ab6>] pci_stop_root_bus+0x36/0x60 [<ffffffffa02c3f38>] hv_pci_remove+0x238/0x260 [pci_hyperv] The problem seems to be that we report local resources release before stopping the bus and removing devices from it and device drivers may try to perform some operations with these resources on shutdown. Move resources release report after we do pci_stop_root_bus(). Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jake Oshins <jakeo@microsoft.com>
2016-05-02ARM: dts: imx6qp: Specify imx6qp version of PCIe coreAndrey Smirnov1-0/+3
I.MX6Quad Plus has a slightly different version of PCIe core than reqular i.MX6Quad. Tested-by: Gary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-05-02PCI: imx6: Implement reset sequence for i.MX6+Andrey Smirnov3-3/+23
I.MX6+ has a dedicated bit for resetting PCIe core, which should be used instead of a regular reset sequence since using the latter will hang the SoC. This commit is based on c34068d48273e24d392d9a49a38be807954420ed from http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git Tested-by: Gary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-05-02PCI: imx6: Use enum instead of bool for variant indicatorAndrey Smirnov1-58/+69
Use enumerated type instead of a boolean flag to specify the variant of the PCIe IP block (6Q, 6SX, etc). This patch has zero functional impact, however it makes the code easier to extend for the case of more than 2 possible variants of an IP block (of which there are). [bhelgaas: rewrap comment, remove extra blank line] Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-05-02PCI: thunder: Don't clobber read-only bits in bridge config registersDavid Daney1-8/+34
The 32-bit addressing modes in the I/O and Prefetchable Memory registers are required to be read-only. Since the underlying access method allows them to be set, emulate their read-only nature and always set them. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-05-02thunderbolt: Fix double free of drom bufferAndreas Noever1-0/+1
If tb_drom_read() fails, sw->drom is freed but not set to NULL. sw->drom is then freed again in the error path of tb_switch_alloc(). The bug can be triggered by unplugging a thunderbolt device shortly after it is detected by the thunderbolt driver. Clear sw->drom if tb_drom_read() fails. [bhelgaas: add Fixes:, stable versions of interest] Fixes: 343fcb8c70d7 ("thunderbolt: Fix nontrivial endpoint devices.") Signed-off-by: Andreas Noever <andreas.noever@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v3.17+ CC: Lukas Wunner <lukas@wunner.de>
2016-05-02PCI: rcar: Select PCI_MSI_IRQ_DOMAINArnd Bergmann1-0/+2
The R-Car PCIe driver requires the use of IRQ domains for its MSI code: drivers/pci/host/pcie-rcar.c:635:9: error: implicit declaration of function 'irq_find_mapping' [-Werror=implicit-function-declaration] drivers/pci/host/pcie-rcar.c:666:8: error: implicit declaration of function 'irq_create_mapping' [-Werror=implicit-function-declaration] ... Add a Kconfig select to ensure that the feature is always enabled. This is not consistent with what the other drivers do at the moment, but I have another patch that changes them to do it like this one, which is more logical. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Simon Horman <horms+renesas@verge.net.au>
2016-04-26PCI: armada: Add driver for Marvell Armada 7K/8K PCIe controllerThomas Petazzoni3-0/+274
The Marvell Armada 7K/8K SoCs integrate a PCIe controller from Synopsys. Add a new driver that provides the small glue needed to use the existing Designware driver to make it work on Marvell Armada 7K/8K SoCs. The MSI support will be enabled at a later point. [bhelgaas: use dev_dbg(), dw_pcie_wait_for_link()] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-04-26dt-bindings: pci: add DT binding for Marvell Armada 7K/8K PCIe controllerThomas Petazzoni1-0/+38
This commit adds the Device Tree binding documentation that allows to describe the PCIe controller found in Marvell Armada 7K/8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <rob@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-04-25alpha/PCI: Call iomem_is_exclusive() for IORESOURCE_MEM, but not IORESOURCE_IOBjorn Helgaas1-2/+2
The alpha pci_mmap_resource() is used for both IORESOURCE_MEM and IORESOURCE_IO resources, but iomem_is_exclusive() is only applicable for IORESOURCE_MEM. Call iomem_is_exclusive() only for IORESOURCE_MEM resources, and do it earlier to match the generic version of pci_mmap_resource(). Fixes: 10a0ef39fbd1 ("PCI/alpha: pci sysfs resources") Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
2016-04-25PCI: Supply CPU physical address (not bus address) to iomem_is_exclusive()Bjorn Helgaas1-4/+3
iomem_is_exclusive() requires a CPU physical address, but on some arches we supplied a PCI bus address instead. On most arches, pci_resource_to_user(res) returns "res->start", which is a CPU physical address. But on microblaze, mips, powerpc, and sparc, it returns the PCI bus address corresponding to "res->start". The result is that pci_mmap_resource() may fail when it shouldn't (if the bus address happens to match an existing resource), or it may succeed when it should fail (if the resource is exclusive but the bus address doesn't match it). Call iomem_is_exclusive() with "res->start", which is always a CPU physical address, not the result of pci_resource_to_user(). Fixes: e8de1481fd71 ("resource: allow MMIO exclusivity for device drivers") Suggested-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Arjan van de Ven <arjan@linux.intel.com>
2016-04-25Merge branches 'pci/enumeration', 'pci/hotplug', 'pci/misc', 'pci/ntb', ↵Bjorn Helgaas17-68/+287
'pci/thunderbolt' and 'pci/virtualization' into next * pci/enumeration: x86/PCI: Refine PCI support check in pcibios_init() * pci/hotplug: PCI: acpiphp_ibm: Avoid uninitialized variable reference * pci/misc: PCI: Fix spelling errors * pci/ntb: PCI: Add DMA alias quirk for mic_x200_dma PCI: Add support for multiple DMA aliases PCI: Move informational printk to pci_add_dma_alias() PCI: Add pci_add_dma_alias() to abstract implementation * pci/thunderbolt: thunderbolt: Support 1st gen Light Ridge controller thunderbolt: Fix typos and magic number PCI: Add Intel Thunderbolt device IDs * pci/virtualization: PCI: Work around Intel Sunrise Point PCH incorrect ACS capability PCI: Reverse standard ACS vs device-specific ACS enabling PCI: Mark Intel i40e NIC INTx masking as broken
2016-04-25PCI: keystone: Remove unnecessary goto statementMurali Karicheri1-9/+14
Fix the misuse of goto statement in ks_pcie_get_irq_controller_info() as simple return is more appropriate for this function. While at it add an error log for absence of interrupt controller node. [bhelgaas: drop "ret" altogether since we always know the return value] Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Rob Herring <robh+dt@kernel.org> CC: Pawel Moll <pawel.moll@arm.com> CC: Mark Rutland <mark.rutland@arm.com> CC: Ian Campbell <ijc+devicetree@hellion.org.uk> CC: Kumar Gala <galak@codeaurora.org>
2016-04-20PCI: imx6: Add DT property for link gen, default to Gen1Tim Harvey2-7/+21
Freescale has stated [1] that the LVDS clock source of the IMX6 does not pass the PCI Gen2 clock jitter test, therefore unless an external Gen2 compliant external clock source is present and supplied back to the IMX6 PCIe core via LVDS CLK1/CLK2 you can not claim Gen2 compliance. Add a DT property to specify Gen1 vs Gen2 and check this before allowing a Gen2 link. We default to Gen1 if the property is not present because at this time there are no IMX6 boards in mainline that 'input' a clock on LVDS CLK1/CLK2. In order to be Gen2 compliant on IMX6 you need to: - Have a Gen2 compliant external clock generator and route that clock back to either LVDS CLK1 or LVDS CLK2 as an input (see IMX6SX-SabreSD reference design). - Specify this clock in the PCIe node in the DT (i.e., IMX6QDL_CLK_LVDS1_IN or IMX6QDL_CLK_LVDS2_IN instead of IMX6QDL_CLK_LVDS1_GATE which configures it as a CLK output). [1] https://community.freescale.com/message/453209 Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Zhu Richard <Richard.Zhu@freescale.com> CC: Akshay Bhat <akshay.bhat@timesys.com> CC: Rob Herring <robh+dt@kernel.org> CC: Shawn Guo <shawnguo@kernel.org>
2016-04-20PCI: imx6: Add reset-gpio-active-high boolean property to DTPetr Štetiar2-3/+17
Currently the reset-gpio DT property which controls the PCI bus device reset signal defaults to active-low reset sequence (L=reset state, H=operation state) plus the code in reset function isn't GPIO polarity aware - it doesn't matter if the defined reset-gpio is active-low or active-high, it will always result into active-low reset sequence. I've tried to fix it properly and change the reset-gpio reset sequence to be polarity-aware, but this patch has been accepted and then reverted as it has introduced few backward incompatible issues: 1. Some DTBs, for example, imx6qdl-sabresd, don't define reset-gpio polarity correctly: reset-gpio = <&gpio7 12 0>; which means that it's defined as active-high, but in reality it's active-low; thus it wouldn't work without a DTS fix. 2. The logic in the reset function is inverted: gpio_set_value_cansleep(imx6_pcie->reset_gpio, 0) msleep(100); gpio_set_value_cansleep(imx6_pcie->reset_gpio, 1); so even if some of the i.MX6 boards had reset-gpio polarity defined correctly in their DTSes, they would stop working. As we can't break old DTBs, we can't fix them, so we need to introduce this new DT reset-gpio-active-high boolean property so we can support boards with active-high reset sequence. This active-high reset sequence is for example needed on Apalis SoMs, where GPIO1_IO28, used to PCIe reset is not connected directly to PERST# PCIe signal, but it's ORed with RESETBMCU coming off the PMIC, and thus is inverted, active-high. Tested-by: Tim Harvey <tharvey@gateworks.com> # Gateworks Ventana boards (which have active-low PERST#) Signed-off-by: Petr Štetiar <ynezz@true.cz> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org>
2016-04-20ARM: dts: imx6: Fix PCIe reset GPIO polarity on Toradex Apalis IxoraPetr Štetiar1-2/+3
Adding reset-gpio-active-high boolean DT binding property, which we need to make PCIe working on Apalis SoMs and not break old DTBs. While at it, I've fixed comment and GPIO polarity. On Apalis SoMs the GPIO1_IO28 used to PCIe reset is not connected directly to PERST# PCIe signal, but it's ORed with RESETBMCU coming off the PMIC, and thus is inverted, active-high. Signed-off-by: Petr Štetiar <ynezz@true.cz> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-04-20PCI: imx6: Add initial imx6sx supportChristoph Fritz2-2/+59
Add initial PCIe support for the imx6 SoC derivate imx6sx. PCI MSI support is untested as the necessary suspend/resume quirk is not included in this patch. This patch is heavily based on patches by Richard Zhu. [bhelgaas: factor out refclk enable, fix adjacent typos in imx6q-pcie.txt] Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com> Acked-by: Richard Zhu <Richard.Zhu@freescale.com> Acked-by: Lucas Stach <l.stach@pengutronix.de>
2016-04-20PCI: imx6: Factor out ref clock enableBjorn Helgaas1-12/+24
Factor out ref clock enable to make it cleaner to add imx6sx support. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Christoph Fritz <chf.fritz@googlemail.com>
2016-04-20PCI: Work around Intel Sunrise Point PCH incorrect ACS capabilityAlex Williamson1-0/+78
Intel Sunrise Point root ports implement ACS but use dwords for the capability and control registers, putting the control register at the wrong offset. Use quirks to enable and test ACS for these devices, which match the standard functions modulo the broken control register offset. Note that lspci assumes devices implement ACS per spec, so it shows invalid ACS data for these devices. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-04-20PCI: Reverse standard ACS vs device-specific ACS enablingAlex Williamson3-10/+13
The original thought was that if a device implemented ACS, then surely we want to use that... well, it turns out that devices can make an ACS capability so broken that we still need to fall back to quirks. Reverse the order of ACS enabling to give quirks first shot at it. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-04-20PCI: Mark Intel i40e NIC INTx masking as brokenAlex Williamson1-0/+33
All of the i40e (XL710/X710) 10/20/40GbE NICs lack support for indicating INTx is asserted via the interrupt bit in the PCI status register. The DisINTx bit in the command register is functional, causing these devices to be incorrectly detected as supporting INTx masking. Quirk them to properly indicate no INTx masking support. Device IDs copied from i40e_devids.h. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: John Ronciak <john.ronciak@intel.com> CC: Jesse Brandeburg <jesse.brandeburg@intel.com>
2016-04-15PCI: acpiphp_ibm: Avoid uninitialized variable referenceDan Carpenter1-0/+2
If ibm_get_table_from_acpi() fails then "table" isn't initialized. Check for failure so we don't reference "table" unless it's been initialized. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-04-14PCI: keystone: Add error IRQ handlerMurali Karicheri4-0/+74
Keystone PCI hardware generates error interrupts at RC using a platform IRQ instead of a standard MSI or legacy IRQ. Add a simple error handler that logs the fatal interrupt status to the console. [bhelgaas: s/node/dev->of_node/, tidy comments, return irqreturn_t directly] Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org> CC: Pawel Moll <pawel.moll@arm.com> CC: Mark Rutland <mark.rutland@arm.com> CC: Ian Campbell <ijc+devicetree@hellion.org.uk> CC: Kumar Gala <galak@codeaurora.org>
2016-04-12PCI: Add DMA alias quirk for mic_x200_dmaJacek Lawrynowicz1-0/+15
The MIC x200 NTB forwards DMA transactions upstream using multiple alien RIDs. These RIDs have to be added as aliases to the DMA device to allow buffer access when the IOMMU is enabled. Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com> Acked-by: David Woodhouse <David.Woodhouse@intel.com>
2016-04-11x86/PCI: Refine PCI support check in pcibios_init()Adrian-Ken Rueegsegger1-1/+1
Also consider raw_pci_ext_ops when validating if a system has PCI support. This leads to proper resource allocation via pcibios_resource_survey() in the case where PCI config space is exclusively accessed through MMCONFIG. Signed-off-by: Adrian-Ken Rueegsegger <ken@codelabs.ch> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-04-11PCI: Add support for multiple DMA aliasesJacek Lawrynowicz5-17/+32
Solve IOMMU support issues with PCIe non-transparent bridges that use Requester ID look-up tables (RID-LUT), e.g., the PEX8733. The NTB connects devices in two independent PCI domains. Devices separated by the NTB are not able to discover each other. A PCI packet being forwared from one domain to another has to have its RID modified so it appears on correct bus and completions are forwarded back to the original domain through the NTB. The RID is translated using a preprogrammed table (LUT) and the PCI packet propagates upstream away from the NTB. If the destination system has IOMMU enabled, the packet will be discarded because the new RID is unknown to the IOMMU. Adding a DMA alias for the new RID allows IOMMU to properly recognize the packet. Each device behind the NTB has a unique RID assigned in the RID-LUT. The current DMA alias implementation supports only a single alias, so it's not possible to support mutiple devices behind the NTB when IOMMU is enabled. Enable all possible aliases on a given bus (256) that are stored in a bitset. Alias devfn is directly translated to a bit number. The bitset is not allocated for devices that have no need for DMA aliases. More details can be found in the following article: http://www.plxtech.com/files/pdf/technical/expresslane/RTC_Enabling%20MulitHostSystemDesigns.pdf Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com> Acked-by: David Woodhouse <David.Woodhouse@intel.com> Acked-by: Joerg Roedel <jroedel@suse.de>
2016-04-11PCI: Move informational printk to pci_add_dma_alias()Bjorn Helgaas2-5/+3
One of the quirks that adds DMA aliases logs an informational message in dmesg. Move that to pci_add_dma_alias() so all users log the message consistently. No functional change intended (except extra message). Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
2016-04-11PCI: Add pci_add_dma_alias() to abstract implementationBjorn Helgaas3-12/+22
Add a pci_add_dma_alias() interface to encapsulate the details of adding an alias. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
2016-04-08PCI: Remove return values from pcie_port_platform_notify() and relativesJon Derrick3-19/+10
Now that pcie_port_acpi_setup() always returns 0, make it and its callers void functions and stop checking the return values. [bhelgaas: changelog] Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-04-08PCI/ACPI: Allow all PCIe services on non-ACPI host bridgesJon Derrick1-2/+2
Host bridges we discover via ACPI, i.e., PNP0A03 and PNP0A08 devices, may have an _OSC method by which the OS can ask the platform for control of PCIe features like native hotplug, power management events, AER, etc. Previously, if we found a bridge without an ACPI device, we assumed we did not have permission to use any of these PCIe features. That seems unreasonably restrictive. If we find no ACPI device, assume we can take control of all PCIe features. The Intel Volume Management Device (VMD) is one such bridge with no ACPI device. Prior to this change, users had to boot with "pcie_ports=native" to get hotplug and other services to work below the VMD Root Port. [bhelgaas: changelog] Suggested-by: Bjorn Helgaas <helgaas@kernel.org> Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-04-08thunderbolt: Support 1st gen Light Ridge controllerLukas Wunner4-4/+44
Add support for the 1st gen Light Ridge controller, which is built into these systems: iMac12,1 2011 21.5" iMac12,2 2011 27" Macmini5,1 2011 i5 2.3 GHz Macmini5,2 2011 i5 2.5 GHz Macmini5,3 2011 i7 2.0 GHz MacBookPro8,1 2011 13" MacBookPro8,2 2011 15" MacBookPro8,3 2011 17" MacBookPro9,1 2012 15" MacBookPro9,2 2012 13" Light Ridge (CV82524) was the very first copper Thunderbolt controller, introduced 2010 alongside its fiber-optic cousin Light Peak (CVL2510). Consequently the chip suffers from some teething troubles: - MSI is broken for hotplug signaling on the downstream bridges: The chip just never sends an interrupt. It requests 32 MSIs for each of its six bridges and the pcieport driver only allocates one per bridge. However I've verified that even if 32 MSIs are allocated there's no interrupt on hotplug. The only option is thus to disable MSI, which is also what OS X does. Apparently all Thunderbolt chips up to revision 1 of Cactus Ridge 4C are plagued by this issue so quirk those as well. - The chip supports a maximum hop_count of 32, unlike its successors which support only 12. Fixup ring_interrupt_active() to cope with values >= 32. - Another peculiarity is that the chip supports a maximum of 13 ports whereas its successors support 12. However the additional port (#5) seems to be unusable as reading its TB_CFG_PORT config space results in TB_CFG_ERROR_INVALID_CONFIG_SPACE. Add a quirk to mark the port disabled on the root switch, assuming that's necessary on all Macs using this chip. Tested-by: Lukas Wunner <lukas@wunner.de> [MacBookPro9,1] Tested-by: William Brown <william@blackhats.net.au> [MacBookPro8,2] Signed-off-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Andreas Noever <andreas.noever@gmail.com>
2016-04-08thunderbolt: Fix typos and magic numberLukas Wunner6-10/+10
Fix typo in tb_cfg_print_error() message. Fix bytecount in struct tb_drom_entry_port comment. Replace magic number in tb_switch_alloc(). Rename tb_sw_set_unpplugged() and TB_CAL_IECS to fix typos. [bhelgaas: no functional change intended] Signed-off-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Andreas Noever <andreas.noever@gmail.com>
2016-04-08PCI: Add Intel Thunderbolt device IDsLukas Wunner4-13/+38
Intel Gen 1 and 2 chips use the same ID for NHI, bridges and switch. Gen 3 chips and onward use a distinct ID for the NHI. No functional change intended. Signed-off-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Andreas Noever <andreas.noever@gmail.com>
2016-04-07PCI: mvebu: Use SET_NOIRQ_SYSTEM_SLEEP_PM_OPS for mvebu_pcie_pm_opsJisheng Zhang1-2/+3
Use the SET_NOIRQ_SYSTEM_SLEEP_PM_OPS helper macro for mvebu_pcie_pm_ops. The macro also sets up freeze_noirq, thaw_noirq and poweroff_noirq, restore_noirq accordingly. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2016-04-07PCI: mvebu: Constify mvebu_pcie_pm_ops structureJisheng Zhang1-1/+1
The mvebu_pcie_pm_ops structure is never modified, so declare it as const. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2016-04-06PCI: designware: Move Root Complex setup code to dw_pcie_setup_rc()Jisheng Zhang2-22/+21
dw_pcie_host_init() looks up host bridge resources, ioremaps them, creates IRQ domains, and enumerates devices below the bridge. dw_pcie_setup_rc() programs the Root Complex registers. The Root Complex may lose power during suspend-to-RAM, and when we resume, we want to redo the latter but not the former. Move some Root Complex programming from dw_pcie_host_init() to dw_pcie_setup_rc() where it belongs. DesignWare-based drivers can call dw_pcie_setup_rc() in their resume paths. [Niklas Cassel <niklas.cassel@axis.com>: This change moves outbound ATU programming, which uses pp->mem_base, to dw_pcie_setup_rc(). Apply the dra7xx pp->mem_base update before calling dw_pcie_setup_rc().] [bhelgaas: changelog, fold in dra7xx fix from Niklas] Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
2016-04-06Revert "PCI: imx6: Add support for active-low reset GPIO"Fabio Estevam1-6/+14
Commit 5c5fb40de8f1 ("PCI: imx6: Add support for active-low reset GPIO") cause regressions on some boards like MX6 Gateworks Ventana, for example. The reason for the breakage is that this commit sets the GPIO polarity in the wrong logic level. Also, the commit log is wrong because active-low reset GPIO is what the driver used to support since the beginning. So keep the old behavior that ignores the GPIO polarity specified in the device tree and treat the PCI reset GPIO as active-low. Reported-by: Krzysztof Hałasa <khalasa@piap.pl> Tested-by: Tim Harvey <tharvey@gateworks.com> # Gateworks Ventana Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Acked-by: Lucas Stach <l.stach@pengutronix.de> CC: stable@vger.kernel.org # v4.5+
2016-04-05PCI: Fix spelling errorsColin Ian King2-2/+2
Fix spelling of "initalization". [bhelgaas: also fix pci/pci.c] Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-04-03Linux 4.6-rc2v4.6-rc2Linus Torvalds1-1/+1
2016-04-03Merge branch 'perf-urgent-for-linus' of ↵Linus Torvalds12-35/+98
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull perf fixes from Ingo Molnar: "Misc kernel side fixes: - fix event leak - fix AMD PMU driver bug - fix core event handling bug - fix build bug on certain randconfigs Plus misc tooling fixes" * 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf/x86/amd/ibs: Fix pmu::stop() nesting perf/core: Don't leak event in the syscall error path perf/core: Fix time tracking bug with multiplexing perf jit: genelf makes assumptions about endian perf hists: Fix determination of a callchain node's childlessness perf tools: Add missing initialization of perf_sample.cpumode in synthesized samples perf tools: Fix build break on powerpc perf/x86: Move events_sysfs_show() outside CPU_SUP_INTEL perf bench: Fix detached tarball building due to missing 'perf bench memcpy' headers perf tests: Fix tarpkg build test error output redirection
2016-04-03Merge branch 'core-urgent-for-linus' of ↵Linus Torvalds9-58/+158
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull core kernel fixes from Ingo Molnar: "This contains the nohz/atomic cleanup/fix for the fetch_or() ugliness you noted during the original nohz pull request, plus there's also misc fixes: - fix liblockdep build bug - fix uapi header build bug - print more lockdep hash collision info to help debug recent reports of hash collisions - update MAINTAINERS email address" * 'core-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: MAINTAINERS: Update my email address locking/lockdep: Print chain_key collision information uapi/linux/stddef.h: Provide __always_inline to userspace headers tools/lib/lockdep: Fix unsupported 'basename -s' in run_tests.sh locking/atomic, sched: Unexport fetch_or() timers/nohz: Convert tick dependency mask to atomic_t locking/atomic: Introduce atomic_fetch_or()
2016-04-03v4l2-mc: avoid warning about unused variableLinus Torvalds1-1/+1
Commit 840f5b0572ea ("media: au0828 disable tuner to demod link in au0828_media_device_register()") removed all uses of the 'dtv_demod', but left the variable itself around. Remove it. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-04-03Merge branch 'x86-urgent-for-linus' of ↵Linus Torvalds12-30/+246
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fixes from Thomas Gleixner: "This lot contains: - Some fixups for the fallout of the topology consolidation which unearthed AMD/Intel inconsistencies - Documentation for the x86 topology management - Support for AMD advanced power management bits - Two simple cleanups removing duplicated code" * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/cpu: Add advanced power management bits x86/thread_info: Merge two !__ASSEMBLY__ sections x86/cpufreq: Remove duplicated TDP MSR macro definitions x86/Documentation: Start documenting x86 topology x86/cpu: Get rid of compute_unit_id perf/x86/amd: Cleanup Fam10h NB event constraints x86/topology: Fix AMD core count
2016-04-03Merge tag 'rproc-v4.6-rc1' of git://github.com/andersson/remoteprocLinus Torvalds2-2/+5
Pull remoteproc fix from Bjorn Andersson: "Fix incorrect error check in the ST remoteproc driver and advertise the newly created linux-remoteproc mailing list" * tag 'rproc-v4.6-rc1' of git://github.com/andersson/remoteproc: MAINTAINERS: Add mailing list for remote processor subsystems remoteproc: st: fix check of syscon_regmap_lookup_by_phandle() return value
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-02 22:57:25 +0300