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2016-09-13crypto: omap-sham - fix software fallback handlingTero Kristo1-1/+1
If we have processed any data with the hardware accelerator (digcnt > 0), we must complete the entire hash by using it. This is because the current hash value can't be imported to the software fallback algorithm. Otherwise we end up with wrong hash results. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-09-13crypto: omap-sham - avoid executing tasklet where not neededTero Kristo1-5/+15
Some of the call paths of OMAP SHA driver can avoid executing the next step of the crypto queue under tasklet; instead, execute the next step directly via function call. This avoids a costly round-trip via the scheduler giving a slight performance boost. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-09-13crypto: arm64/aes-ctr - fix NULL dereference in tail processingArd Biesheuvel1-1/+1
The AES-CTR glue code avoids calling into the blkcipher API for the tail portion of the walk, by comparing the remainder of walk.nbytes modulo AES_BLOCK_SIZE with the residual nbytes, and jumping straight into the tail processing block if they are equal. This tail processing block checks whether nbytes != 0, and does nothing otherwise. However, in case of an allocation failure in the blkcipher layer, we may enter this code with walk.nbytes == 0, while nbytes > 0. In this case, we should not dereference the source and destination pointers, since they may be NULL. So instead of checking for nbytes != 0, check for (walk.nbytes % AES_BLOCK_SIZE) != 0, which implies the former in non-error conditions. Fixes: 49788fe2a128 ("arm64/crypto: AES-ECB/CBC/CTR/XTS using ARMv8 NEON and Crypto Extensions") Cc: stable@vger.kernel.org Reported-by: xiakaixu <xiakaixu@huawei.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-09-13crypto: arm/aes-ctr - fix NULL dereference in tail processingArd Biesheuvel1-1/+1
The AES-CTR glue code avoids calling into the blkcipher API for the tail portion of the walk, by comparing the remainder of walk.nbytes modulo AES_BLOCK_SIZE with the residual nbytes, and jumping straight into the tail processing block if they are equal. This tail processing block checks whether nbytes != 0, and does nothing otherwise. However, in case of an allocation failure in the blkcipher layer, we may enter this code with walk.nbytes == 0, while nbytes > 0. In this case, we should not dereference the source and destination pointers, since they may be NULL. So instead of checking for nbytes != 0, check for (walk.nbytes % AES_BLOCK_SIZE) != 0, which implies the former in non-error conditions. Fixes: 86464859cc77 ("crypto: arm - AES in ECB/CBC/CTR/XTS modes using ARMv8 Crypto Extensions") Cc: stable@vger.kernel.org Reported-by: xiakaixu <xiakaixu@huawei.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-09-13crypto: skcipher - Fix blkcipher walk OOM crashHerbert Xu1-1/+2
When we need to allocate a temporary blkcipher_walk_next and it fails, the code is supposed to take the slow path of processing the data block by block. However, due to an unrelated change we instead end up dereferencing the NULL pointer. This patch fixes it by moving the unrelated bsize setting out of the way so that we enter the slow path as inteded. Fixes: 7607bd8ff03b ("[CRYPTO] blkcipher: Added blkcipher_walk_virt_block") Cc: stable@vger.kernel.org Reported-by: xiakaixu <xiakaixu@huawei.com> Reported-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-09-13crypto: echainiv - Replace chaining with multiplicationHerbert Xu1-91/+24
The current implementation uses a global per-cpu array to store data which are used to derive the next IV. This is insecure as the attacker may change the stored data. This patch removes all traces of chaining and replaces it with multiplication of the salt and the sequence number. Fixes: a10f554fa7e0 ("crypto: echainiv - Add encrypted chain IV...") Cc: stable@vger.kernel.org Reported-by: Mathias Krause <minipli@googlemail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-09-07crypto: arm/ghash - change internal cra_name to "__ghash"Ard Biesheuvel1-1/+1
The fact that the internal synchrous hash implementation is called "ghash" like the publicly visible one is causing the testmgr code to misidentify it as an algorithm that requires testing at boottime. So rename it to "__ghash" to prevent this. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-09-07PCI: Fix cavium quirk compile failure with PCI_ATS offHerbert Xu1-1/+1
The newly added quirk_cavium_sriov_rnm_link doesn't compile if PCI_ATS is off. This patch adds a check for PCI_ATS. Fixes: 21b5b8eebbae ("PCI: quirk fixup for cavium invalid sriov...") Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-09-07hwrng: pasemi - Migrate to managed APIPrasannaKumar Muralidharan1-30/+7
Use devm_ioremap and devm_hwrng_register instead of ioremap and hwrng_register. This removes unregistering and error handling code. Changes in v2: Remove hardcoded resource size in ioremap, use resource struct obtained by calling platform_get_resource. Removing hardcoded resource size was suggested by LABBE Corentin. CC: Darren Stevens <darren@stevens-zone.net> Suggested-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-09-07crypto: mv_cesa - remove NO_IRQ referenceArnd Bergmann1-5/+2
Drivers should not use NO_IRQ, as we are trying to get rid of that. In this case, the call to irq_of_parse_and_map() is both wrong (as it returns '0' on failure, not NO_IRQ) and unnecessary (as platform_get_irq() does the same thing) This removes the call to irq_of_parse_and_map() and checks for the error code correctly. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-09-07crypto: ccp - add missing release in ccp_dmaengine_registerQuentin Lambert1-2/+5
ccp_dmaengine_register used to return with an error code before releasing all resource. This patch adds a jump to the appropriate label ensuring that the resources are properly released before returning. This issue was found with Hector. Signed-off-by: Quentin Lambert <lambert.quentin@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-09-07crypto: arm/ghash-ce - add missing async import/exportArd Biesheuvel1-0/+24
Since commit 8996eafdcbad ("crypto: ahash - ensure statesize is non-zero"), all ahash drivers are required to implement import()/export(), and must have a non-zero statesize. Fix this for the ARM Crypto Extensions GHASH implementation. Fixes: 8996eafdcbad ("crypto: ahash - ensure statesize is non-zero") Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-09-07crypto: arm/sha1-neon - add support for building in Thumb2 modeArd Biesheuvel1-1/+0
The ARMv7 NEON module is explicitly built in ARM mode, which is not supported by the Thumb2 kernel. So remove the explicit override, and leave it up to the build environment to decide whether the core SHA1 routines are assembled as ARM or as Thumb2 code. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-09-07crypto: algif_hash - Handle NULL hashes correctlyHerbert Xu1-12/+61
Right now attempting to read an empty hash simply returns zeroed bytes, this patch corrects this by calling the digest function using an empty input. Reported-by: Russell King - ARM Linux <linux@armlinux.org.uk> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-09-07crypto: caam - fix rfc3686(ctr(aes)) IV loadCatalin Vasile2-42/+57
-nonce is being loaded using append_load_imm_u32() instead of append_load_as_imm() (nonce is a byte array / stream, not a 4-byte variable) -counter is not being added in big endian format, as mandatated by RFC3686 and expected by the crypto engine Signed-off-by: Catalin Vasile <cata.vasile@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-09-07crypto: engine - permit to enqueue ashash_requestCorentin LABBE4-62/+189
The current crypto engine allow only ablkcipher_request to be enqueued. Thus denying any use of it for hardware that also handle hash algo. This patch modify the API for allowing to enqueue ciphers and hash. Since omap-aes/omap-des are the only users, this patch also convert them to the new cryptoengine API. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-09-07crypto: engine - move crypto engine to its own headerCorentin LABBE5-70/+93
This patch move the whole crypto engine API to its own header crypto/engine.h. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-09-07crypto: qat - fix incorrect accelerator mask for C3X devicesMaksim Lukoshkov1-1/+1
Fix incorrect value of ADF_C3XXX_ACCELERATORS_MASK. Signed-off-by: Maksim Lukoshkov <maksim.lukoshkov@intel.com> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-09-07hwrng: bcm2835 - handle of_iomap failuresArvind Yadav1-2/+3
Check return value of of_iomap and handle errors correctly. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-09-07crypto: cryptd - initialize child shash_desc on importArd Biesheuvel1-2/+7
When calling .import() on a cryptd ahash_request, the structure members that describe the child transform in the shash_desc need to be initialized like they are when calling .init() Cc: stable@vger.kernel.org Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-31crypto: FIPS - allow tests to be disabled in FIPS modeStephan Mueller2-0/+13
In FIPS mode, additional restrictions may apply. If these restrictions are violated, the kernel will panic(). This patch allows test vectors for symmetric ciphers to be marked as to be skipped in FIPS mode. Together with the patch, the XTS test vectors where the AES key is identical to the tweak key is disabled in FIPS mode. This test vector violates the FIPS requirement that both keys must be different. Reported-by: Tapas Sarangi <TSarangi@trustwave.com> Signed-off-by: Stephan Mueller <smueller@chronox.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-31crypto: qat - fix constants table DMAMaksim Lukoshkov1-8/+12
Copy const_tab array into DMA-able memory (accesible by qat hw). Signed-off-by: Maksim Lukoshkov <maksim.lukoshkov@intel.com> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-31hwrng: tx4939 - Use devm_hwrng_register instead of hwrng_registerPrasannaKumar Muralidharan1-10/+1
By using devm_hwrng_register instead of hwrng_register the .remove callback in platform_driver can be removed. This reduces a few lines in code. Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-31hwrng: Remove check for max less than 4 bytesPrasannaKumar Muralidharan2-6/+0
HW RNG core never asks for data less than 4 bytes. The check whether max is less than 4 bytes is unnecessary. Remove the check. Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-31crypto: xor - Fix warning when XOR_SELECT_TEMPLATE is unsetHerbert Xu1-4/+5
This patch fixes an unused label warning triggered when the macro XOR_SELECT_TEMPLATE is not set. Fixes: 39457acda913 ("crypto: xor - skip speed test if the xor...") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Suggested-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-31hwrng: amd - Convert to new hwrng read() APICorentin LABBE1-19/+28
This patch convert the hwrng interface used by amd768-rng to its new API by replacing data_read()/data_present() by read(). Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-31hwrng: amd - Access hardware via ioread32/iowrite32Corentin LABBE1-6/+25
Instead of accessing hw directly via pmbase, it's better to access after ioport_map() via ioread32/iowrite32. Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-31hwrng: amd - Replace global variable with private structCorentin LABBE1-19/+38
Instead of having two global variable, it's better to use a private struct. This will permit to remove amd_pdev variable Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-31hwrng: amd - release_region must be called after hwrng_unregisterCorentin LABBE1-1/+2
The driver release the memory region before being sure that nobody use it. This patch made hwrng_unregister ran before any release was done. Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-31hwrng: amd - Remove asm/io.hCorentin LABBE1-4/+3
checkpatch complains about <asm/io.h> used instead of linux/io.h. In fact it is not needed. This patch remove it, and in the process, alphabetize the other headers. Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-31hwrng: amd - Be consitent with the driver nameCorentin LABBE1-6/+5
The driver name is displayed each time differently. This patch make use of the same name everywhere. Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-31hwrng: amd - use the BIT macroCorentin LABBE1-3/+3
This patch add usage of the BIT() macro Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-31hwrng: amd - Fix style problem with blank lineCorentin LABBE1-5/+1
Some blank line are unncessary, and one is missing after declaration. This patch fix thoses style problems. Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-31crypto: caam - add missing header dependenciesBaoyou Xie1-0/+1
We get 1 warning when biuld kernel with W=1: drivers/crypto/caam/ctrl.c:398:5: warning: no previous prototype for 'caam_get_era' [-Wmissing-prototypes] In fact, this function is declared in drivers/crypto/caam/ctrl.h, so this patch add missing header dependencies. Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-31hwrng: cavium - Add Cavium HWRNG driver for ThunderX SoC.Omer Khaliq4-0/+207
The Cavium ThunderX SoC has a hardware random number generator. This driver provides support using the HWRNG framework. Signed-off-by: Omer Khaliq <okhaliq@caviumnetworks.com> Signed-off-by: Ananth Jasty <Ananth.Jasty@cavium.com> Acked-by: David Daney <david.daney@cavium.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-31PCI: quirk fixup for cavium invalid sriov link value.Ananth Jasty1-0/+11
Cavium cn88xx hardware presents an incorrect SR-IOV Function Dependency Link, add a fixup quirk for the affected devices. Acked-by: David Daney <david.daney@cavium.com> Signed-off-by: Ananth Jasty <Ananth.Jasty@cavium.com> Signed-off-by: Omer Khaliq <okhaliq@caviumnetworks.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-31crypto: caam - fix IV loading for authenc (giv)decryptionHoria Geantă1-40/+37
For algorithms that implement IV generators before the crypto ops, the IV needed for decryption is initially located in req->src scatterlist, not in req->iv. Avoid copying the IV into req->iv by modifying the (givdecrypt) descriptors to load it directly from req->src. aead_givdecrypt() is no longer needed and goes away. Cc: <stable@vger.kernel.org> # 4.3+ Fixes: 479bcc7c5b9e ("crypto: caam - Convert authenc to new AEAD interface") Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-31crypto: cryptd - Use correct tfm object for AEAD trackingHerbert Xu1-1/+2
The AEAD code path incorrectly uses the child tfm to track the cryptd refcnt, and then potentially frees the child tfm. Fixes: 81760ea6a95a ("crypto: cryptd - Add helpers to check...") Reported-by: Sowmini Varadhan <sowmini.varadhan@oracle.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-24crypto: rockchip - use devm_add_action_or_reset()Sudip Mukherjee1-4/+2
If devm_add_action() fails we are explicitly calling the cleanup to free the resources allocated. Lets use the helper devm_add_action_or_reset() and return directly in case of error, as we know that the cleanup function has been already called by the helper if there was any error. Signed-off-by: Sudip Mukherjee <sudip.mukherjee@codethink.co.uk> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-24crypto: rsa - allow keys >= 2048 bits in FIPS modeStephan Mueller1-2/+2
With a public notification, NIST now allows the use of RSA keys with a modulus >= 2048 bits. The new rule allows any modulus size >= 2048 bits provided that either 2048 or 3072 bits are supported at least so that the entire RSA implementation can be CAVS tested. This patch fixes the inability to boot the kernel in FIPS mode, because certs/x509.genkey defines a 4096 bit RSA key per default. This key causes the RSA signature verification to fail in FIPS mode without the patch below. Signed-off-by: Stephan Mueller <smueller@chronox.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-24crypto: mxc-scc - check clk_prepare_enable() errorFabio Estevam1-1/+3
clk_prepare_enable() may fail, so we should better check its return value and propagate it in the case of failure. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-24hwrng: omap3-rom - Remove obsoleted functionsPrasannaKumar Muralidharan1-8/+2
Remove omap3_rom_rng_data_present method as it was returning 1 always. Use .read callback instead of .data_read callback. This avoids use of obsolete callbacks. This patch is not tested with hardware as I don't have access to it. Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-24crypto: drbg - fix error return codeWei Yongjun1-5/+11
Fix to return a negative error code from the error handling case instead of 0. Signed-off-by: Wei Yongjun <weiyj.lk@gmail.com> Acked-by: Stephan Mueller <smueller@chronox.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-24crypto: sun4i-ss - fix missing unlock on error in sun4i_hash()Wei Yongjun1-1/+2
Add the missing unlock before return from function sun4i_hash() in the error handling case. Fixes: 477d9b2e591b ("crypto: sun4i-ss - unify update/final function") Signed-off-by: Wei Yongjun <weiyj.lk@gmail.com> Acked-by: Corentin LABBE <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-24crypto: xor - skip speed test if the xor function is selected automaticallyMartin Schwidefsky1-21/+19
If the architecture selected the xor function with XOR_SELECT_TEMPLATE the speed result of the do_xor_speed benchmark is of limited value. The speed measurement increases the bootup time a little, which can makes a difference for kernels used in container like virtual machines. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-24hwrng: core - Improve description of the ->read() interfaceDaniel Thompson1-1/+3
Currently, very few RNG drivers support single byte reads using the ->read() interface. Of the 14 drivers in drivers/char/hw_random that support this interface only three of these actually support max == 1. The other behaviours vary between return 0, return 2, return 4 and return -EIO). This is not a problem in practice because the core hw_random code never performs a read shorter than 16 bytes. The documentation for this function already contrains the alignment of the buffer pointer, so let's also guarantee that the buffer is at least as large as its alignment. This constraint is intended to be the weakest guarantee neccessary to allow driver writers to safely simplify their code. Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-24crypto: doc - fix documentation for bulk registration functionsEric Biggers1-12/+26
Update the documentation for crypto_register_algs() and crypto_unregister_algs() to match the actual behavior. Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-24crypto: vmx - fix null dereference in p8_aes_xts_cryptLi Zhong1-1/+1
walk.iv is not assigned a value in blkcipher_walk_init. It makes iv uninitialized. It is possibly a null value(as shown below), which is then used by aes_p8_encrypt. This patch moves iv = walk.iv after blkcipher_walk_virt, in which walk.iv is set. [17856.268050] Unable to handle kernel paging request for data at address 0x00000000 [17856.268212] Faulting instruction address: 0xd000000002ff04bc 7:mon> t [link register ] d000000002ff47b8 p8_aes_xts_crypt+0x168/0x2a0 [vmx_crypto] (938) [c000000013b77960] d000000002ff4794 p8_aes_xts_crypt+0x144/0x2a0 [vmx_crypto] (unreliable) [c000000013b77a70] c000000000544d64 skcipher_decrypt_blkcipher+0x64/0x80 [c000000013b77ac0] d000000003c0175c crypt_convert+0x53c/0x620 [dm_crypt] [c000000013b77ba0] d000000003c043fc kcryptd_crypt+0x3cc/0x440 [dm_crypt] [c000000013b77c50] c0000000000f3070 process_one_work+0x1e0/0x590 [c000000013b77ce0] c0000000000f34c8 worker_thread+0xa8/0x660 [c000000013b77d80] c0000000000fc0b0 kthread+0x110/0x130 [c000000013b77e30] c0000000000098f0 ret_from_kernel_thread+0x5c/0x6c Signed-off-by: Li Zhong <zhong@linux.vnet.ibm.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-24crypto: qat - fix aes-xts key sizesGiovanni Cabiddu1-2/+2
Increase value of supported key sizes for qat_aes_xts. aes-xts keys consists of keys of equal size concatenated. Fixes: def14bfaf30d ("crypto: qat - add support for ctr(aes) and xts(aes)") Cc: stable@vger.kernel.org Reported-by: Wenqian Yu <wenqian.yu@intel.com> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-08-24hwrng: mxc-rnga - Fix Kconfig dependencyFabian Frederick1-1/+1
We can directly depend on SOC_IMX31 since commit c9ee94965dce ("ARM: imx: deconstruct mxc_rnga initialization") Since that commit, CONFIG_HW_RANDOM_MXC_RNGA could not be switched on with unknown symbol ARCH_HAS_RNGA and mxc-rnga.o can't be generated with ARCH=arm make M=drivers/char/hw_random Previously, HW_RANDOM_MXC_RNGA required ARCH_HAS_RNGA which was based on IMX_HAVE_PLATFORM_MXC_RNGA && ARCH_MXC. IMX_HAVE_PLATFORM_MXC_RNGA was based on SOC_IMX31. Fixes: c9ee94965dce ("ARM: imx: deconstruct mxc_rnga initialization") Signed-off-by: Fabian Frederick <fabf@skynet.be> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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