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2014-09-17irqchip: omap-intc: enable TURBO idle modeFelipe Balbi1-0/+5
When TURBO bit is set in the INTC_IDLE register, the input synchronizer clock will be autogated based on activity on the INTC. Because this idle mode increases the interrupt latency by 2 clock cycles, we're only enabling it during suspend. Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-17irqchip: omap-intc: enable IP protectionFelipe Balbi1-2/+20
When PROTECTION bit in enabled in PROTECTION register, INTC's registers are only accessible from privileged mode. Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-17irqchip: omap-intc: remove unnecesary of_address_to_resource() callFelipe Balbi1-6/+0
of_iomap(), which is called from omap_init_irq_of(), already takes care of making sure we have a valid resource to deal with. Because of that, we can safely remove our explicit call to of_address_to_resource(). Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-17irqchip: omap-intc: comment style cleanupFelipe Balbi1-2/+4
no functional changes, just making sure comment follows Coding Style. Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-17irqchip: omap-intc: minor improvement to omap_irq_pending()Felipe Balbi1-4/+3
We already hold the number of Pending registers in omap_nr_pending. Let's use that instead. Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-17arm: omap: irq: move irq.c to drivers/irqchip/Felipe Balbi5-6/+13
Just move the code over as it has no dependencies on arch/arm/ anymore. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-17irqchip: add irq-omap-intc.h headerFelipe Balbi2-9/+33
OMAP INTC irqchip driver will be moved under drivers/irqchip/ soon but we still have a dependency with mach-omap2 when it comes to idle functions. In order to make it easy to share those function prototypes with OMAP PM code, we introduce this new header. To avoid modifying several board-files and some of the PM-related code, we just include the new header from common.h which was already included by all users of IRQ-related PM code. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-17arm: omap2: n8x0: move i2c devices to DTFelipe Balbi5-23/+23
By moving i2c devices to DT we can clean up i2c_board_info and fix a problem with moving INTC to irq domain where IRQs can be renumbered on each boot. Cc: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: intc: switch over to linear irq domainFelipe Balbi1-9/+79
now that we don't need to support legacy board-files, we can completely switch over to a linear irq domain and make use of irq_alloc_domain_generic_chips() to allocate all generic irq chips for us. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: get rid of ifdef hackFelipe Balbi1-15/+7
we don't need the ifdef if we have omap_nr_pending telling us how many pending registers we have on current platform. This solves a possible problem where we could try to handle bogus interrupts on OMAP2 and OMAP3 if using single zImage kernel, because we would end up reading the following pending FIQ register. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: introduce omap_nr_pendingFelipe Balbi1-1/+8
that variable will tell us how many INTC_PENDING_IRQn registers we have. It'll be used on a following patch to cleanup omap_intc_handle_irq() a bit. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: remove nr_irqs argumentFelipe Balbi1-12/+13
we can set our global omap_nr_irqs early on and drop the extra argument to omap_init_irq(). Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: remove unnecessary headerFelipe Balbi1-1/+0
There's no need for that header to be included. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: drop omap2_intc_handle_irq()Felipe Balbi2-11/+6
that was just a no-op wrapper around omap_intc_handle_irq anyway. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: drop omap3_intc_handle_irq()Felipe Balbi16-22/+0
now that we're calling set_handle_irq() from init_irq(), we can safely drop all callers to omap3_intc_handle_irq() and its definition. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: call set_handle_irq() from .init_irqFelipe Balbi1-0/+3
the idea is that board-files won't need to set .handle_irq on their machine_descs, which lets us drop a little more pointless code. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: move some more code aroundFelipe Balbi1-15/+15
We want .init_irq to call set_irq_handle() for legacy platforms. Note that this code will also be dropped once omap2/3 devices are completely moved to DT. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: boot: dts: omap2/3/am33xx: drop ti,intc-sizeFelipe Balbi3-3/+0
we are now infering number of IRQ lines based on correct compatible flag, which renders this binding completely useless. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: drop ti,intc-size supportFelipe Balbi1-3/+0
we don't need that anymore since specific devices are passing correct compatible flags. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: boot: dts: am33xx/omap3: fix intc compatible flagFelipe Balbi2-2/+2
that way, our intc driver can figure out how many IRQ lines INTC has. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: use compatible flag to figure out number of IRQ linesFelipe Balbi1-0/+3
so far, only am33xx has 128 lines, all other devices have only 96. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: add specific compatibles for omap3 and am33xx devicesFelipe Balbi1-1/+3
with this, we can use a compatible flag to figure out how many irq lines are wired up, no need for our TI-specific ti,intc-size binding. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: drop .handle_irq and .init_irq fieldsFelipe Balbi3-20/+0
now we can safely drop those fields from our machine_desc. While at that, also drop the now unused omap_intc_of_init() definition. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: use IRQCHIP_DECLARE macroFelipe Balbi1-5/+3
IRQCHIP_DECLARE macro is used to declare the same of_device_id structure for irqchips, it's just a helper. No functional changes. Note that we're temporarily including irqchip.h with its full path, until we move this driver to drivers/irqchip/. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: call set_handle_irq() from intc_of_initFelipe Balbi1-0/+2
this will let us drop .handle_irq and .init_irq fields from our generic machine_descs. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: make intc_of_init staticFelipe Balbi2-11/+1
nobody uses that function outside of this file, so we don't need to expose it. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: reorganize code a little bitFelipe Balbi1-67/+66
no functional changes, just moving code around. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: always define omap3 supportFelipe Balbi1-2/+0
remove ifdef around omap3 INTC support. This will make it easier to reuse code for PM. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: rename omap3_intc_regsFelipe Balbi1-2/+2
just to make it clearer that it can be used on all omaps. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: remove unnecessary base_addr argumentFelipe Balbi1-7/+3
omap_intc_handle_irq now had an unnecessary base_addr argument. Let's remove it and fix all callers. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: switch over to intc_readl on omap_intc_handle_irqFelipe Balbi1-6/+8
an almost blind conversion from readl_relaxed to our newly introduced intc_readl(). While at that, also remove some hardcoded register addresses. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: remove unused macroFelipe Balbi1-2/+0
no functional changes. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: remove rest of irq_banks usageFelipe Balbi1-81/+47
now we can finally remove the pointless irq_banks array. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: add a global omap_nr_irqs variableFelipe Balbi1-0/+3
this will cache number of irqs. Also in preparation for removal of irq_banks array. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: start to remove irq_banks arrayFelipe Balbi1-37/+27
We have a single bank in that array, this patch is in preparation to remove that array. It just shifts everything to a new set of functions for register IO while also removing old ones. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: define INTC_ILR0 registerFelipe Balbi1-0/+1
this is currently used as a hardcoded 0x100 offset. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12arm: omap: irq: make omap_irq_base globalFelipe Balbi1-1/+1
This is in preparation for removing the pointless irq_banks array. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-12Merge branch 'omap-for-v3.18/fixes-not-urgent' into omap-for-v3.18/intc-v2Tony Lindgren7-21/+21
2014-09-11ARM: OMAP2+: make of_device_ids constUwe Kleine-König7-9/+9
of_device_ids (i.e. compatible strings and the respective data) are not supposed to change at runtime. All functions working with of_device_ids provided by <linux/of.h> work with const of_device_ids. So mark the non-const function parameters and structs for OMAP2+ as const, too. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-11ARM: omap2: make arrays containing machine compatible strings constUwe Kleine-König1-12/+12
The definition static const char *omap3_boards_compat[] __initconst = { defines a changable array of constant strings. That is you must not do: *omap3_boards_compat[0] = 'f'; but omap3_boards_compat[0] = "another string"; is fine. So the annotation __initconst is wrong and yields a compiler error when other really const variables are added with __initconst. As the struct machine_desc member dt_compat is declared as const char *const *dt_compat; making the arrays const is the better alternative over changing all annotations to __initdata. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-09ARM: dts: OMAP3+: Add PRM interruptNishanth Menon4-0/+4
Provide OMAP3, 4 and OMAP5 with interrupt number for PRM And for DRA7, provide crossbar number for prm interrupt. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-09ARM: omap: Remove stray ARCH_HAS_OPP referencesMark Brown1-5/+0
OPP is now a normal kernel library selected by its users rather than a feature that architectures need to enable so ARCH_HAS_OPP serves no function any more - remove the selects. Signed-off-by: Mark Brown <broonie@kernel.org> Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-09ARM: DRA7: Add hook in SoC initcalls to enable pm initializationRajendra Nayak2-1/+4
With consolidated code, now we can add the required hooks for DRA7 to enable power management. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [nm@ti.com: minor modifications] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-09Merge branch 'pull/v3.18/for-omap-soc' of ↵Tony Lindgren13-64/+275
https://github.com/nmenon/linux-2.6-playground into omap-for-v3.18/soc
2014-09-09Merge branch 'pull/v3.18/powerdomain-fixes' of ↵Tony Lindgren6-16/+106
https://github.com/nmenon/linux-2.6-playground into omap-for-v3.18/fixes-not-urgent
2014-09-08ARM: OMAP5: Add hook in SoC initcalls to enable pm initializationSantosh Shilimkar2-1/+4
With consolidated code, now we can add the required hooks for OMAP5 to enable power management. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [nm@ti.com: minor rebase updates] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
2014-09-08ARM: OMAP5 / DRA7: Enable CPU RET on suspendRajendra Nayak4-3/+17
On OMAP5 / DRA7, prevent a CPU powerdomain OFF and resulting MPU OSWR and instead attempt a CPU RET and side effect, MPU RET in suspend. NOTE: the hardware was originally designed to be capable of achieving deep power states such as OFF and OSWR, however due to various issues and risks, deepest valid state was determined to be CSWR - hence we use the errata framework to handle this case. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [nm@ti.com: updates] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
2014-09-08ARM: OMAP5 / DRA7: PM: Provide a dummy startup function for CPU hotplugSantosh Shilimkar1-6/+8
Dont assume that all OMAP4+ code will be able to use OMAP4 hotplug logic. On OMAP5, DRA7, we do not need this in place yet, also, currently the CPU startup pointer is located in omap4_cpu_pm_info instead of cpu_pm_ops. So, isolate the function to hotplug_restart pointer in cpu_pm_ops where it should have belonged, initalize them as per valid startup pointers for OMAP4430/60 as in current logic, however provide dummy_cpu_resume to be the startup location as well. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [nm@ti.com: split this out of original code and isolate it] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
2014-09-08ARM: OMAP5 / DRA7: PM: Avoid all SAR savesRajendra Nayak1-21/+34
Get rid of all assumptions about always having a sar base on *all* OMAP4+ platforms. We dont need one on DRA7 and it is not necessary at this point for OMAP5 either. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [nm@ti.com: Split and optimize] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
2014-09-08ARM: OMAP5 / DRA7: PM: Enable Mercury retention mode on CPUx powerdomainsSantosh Shilimkar1-0/+16
In addition to the standard power-management technique, the OMAP5 / DRA7 MPU subsystem also employs an SR3-APG (mercury) power management technology to reduce leakage. It allows for full logic and memories retention on MPU_C0 and MPU_C1 and is controlled by the PRCM_MPU. Only "Fast-mode" is supported on the OMAP5 and DRA7 family of processors. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [nm@ti.com: minor consolidation] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
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