summaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2022-04-23dt-bindings: pinctrl: add binding for Ralink MT7621 pinctrlArınç ÜNAL1-0/+71
Add binding for the Ralink MT7621 pin controller for MT7621 SoC. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20220414173916.5552-13-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-23dt-bindings: pinctrl: add binding for Ralink MT7620 pinctrlArınç ÜNAL1-0/+91
Add binding for the Ralink MT7620 pin controller for MT7620, MT7628 and MT7688 SoCs. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20220414173916.5552-12-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-23dt-bindings: pinctrl: rt2880: fix binding name, pin groups and functionsArınç ÜNAL1-13/+13
Deprecate the old property "ralink,rt2880-pinmux". Add the new property "ralink,rt2880-pinctrl". The old property name was inaccurate as the hardware block is called pinctrl across the Mediatek/Ralink architecture. Current pin group and function bindings are for MT7621. Put bindings for RT2880 instead. Add me as a maintainer. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20220414173916.5552-11-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-23mips: dts: ralink: mt7621: use the new compatible string for MT7621 pinctrlArınç ÜNAL1-1/+1
Use the new compatible string "ralink,mt7621-pinctrl" for the Ralink MT7621 pinctrl subdriver on mt7621.dtsi. Each subdriver needs to have a different compatible string. We don't want the same compatible string to match a different subdriver's pinmux data as it's not for our SoC. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20220414173916.5552-10-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-23MAINTAINERS: add Ralink pinctrl driverArınç ÜNAL1-0/+7
Add a new section for the Ralink pinctrl driver and add me and Sergio as the maintainers. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20220414173916.5552-9-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-23pinctrl: ralink: add new compatible strings for each pinctrl subdriverArınç ÜNAL5-10/+10
As seen on any other pinctrl subdriver that calls code from a main driver, each subdriver needs to have a different compatible string. We don't want the same compatible string to match a different subdriver's pinmux data as it's not for our SoC. Therefore, add new compatible strings for each pinctrl subdriver. Change driver name on all subdrivers accordingly. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20220414173916.5552-8-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-23pinctrl: ralink: rename driver names to subdriversArınç ÜNAL1-5/+5
MT7620, MT7621, RT2880, RT305X and RT3883 pinctrl are subdrivers of the Ralink pinctrl driver. Change the bool for these subdrivers accordingly. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20220414173916.5552-7-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-23pinctrl: ralink: rename variable names for functions on MT7620 and MT7621Arınç ÜNAL2-106/+106
Variables for functions include "grp" on the Ralink MT7620 and MT7621 subdrivers. Rename them to "func" instead as they define the functions for the pin groups. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20220414173916.5552-6-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-23pinctrl: ralink: rename pinctrl-rt288x to pinctrl-rt2880Arınç ÜNAL3-12/+12
Rename "pinctrl-rt288x.c" to "pinctrl-rt2880.c" as this is the Ralink RT2880 pinctrl subdriver. Rename PINCTRL_RT288X symbol to PINCTRL_RT2880. Rename functions that include "rt288x" to "rt2880". Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20220414173916.5552-5-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-23pinctrl: ralink: rename pinmux functions to pinctrlArınç ÜNAL7-62/+62
Rename pinctrl related functions from "pinmux" to "pinctrl". Change driver name from "ralink-pinmux" to "ralink-pinctrl". Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20220414173916.5552-4-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-23pinctrl: ralink: rename pinctrl-rt2880 to pinctrl-ralinkArınç ÜNAL9-171/+167
pinctrl-rt2880.c and pinmux.h make up the Ralink pinctrl driver. Rename pinctrl-rt2880.c to pinctrl-ralink.c. Rename pinmux.h to pinctrl-ralink.h. Fix references to it. Rename functions that include "rt2880" to "ralink". Remove PINCTRL_RT2880 symbol and make the existing PINCTRL_RALINK symbol compile pinctrl-ralink.c. Change the bool to "Ralink pinctrl driver". Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20220414173916.5552-3-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-23pinctrl: ralink: rename MT7628(an) functions to MT76X8Arınç ÜNAL1-109/+109
The functions that include "MT7628(an)" are for MT7628 and MT7688 SoCs. Rename them to MT76X8 to refer to both of the SoCs. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20220414173916.5552-2-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-23Merge tag 'renesas-pinctrl-for-v5.19-tag1' of ↵Linus Walleij18-153/+362
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.19 - Add support for the new RZ/G2UL SoC, - Add drive-strength support for R-Car E3, - Add RPC/QSPI pin groups on R-Car E3 and E3, - Miscellaneous fixes and improvements.
2022-04-23pinctrl: qcom: Update clock voting as optionalSrinivasa Rao Mandadapu3-2/+8
Update bulk clock voting to optional voting as ADSP bypass platform doesn't need macro and decodec clocks, as these macro and dcodec GDSC switches are maintained as power domains and operated from lpass clock drivers. Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1650285427-19752-8-git-send-email-quic_srivasam@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-23pinctrl: qcom: Add SC7280 lpass pin configurationSrinivasa Rao Mandadapu3-0/+176
Add pin control support for SC7280 LPASS LPI. Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/1650285427-19752-7-git-send-email-quic_srivasam@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-23pinctrl: qcom: Extract chip specific LPASS LPI codeSrinivasa Rao Mandadapu5-228/+263
Extract the chip specific SM8250 data from the LPASS LPI pinctrl driver to allow reusing the common code in the addition of subsequent platforms. Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/1650285427-19752-6-git-send-email-quic_srivasam@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-23pinctrl: qcom: Update lpi pin group custiom functions with framework generic ↵Srinivasa Rao Mandadapu2-51/+52
functions Update custom pin group structure members with framework generic group_desc structure and replace the driver's custom pinctrl_ops with framework provided generic pin control group functions to avoid redundant code written in lpass lpi driver. Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/1650285427-19752-5-git-send-email-quic_srivasam@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-23pinctrl: qcom: Update macro name to LPI specificSrinivasa Rao Mandadapu1-8/+8
Update NO_SLEW macro to LPI_NO_SLEW macro as this driver lpi specific. Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1650285427-19752-4-git-send-email-quic_srivasam@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-23dt-bindings: pinctrl: qcom: Add sc7280 lpass lpi pinctrl bindingsSrinivasa Rao Mandadapu1-0/+115
Add device tree binding Documentation details for Qualcomm SC7280 LPASS LPI pinctrl driver. Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1650285427-19752-3-git-send-email-quic_srivasam@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-23dt-bindings: pinctrl: qcom: Update lpass lpi file name to SoC specificSrinivasa Rao Mandadapu1-1/+1
Change generic lpass lpi pincotrol bindings file to SoC specific file, to distinguish and accomadate other SoC specific dt bindings. Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1650285427-19752-2-git-send-email-quic_srivasam@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-23dt-bindings: pinctrl: rockchip: add rk3588Sebastian Reichel1-0/+1
Add compatible string for rk3588 pin controller. No other changes are required, since the new controller can use the old binding. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20220422170920.401914-12-sebastian.reichel@collabora.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-23pinctrl: nomadik: Add new MC2 configLinus Walleij1-1/+6
The MC2 MMC interface can be configured with the FBCLK (feedback clock) unconnected, leaving the pin available for reuse for something else. Add a group mc2_a_2 for this. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220418164317.864418-1-linus.walleij@linaro.org
2022-04-23pinctrl: thunderbay: Use devm_platform_ioremap_resource()Lv Ruyi1-6/+1
Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately.Make the code simpler without functional changes. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Lv Ruyi <lv.ruyi@zte.com.cn> Link: https://lore.kernel.org/r/20220418020238.2556989-1-lv.ruyi@zte.com.cn Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-22pinctrl: ingenic: Garbage-collect code paths for SoCs disabled by configPaul Cercueil1-47/+71
By being a bit smarter about how the SoC version checks are performed, it is possible to have all the code paths that correspond to SoCs disabled in the kernel config automatically marked as dead code by the compiler, and therefore garbage-collected. With this patch, when compiling a kernel that only targets the JZ4760 for instance, the driver is now about 4.5 KiB smaller. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20220412162218.32509-1-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-22dt-bindings: pinctrl: add rockchip,rk3036-pinctrl compatible stringJohan Jonker1-0/+1
Add the compatible string "rockchip,rk3036-pinctrl" in already in use in rk3036.dtsi to rockchip,pinctrl.yaml. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220330133952.1949-1-jbx6244@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-22dt-bindings: pinctrl: Convert i.MX7D to json-schemaAlexander Stein2-87/+113
Convert the i.MX7D pinctrl binding to DT schema format using json-schema Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20220303150653.1903910-1-alexander.stein@ew.tq-group.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-22pinctrl: max77620: drop unneeded MODULE_ALIASKrzysztof Kozlowski1-1/+0
The MODULE_DEVICE_TABLE already creates proper alias for platform driver. Having another MODULE_ALIAS causes the alias to be duplicated. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220407202509.23228-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-22pinctrl: meson: fix unused variable warningQianggui Song1-1/+2
The kernel test robot reported a warning as below: >> drivers/pinctrl/meson/pinctrl-meson-s4.c:178:27: warning: unused variable 'tdm_sclk1_c_pins' [-Wunused-const-variable] static const unsigned int tdm_sclk1_c_pins[] = { GPIOC_3 }; Fix it by adding missing description about this pins Fixes: 775214d389c2 ("pinctrl: meson: add pinctrl driver support for Meson-S4 Soc") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Qianggui Song <qianggui.song@amlogic.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220330023720.18238-1-qianggui.song@amlogic.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-22pinctrl: mediatek: mt8195: enable driver on mtk platformsFabien Parent1-0/+1
Set the pinctrl driver as built-in by default if ARM64 and ARCH_MEDIATEK are enabled. Fixes: 6cf5e9ef362a ("pinctrl: add pinctrl driver on mt8195") Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220327160813.2978637-1-fparent@baylibre.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-22gpio/rockchip: handle deferring input-enable pinconfsCaleb Connolly1-0/+5
Add support for deferred PIN_CONFIG_INPUT_ENABLE handling. Signed-off-by: Caleb Connolly <kc@postmarketos.org> Acked-by: Bartosz Golaszewski <brgl@bgdev.pl> Link: https://lore.kernel.org/r/20220328005005.72492-4-kc@postmarketos.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-22pinctrl/rockchip: support setting input-enable paramCaleb Connolly1-1/+11
Handle the PIN_CONFIG_INPUT_ENABLE param for configuring GPIOs as input. Signed-off-by: Caleb Connolly <kc@postmarketos.org> Link: https://lore.kernel.org/r/20220328005005.72492-3-kc@postmarketos.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-22pinctrl/rockchip: support deferring other gpio paramsCaleb Connolly3-35/+50
Add support for deferring other params like PIN_CONFIG_INPUT_ENABLE. This will be used to add support for PIN_CONFIG_INPUT_ENABLE to the driver. Fixes: e7165b1dff06 ("pinctrl/rockchip: add a queue for deferred pin output settings on probe") Fixes: 59dd178e1d7c ("gpio/rockchip: fetch deferred output settings on probe") Signed-off-by: Caleb Connolly <kc@postmarketos.org> Link: https://lore.kernel.org/r/20220328005005.72492-2-kc@postmarketos.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-21pinctrl: ocelot: add clock monitor option for LAN966xMichael Walle1-2/+4
The SoC supports a debug clock output of its internal clocks. Depending on the clk_sel input (GPIO_31) clk_mon (GPIO_30) will output either cpu_clk/64 or sys_clk/64. This is very useful for debugging and is missing in the pinmux table. Add it. Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220326192848.2944519-2-michael@walle.cc Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-21pinctrl: ocelot: add pwm output option for LAN966xMichael Walle1-2/+6
According to the reference manual, you can mux the PWM output on GPIO27 and GPIO51. This was missing in the pinmux table. Add it. Tested on a LAN9668 on GPIO51. Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220326192848.2944519-1-michael@walle.cc Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-21dt-bindings: pinctrl: convert ocelot-pinctrl to YAML formatMichael Walle2-42/+108
Convert the ocelot-pinctrl device tree binding to the new YAML format. Additionally to the original binding documentation, add interrupt properties which are optional and already used on several SoCs like SparX-5, Luton, Ocelot and LAN966x but were not documented before. Also, on the sparx5 and the lan966x SoCs there are two items for the reg property. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20220319204628.1759635-7-michael@walle.cc Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-21pinctrl: qcom-pmic-gpio: Add support for pmx65Rohit Agarwal1-0/+1
PMX65 pmic support gpio controller so add compatible. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Link: https://lore.kernel.org/r/1649048650-14059-3-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-21dt-bindings: pinctrl: qcom-pmic-gpio: Add pmx65 supportRohit Agarwal1-0/+2
Add support for the PMX65 GPIO support to the Qualcomm PMIC GPIO binding. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/1649048650-14059-2-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-21pinctrl: bcm2835: implement hook for missing gpio-rangesStefan Wahren1-0/+18
The commit c8013355ead6 ("ARM: dts: gpio-ranges property is now required") fixed the GPIO probing issues caused by "pinctrl: bcm2835: Change init order for gpio hogs". This changed only the kernel DTS files. Unfortunately it isn't guaranteed that these files are shipped to all users. So implement the necessary backward compatibility for BCM2835 and BCM2711 platform. Fixes: 266423e60ea1 ("pinctrl: bcm2835: Change init order for gpio hogs") Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20220409095129.45786-3-stefan.wahren@i2se.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-21gpiolib: of: Introduce hook for missing gpio-rangesStefan Wahren2-0/+17
Since commit 2ab73c6d8323 ("gpio: Support GPIO controllers without pin-ranges") the device tree nodes of GPIO controller need the gpio-ranges property to handle gpio-hogs. Unfortunately it's impossible to guarantee that every new kernel is shipped with an updated device tree binary. In order to provide backward compatibility with those older DTB, we need a callback within of_gpiochip_add_pin_range() so the relevant platform driver can handle this case. Fixes: 2ab73c6d8323 ("gpio: Support GPIO controllers without pin-ranges") Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Bartosz Golaszewski <brgl@bgdev.pl> Link: https://lore.kernel.org/r/20220409095129.45786-2-stefan.wahren@i2se.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-20pinctrl: renesas: rzg2l: Restore pin config orderGeert Uytterhoeven1-1/+1
The PIN_CFG_* capabilities are always listed in the order they are defined, except in the "TMS/SWDIO" pin definition. Fix the order, to increase uniformity. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/f9b18be9e5402531d058bd2479b4881377f9b8b6.1649857772.git.geert+renesas@glider.be
2022-04-20pinctrl: renesas: Remove unneeded #include <linux/init.h>Geert Uytterhoeven11-11/+0
The last __init annotations were removed from these source files almost one decade ago. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/fb71c409ea3ad76163496e305dc955ca8e84416d.1649681741.git.geert+renesas@glider.be
2022-04-20pinctrl: renesas: Select PINCTRL_RZG2L if ARCH_RZG2L is enabledLad Prabhakar1-3/+1
GPIO (PINCTRL) block is identical on Renesas RZ/G2L, RZ/G2UL and RZ/V2L SoC's, so instead of selecting PINCTRL_RZG2L config for each SoC select PINCTRL_RZG2L config option if ARCH_RZG2L is enabled. The ARCH_RZG2L config option is already selected by ARCH_R9A07G043, ARCH_R9A07G044 and ARCH_R9A07G054. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220406075318.14385-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-20pinctrl: renesas: rzg2l: Add RZ/G2UL supportBiju Das2-81/+124
RZ/G2UL SoC has fewer pins compared to RZ/G2L and the port pin definitions are different compared to RZ/G2L. This patch adds a new compatible to take care of these differences by adding r9a07g043_data with r9a07g043_gpio_configs and rzg2l_dedicated_pins.common. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220401180230.19950-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-20pinctrl: renesas: r8a77995: Add QSPI and RPC pins, groups, and functionsGeert Uytterhoeven1-0/+98
Add pins, groups, and functions for the SPI Multi I/O Bus Controller (RPC-IF) to the R8A77995 PFC driver. They are to be used when a QSPI Flash, Octal-SPI Flash, or HyperFlash is connected. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/19a3bccd0ec830846578a38b4c80dccb195109a0.1648547080.git.geert+renesas@glider.be
2022-04-20pinctrl: renesas: r8a77990: Add RPC pins, groups, and functionsGeert Uytterhoeven1-20/+61
Add pins, groups, and functions for the SPI Multi I/O Bus Controller (RPC-IF) to the R8A77990 PFC driver. They are to be used when an Octal-SPI Flash or HyperFlash is connected. Redefine the QSPI[01] pin groups using the RPC DQ[0:7] pin data, to save memory. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/ec9735bb3468225e04ac6cb95e11a0e237b2b9ed.1648547080.git.geert+renesas@glider.be
2022-04-20pinctrl: renesas: r8a77990: Add drive-strengthWolfram Sang1-2/+37
According to R-Car Gen3 HW documentation 2.20 onwards, drive-strength is introduced to r8a77990. It is also documented for r8a774c0. Add it to the pinctrl driver. Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220320092542.2308-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-20pinctrl: renesas: Allow up to 10 fields for drive_regsWolfram Sang1-1/+1
Needed to support R-Car E3 and RZ/G2E drive regs. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220320092542.2308-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-20pinctrl: renesas: checker: Rework drive and bias pin iterationGeert Uytterhoeven1-31/+36
The checker code to iterate over all drive strength and bias register description items is cumbersome, due to the repeated calculation of indices, and the use of hardcoded array sizes. The latter was done under the assumption they would never need to be changed, which turned out to be false. Increase readability by introducing helper macros to access drive strength and bias register description items. Increase maintainability by replacing hardcoded numbers by array sizes calculated at compile-time. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/5051ae56a1388ccf2d283dfc9624de2991cce914.1650355619.git.geert+renesas@glider.be
2022-04-20dt-bindings: pinctrl: mt8192: Add gpio-line-names propertyNícolas F. R. A. Prado1-0/+2
Add the gpio-line-names optional property to the pinctrl-mt8192 binding to prevent dt_binding_check warnings when it is present in the pinctrl node in the Devicetree. Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220315211936.442708-5-nfraprado@collabora.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-20dt-bindings: pinctrl: mt8192: Add mediatek,pull-up-adv propertyNícolas F. R. A. Prado1-0/+11
Add the mediatek,pull-up-adv property to the pinctrl-mt8192 dt-binding to allow configuring pull-up resistors on the pins of MT8192. It is the same as in mt8183-pinctrl. Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220315211936.442708-4-nfraprado@collabora.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-26 19:25:01 +0300