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2016-06-23clk: meson: fractional pll supportMichael Turquette2-2/+45
Fractional MPLLs are a superset of the existing AmLogic MPLLs. They add in a couple of new bitfields for further dividing the clock rate to achieve rates with fractional hertz. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-23clk: meson: add mpll supportMichael Turquette3-1/+105
MPLLs are adjustable rate clocks derived from PLLs. On both Meson8b and GXBB they appear to be only derived from fixed_pll. Add support for these clock types so that they can be added to their respective drivers. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-23clk: meson: add peripheral gate macroMichael Turquette1-0/+14
There are a series of peripheral and system gate clocks that fan out from the clk81 signal. Add a helper macro to statically initialize these gate clocks. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-23clk: meson: only build selected platformsMichael Turquette4-3/+16
Break the AmLogic clock code up so that only the necessary parts are compiled and linked. The core code is selected by both arm and arm64 builds with COMMON_CLK_AMLOGIC. The individual drivers have their own config options as well. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-23clk: meson8b: convert to platform_driverMichael Turquette1-18/+49
This patch creates a proper platform_driver for the meson8b clock controller. Use of CLK_OF_DECLARE is removed, and can be added back in later if very early registration of some clocks is required. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-23clk: meson8b: clean up composite clocksMichael Turquette5-247/+69
Remove the composite clock registration function and helpers. Replace unnecessary configuration struct with static initialization of the desired clock type. To preserve git bisect this patch also flips the switch and starts using of_clk_add_hw_provider instead of the deprecated meson_clk_register_clks method. As a byproduct clk.c can be deleted. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-23clk: meson8b: remove mali clkMichael Turquette1-22/+0
This clock is undocumented and always orphaned. Get rid of it until we have more complete clock tree documentation. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-23clk: meson8b: clean up cpu clocksMichael Turquette4-90/+59
Remove the cpu clock registration function and helpers. Replace unnecessary configuration struct with static initialization of the desired clock type. Ninja rename a5_clk to cpu_clk to better align with cpufreq convention. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-23clk: meson8b: clean up fixed factor clocksMichael Turquette3-71/+60
Remove the fixed factor registration function and helpers. Replace unnecessary configuration struct with static initialization of the desired clock type. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-23clk: meson8b: clean up pll clocksMichael Turquette4-114/+131
Remove the pll registration function and helpers. Replace unnecessary configuration struct with static initialization of the desired clock type. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-23clk: meson8b: clean up fixed rate clocksMichael Turquette3-75/+54
Remove the fixed_rate registration function and helpers from clkc.[ch]. Replace unnecessary configuration struct with static initialization of the desired clock type. While we're here, begin the transition to a proper platform_driver and call of_clk_add_hw_provider with a shiny new struct clk_hw_onecell_data. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-23clk: meson8b: rectify reg offsets with datasheetMichael Turquette1-3/+12
The register offsets in the data sheet are confusing. Document them more thoroughly. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-22clk: tegra: Mark timer clock as criticalThierry Reding1-1/+1
The timer clock feeds the timer block, which, among other things, is used to drive the SOR lane sequencer. Since the Tegra timer driver is not enabled on 64-bit ARM, nothing currently claims that clock and it gets disabled by the common clock framework at late_init time. Given the non-obvious dependencies, the timer clock can be considered a critical part of the SoC infrastructure, requiring its clock source to be always on. Acked-by: Rhyland Klein <rklein@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-22clk: rockchip: fix incorrect rk3228 clock registersXing Zheng1-9/+9
Due to copy and paste carelessly, RK3288_CLKxxx references are incorrect, we need to fix them. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-06-22clk: rockchip: add clock-ids for rk3228 MAC clocksXing Zheng1-0/+11
This patch exports related MAC clocks for dts reference. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-06-22clk: rockchip: add clock-ids for rk3228 audio clocksXing Zheng1-0/+4
This patch exports related i2s/spdif clocks for dts reference. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-06-21clk: renesas: r8a7795: Add THS/TSC clockKhiem Nguyen1-0/+1
Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@rvc.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-06-21clk: renesas: r8a7795: Add DRIF clockRamesh Shanmugasundaram1-0/+8
This patch adds DRIF module clocks for r8a7795 SoC. Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-06-21clk: renesas: r8a7795: Correct lvds clock parentGeert Uytterhoeven1-1/+1
According to the latest information, the parent clock of the LVDS module clock is the S0D4 clock, not the S2D1 clock. Note that this change has no influence on actual operation, as the rcar-du LVDS encoder driver doesn't use the parent clock's rate. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2016-06-21clk: renesas: r8a7795: Provide FDP1 clocksKieran Bingham1-0/+3
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Kieran Bingham <kieran@bingham.xyz> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-06-21clk: renesas: Add R8A7792 supportSergei Shtylyov2-0/+2
Renesas R-Car V2H (R8A7792) clocks are handled by R-Car gen2 clock driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-06-21clk: renesas: mstp: Document R8A7792 supportSergei Shtylyov1-0/+1
Renesas R8A7792 SoC also has the CPG MSTP clocks... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-06-21clk: renesas: rcar-gen2: Document R8A7792 supportSergei Shtylyov1-0/+1
Renesas R8A7792 SoC is a member of the R-Car gen2 family and so has CPG... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-06-21Merge tag 'clk-samsung-4.8' of git://linuxtv.org/snawrocki/samsung into clk-nextStephen Boyd24-514/+812
Merge changes from Sylwester Nawrocki for samsung clk drivers: - a fix for exynos7 to prevent gating some critical CMU clocks, - addition of CPU clocks for CPU frequency scaling on Exynos5433 SoCs, - additions for exynos5410 SoC required for Odroid XU board support, - register accessors fixes for kernels built for big endian operation (mostly exynos4 SoCs), - Exynos5433 clock definitions fixes required for suspend to RAM and the audio subsystem operation, - many cleanups changing attributes of the clock initializer data * tag 'clk-samsung-4.8' of git://linuxtv.org/snawrocki/samsung: (41 commits) clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag to PCIE device clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flags to avoid hang during S2R clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag for AUD UART clk: samsung: exynos4: fixup reg access on be clk: samsung: fixup endian in pll clk clk: samsung: exynos5410: Add WDT, ACLK266 and SSS clocks clk: samsung: exynos5433: add CPU clocks configuration data and instantiate CPU clocks clk: samsung: cpu: prepare for adding Exynos5433 CPU clocks clk: samsung: exynos5433: prepare for adding CPU clocks clk: samsung: Suppress unbinding to prevent theoretical attacks clk: samsung: exynos5420: Set ID for aclk333 gate clock clk: samsung: exynos5410: Add TMU clock clk: samsung: exynos5410: Add I2C, HSI2C and RTC clocks clk: samsung: exynos5410: Add serial3, USB and PWM clocks clk: samsung: exynos3250: Move PLL rates data to init section clk: samsung: Fully constify mux parent names clk: samsung: exynos5250: Move sleep init function to init section clk: samsung: exynos5420: Move sleep init function and PLL data to init section clk: samsung: exynos5433: Move PLL rates data to init section clk: samsung: exynos5433: Constify all clock initializers ...
2016-06-21clk: correct comments for __clk_determine_ratePeng Fan1-3/+1
Correct comments for __clk_determine_rate. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-21clk: vt8500: rework wm8650_find_pll_bits()Roman Volkov1-35/+38
PLL clock on WM8650 is calculated in the following way: M * parent [O1] => / P [O2] => / D [O3] Where O2 is 600MHz >= (M * parent) / P >= 300MHz. Current algorithm does not met this requirement, so that the function may return rates which are not supported by the hardware. This patch fixes the algorithm and simplifies the code, reducing the calculation time by ~10000 times (according to usermode app) by removing the nested loops. Signed-off-by: Roman Volkov <rvolkov@v1ros.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-21clk: vt8500: fix gcc-4.9 warningsArnd Bergmann1-24/+10
This fixes some false positive warnings we get with older compiler versions: clk-vt8500.c: In function ‘wm8650_find_pll_bits’: clk-vt8500.c:430:12: ‘best_div2’ may be used uninitialized in this function clk-vt8500.c:429:12: ‘best_div1’ may be used uninitialized in this function clk-vt8500.c:428:14: ‘best_mul’ may be used uninitialized in this function clk-vt8500.c: In function ‘wm8750_find_pll_bits’: clk-vt8500.c:509:12: ‘best_div2’ may be used uninitialized in this function clk-vt8500.c:508:12: ‘best_div1’ may be used uninitialized in this function clk-vt8500.c:507:14: ‘best_mul’ may be used uninitialized in this function clk-vt8500.c: In function ‘wm8850_find_pll_bits’: clk-vt8500.c:560:12: ‘best_div2’ may be used uninitialized in this function clk-vt8500.c:559:12: ‘best_div1’ may be used uninitialized in this function clk-vt8500.c:558:14: ‘best_mul’ may be used uninitialized in this function As the local variables are only use for temporaries, we can just as well assign the final values directly, which also makes the code slightly shorter. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Roman Volkov <rvolkov@v1ros.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-21clk: Remove unused variableLee Jones1-2/+1
Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-21clk: hi6220: fix missing clk.h includeBen Dooks1-0/+2
Fix the warning from missing "clk.h" include which defines hi6220_register_clkdiv() function. drivers/clk/hisilicon/clkdivider-hi6220.c:102:12: warning: symbol 'hi6220_register_clkdiv' was not declared. Should it be static? Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-21clk: iproc: fix missing include of clk-iproc.hBen Dooks1-0/+2
Fix the implicit declaration of iproc_armpll_setup() by including clk-iproc.h which defines it. Fixes the warning: drivers/clk/bcm/clk-iproc-armpll.c:242:13: warning: symbol 'iproc_armpll_setup' was not declared. Should it be static? Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Acked-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-21clk: at91: make of_sama5d2_clk_generated_setup() staticBen Dooks1-1/+1
The of_sama5d2_clk_generated_setup() is not exported outside of the driver, so make it static to fix the warning about it being not static: drivers/clk/at91/clk-generated.c:270:13: warning: symbol 'of_sama5d2_clk_generated_setup' was not declared. Should it be static? Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-21Merge branch 'clk-fixes' into clk-nextStephen Boyd4-17/+11
* clk-fixes: clk: Fix return value check in oxnas_stdclk_probe() clk: rockchip: release io resource when failing to init clk on rk3399 clk: rockchip: fix cpuclk registration error handling clk: rockchip: Revert "clk: rockchip: reset init state before mmc card initialization" clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src clk: rockchip: mark rk3399 GIC clocks as critical clk: rockchip: initialize flags of clk_init_data in mmc-phase clock
2016-06-21Merge tag 'v4.7-rockchip-clk-fixes1' of ↵Stephen Boyd3-15/+9
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes A bunch of fixes. Some for the newly added rk3399 clock tree, some concerning error handling and initialization and a revert of the mmc-phase clock initialization, as this could conflict with the bootloader setting of this clock and a real solution to initing the phase correctly from dw_mmc went in as fix for 4.7 through the mmc tree. * tag 'v4.7-rockchip-clk-fixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: release io resource when failing to init clk on rk3399 clk: rockchip: fix cpuclk registration error handling clk: rockchip: Revert "clk: rockchip: reset init state before mmc card initialization" clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src clk: rockchip: mark rk3399 GIC clocks as critical clk: rockchip: initialize flags of clk_init_data in mmc-phase clock
2016-06-21clk: Fix return value check in oxnas_stdclk_probe()Wei Yongjun1-2/+2
In case of error, the function syscon_node_to_regmap() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Fixes: 0bbd72b4c64f ("clk: Add Oxford Semiconductor OXNAS Standard Clocks") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-20clk: multiplier: Prevent the multiplier from under / over flowingMaxime Ripard1-3/+17
In the current multiplier base clock implementation, if the CLK_SET_RATE_PARENT flag isn't set, the code will not make sure that the multiplier computed remains within the boundaries of our clock. This means that if the clock we want to reach is below the parent rate, or if the multiplier is above the maximum that we can reach, we will end up with a completely bogus one that the clock cannot achieve. Fixes: f2e0a53271a4 ("clk: Add a basic multiplier clock") Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1463402840-17062-3-git-send-email-maxime.ripard@free-electrons.com
2016-06-17clk: tegra: Enable sor1 and sor1_src on Tegra210Thierry Reding2-1/+3
Make the sor1 and sor1_src clocks available on Tegra210. They will be used by the display driver to support HDMI and DP. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-17clk: tegra: Squash sor1 safe/brick/src into a single muxThierry Reding2-12/+12
The sor1 clock on Tegra210 is structured in the following way: +-------+ | pllp |---+ +-------+ | +--------------+ +-----------+ +----| | | sor_safe | +-------+ | | +-----------+ | plld |--------| | | +-------+ | | +-----------+ | sor1_src |-------| | +-------+ | | +-----------+ | plld2 |--------| | | +-------+ | | | +----| | | +-------+ | +--------------+ | | clkm |---+ +-----------+ +-------+ +--------------+ | | | sor1_brick |-------| sor1 | +--------------+ | | +-----------+ This is impractical to represent in a clock tree, though, because there is no name for the mux that has sor_safe and sor1_src as parents. It is also much more cumbersome to deal with the additional mux because users of these clocks (the display driver) would have to juggle with an extra mux for no real reason. To simply things, the above is squashed into two muxes instead, so that it looks like this: +-------+ | pllp |---+ +-------+ | +--------------+ +-----------+ +----| | | sor_safe | +-------+ | | +-----------+ | plld |--------| | | +-------+ | | +-----------+ | sor1_src |-------| sor1 | +-------+ | | +-----------+ | plld2 |--------| | | | +-------+ | | | | +----| | | | +-------+ | +--------------+ | | | clkm |---+ | | +-------+ +--------------+ | | | sor1_brick |-----------+---+ +--------------+ This still very accurately represents the hardware. Note that sor1 has sor1_brick as input twice, that's because bit 1 in the mux selects the sor1_brick irrespective of bit 0. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-17clk: tegra: Disable spread spectrum on pll_d2Thierry Reding1-2/+3
Enabling spread spectrum on pll_d2 can lead to issues with display modes. HDMI monitors, for example, would report "Signal Error" and some modes driven over DisplayPort would generate fuzzy horizontal bands. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-17Merge commit 'f17a0dd1c2e0' into clk-nextMichael Turquette1-4/+4
2016-06-16clk: imx6ul: fix gpt2 clock namesDong Aisheng1-2/+2
fix gpt2 clock names Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-16clk: imx: refine the powerdown bit of clk-pllv3Dong Aisheng1-10/+10
The powerdown bit is a bit confused, let's change it to power_bit to relfect both powerdown and powerup case according to different plls. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-15clk: Use _rcuidle suffix to allow clk_core_enable() to used from idlePaul E. McKenney1-2/+2
This commit fixes the RCU use-from-idle bug corresponding the following splat: > [ INFO: suspicious RCU usage. ] > 4.6.0-rc5-next-20160426+ #1127 Not tainted > ------------------------------- > include/trace/events/clk.h:45 suspicious rcu_dereference_check() usage! > > other info that might help us debug this: > > > RCU used illegally from idle CPU! > rcu_scheduler_active = 1, debug_locks = 0 > RCU used illegally from extended quiescent state! > 2 locks held by swapper/0/0: > #0: (&oh->hwmod_key#30){......}, at: [<c0121afc>] omap_hwmod_enable+0x18/0x44 > #1: (enable_lock){......}, at: [<c0630684>] clk_enable_lock+0x18/0x124 > > stack backtrace: > CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.6.0-rc5-next-20160426+ #1127 > Hardware name: Generic OMAP36xx (Flattened Device Tree) > [<c0110290>] (unwind_backtrace) from [<c010c3a8>] (show_stack+0x10/0x14) > [<c010c3a8>] (show_stack) from [<c047fd68>] (dump_stack+0xb0/0xe4) > [<c047fd68>] (dump_stack) from [<c06315c0>] (clk_core_enable+0x1e0/0x36c) > [<c06315c0>] (clk_core_enable) from [<c0632298>] (clk_enable+0x1c/0x38) > [<c0632298>] (clk_enable) from [<c01204e0>] (_enable_clocks+0x18/0x7c) > [<c01204e0>] (_enable_clocks) from [<c012137c>] (_enable+0x114/0x2ec) > [<c012137c>] (_enable) from [<c0121b08>] (omap_hwmod_enable+0x24/0x44) > [<c0121b08>] (omap_hwmod_enable) from [<c0122ad0>] (omap_device_enable+0x3c/0x90) > [<c0122ad0>] (omap_device_enable) from [<c0122b34>] (_od_runtime_resume+0x10/0x38) > [<c0122b34>] (_od_runtime_resume) from [<c052cc00>] (__rpm_callback+0x2c/0x60) > [<c052cc00>] (__rpm_callback) from [<c052cc54>] (rpm_callback+0x20/0x80) > [<c052cc54>] (rpm_callback) from [<c052df7c>] (rpm_resume+0x3d0/0x6f0) > [<c052df7c>] (rpm_resume) from [<c052e2e8>] (__pm_runtime_resume+0x4c/0x64) > [<c052e2e8>] (__pm_runtime_resume) from [<c04bf2c4>] (omap2_gpio_resume_after_idle+0x54/0x68) > [<c04bf2c4>] (omap2_gpio_resume_after_idle) from [<c01269dc>] (omap3_enter_idle_bm+0xfc/0x1ec) > [<c01269dc>] (omap3_enter_idle_bm) from [<c0601888>] (cpuidle_enter_state+0x80/0x3d4) > [<c0601888>] (cpuidle_enter_state) from [<c0183b08>] (cpu_startup_entry+0x198/0x3a0) > [<c0183b08>] (cpu_startup_entry) from [<c0b00c0c>] (start_kernel+0x354/0x3c8) > [<c0b00c0c>] (start_kernel) from [<8000807c>] (0x8000807c) Reported-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Tested-by: Tony Lindgren <tony@atomide.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Cc: Russell King <linux@arm.linux.org.uk> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: <linux-omap@vger.kernel.org> Cc: <linux-arm-kernel@lists.infradead.org> Cc: <linux-clk@vger.kernel.org>
2016-06-15clk: Add _rcuidle tracepoints to allow clk_core_disable() use from idlePaul E. McKenney1-2/+2
This commit adds an _rcuidle suffix to a pair of trace events to prevent the following splat: > =============================== > [ INFO: suspicious RCU usage. ] > 4.6.0-rc5-next-20160426+ #1114 Not tainted > ------------------------------- > include/trace/events/clk.h:59 suspicious rcu_dereference_check() usage! > > other info that might help us debug this: > > > RCU used illegally from idle CPU! > rcu_scheduler_active = 1, debug_locks = 0 > RCU used illegally from extended quiescent state! > 2 locks held by swapper/0/0: > #0: (&oh->hwmod_key#30){......}, at: [<c0121b40>] omap_hwmod_idle+0x18/0x44 > #1: (enable_lock){......}, at: [<c0630998>] clk_enable_lock+0x18/0x124 > > stack backtrace: > CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.6.0-rc5-next-20160426+ #1114 > Hardware name: Generic OMAP36xx (Flattened Device Tree) > [<c0110290>] (unwind_backtrace) from [<c010c3a8>] (show_stack+0x10/0x14) > [<c010c3a8>] (show_stack) from [<c047fd68>] (dump_stack+0xb0/0xe4) > [<c047fd68>] (dump_stack) from [<c0631618>] (clk_core_disable+0x17c/0x348) > [<c0631618>] (clk_core_disable) from [<c0632774>] (clk_disable+0x24/0x30) > [<c0632774>] (clk_disable) from [<c0120590>] (_disable_clocks+0x18/0x7c) > [<c0120590>] (_disable_clocks) from [<c0121680>] (_idle+0x12c/0x230) > [<c0121680>] (_idle) from [<c0121b4c>] (omap_hwmod_idle+0x24/0x44) > [<c0121b4c>] (omap_hwmod_idle) from [<c0122c24>] (omap_device_idle+0x3c/0x90) > [<c0122c24>] (omap_device_idle) from [<c052cc00>] (__rpm_callback+0x2c/0x60) > [<c052cc00>] (__rpm_callback) from [<c052cc54>] (rpm_callback+0x20/0x80) > [<c052cc54>] (rpm_callback) from [<c052d150>] (rpm_suspend+0x100/0x768) > [<c052d150>] (rpm_suspend) from [<c052ec58>] (__pm_runtime_suspend+0x64/0x84) > [<c052ec58>] (__pm_runtime_suspend) from [<c04bf25c>] (omap2_gpio_prepare_for_idle+0x5c/0x70) > [<c04bf25c>] (omap2_gpio_prepare_for_idle) from [<c0125568>] (omap_sram_idle+0x140/0x244) > [<c0125568>] (omap_sram_idle) from [<c01269dc>] (omap3_enter_idle_bm+0xfc/0x1ec) > [<c01269dc>] (omap3_enter_idle_bm) from [<c0601bdc>] (cpuidle_enter_state+0x80/0x3d4) > [<c0601bdc>] (cpuidle_enter_state) from [<c0183b08>] (cpu_startup_entry+0x198/0x3a0) > [<c0183b08>] (cpu_startup_entry) from [<c0b00c0c>] (start_kernel+0x354/0x3c8) > [<c0b00c0c>] (start_kernel) from [<8000807c>] (0x8000807c) Reported-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Tested-by: Tony Lindgren <tony@atomide.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Cc: Russell King <linux@arm.linux.org.uk> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: <linux-omap@vger.kernel.org> Cc: <linux-arm-kernel@lists.infradead.org> Cc: <linux-clk@vger.kernel.org>
2016-06-13clk: imx: clk-pllv3: fix incorrect handle of enet powerdown bitDong Aisheng1-4/+4
After commit f53947456f98 ("ARM: clk: imx: update pllv3 to support imx7"), the former used BM_PLL_POWER bit is not correct anymore for IMX7 ENET. Instead, pll->powerdown holds the correct bit, so using powerdown bit in clk_pllv3_{prepare | unprepare} functions. Fixes: f53947456f98 ("ARM: clk: imx: update pllv3 to support imx7") Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-12clk: imx: fix pll clock parentsDong Aisheng5-34/+34
pllx_bypass_src mux shouldn't be the parent of pllx clock since it's only valid when when pllx BYPASS bit is set. Thus it is actually one parent of pllx_bypass only. Instead, pllx parent should be fixed to osc according to reference manual. Other plls have the same issue. e.g. before fix, the pll tree is: osc 6 6 24000000 0 0 pll1_bypass_src 0 0 24000000 0 0 pll1 0 0 792000000 0 0 pll1_bypass 0 0 792000000 0 0 pll1_sys 0 0 792000000 0 0 After the fix, it's: osc 6 6 24000000 0 0 pll1 0 0 792000000 0 0 pll1_bypass 0 0 792000000 0 0 pll1_sys 0 0 792000000 0 0 Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-12clk: imx7d: correct dram pll typeAnson Huang1-1/+1
DRAM PLL is a audio/video type PLL, need to correct it to get correct ops of PLL. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-12clk: imx7d: correct dram root clk parent selectAnson Huang1-1/+1
DRAM root clk should be either from pll dram main clk or dram alt root clk. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-12clk: imx: correct AV PLL rate formulaAnson Huang1-2/+6
The audio/video PLL's rate calculation is as below in RM: Fref * (DIV_SELECT + NUM / DENOM), in origin clk-pllv3's code, below code is used: (parent_rate * div) + ((parent_rate / mfd) * mfn as it does NOT consider the float data using div, so below formula should be used as a decent method: (parent_rate * div) + ((parent_rate * mfn) / mfd) and we also need to consider parent_rate * mfd may overflow a 32 bit value, 64 bit value should be used. After updating this formula, the dram PLL's rate is 1066MHz, which is correct, while the old formula gets 1056MHz. [Aisheng: fix clk_pllv3_av_round_rate too] Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-10clk: tegra: Fixup post dividers on Tegra210Thierry Reding1-47/+47
Commit 86c679a52294 ("clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate") changed the PLL divider computation logic to consistently use P-divider values from tables as real dividers rather than the hardware values. Unfortunately for some reason many of the Tegra210 clocks didn't have their tables updated (most likely an over- sight by me when applying the patches). This commit fixes them all up. Cc: Jon Hunter <jonathanh@nvidia.com> Cc: Rhyland Klein <rklein@nvidia.com> Acked-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-10clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag to PCIE deviceJaehoon Chung2-6/+8
This patch adds the CLK_IGNORE_UNUSED flag for PCI Express's clocks which need to remain enabled. The 'pcie' gate clock definition is also added. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> [s.nawrocki@samsung.com: edited the patch's summary] Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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