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git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/drivers
i.MX drivers updates for 4.12:
- A series from Lucas Stach which partly rewrites the imx gpc driver
to support multiple power domains, and moves the related code from
imx platform into drivers folder.
- A series from Dong Aisheng which fixes the issues with Lucas' code
changes and improves things.
- Add workaround for i.MX6QP hardware erratum ERR009619 that is PRE
clocks may be stalled during the power up sequencing of the PU power
domain.
- Add imx-gpcv2 driver to support power domains managed by GPCv2 IP
block found on i.MX7 series of SoCs.
* tag 'imx-drivers-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
soc: imx: gpc: add workaround for i.MX6QP to the GPC PD driver
dt-bindings: imx-gpc: add i.MX6 QuadPlus compatible
soc: imx: gpc: add defines for domain index
soc: imx: Add GPCv2 power gating driver
dt-bindings: Add GPCv2 power gating driver
soc: imx: gpc: remove unnecessary readable_reg callback
dt-bindings: imx-gpc: correct the DOMAIN_INDEX using
soc: imx: gpc: keep PGC_X_CTRL name align with reference manual
soc: imx: gpc: fix comment when power up domain
soc: imx: gpc: fix imx6sl gpc power domain regression
soc: imx: gpc: fix domain_index sanity check issue
soc: imx: gpc: fix the wrong using of regmap cache
soc: imx: gpc: fix gpc clk get error handling
soc: imx: move PGC handling to a new GPC driver
dt-bindings: add multidomain support to i.MX GPC DT binding
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/drivers
This moves the ICST helper library from arch/arm to drivers/clk
* tag 'arm-to-clk-icst' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM/clk: move the ICST library to drivers/clk
ARM: plat-versatile: remove stale clock header
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/drivers
Qualcomm ARM Based Driver Updates for v4.12
* Add SCM APIs for restore_sec_cfg and iommu secure page table
* tag 'qcom-drivers-for-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
firmware: qcom_scm: add two scm calls for iommu secure page table
firmware/qcom: add qcom_scm_restore_sec_cfg()
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers
soc/tegra: Core SoC changes for v4.12-rc1
This contains PMC support for Tegra186 as well as a proper driver for
the flow controller found on SoCs up to Tegra210. This also turns the
fuse driver into an explicitly non-modular driver.
* tag 'tegra-for-4.12-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
soc/tegra: Add initial flowctrl support for Tegra132/210
soc/tegra: flowctrl: Add basic platform driver
soc/tegra: Move Tegra flowctrl driver
ARM: tegra: Remove unnecessary inclusion of flowctrl header
soc: tegra: make fuse-tegra explicitly non-modular
soc/tegra: Fix link errors with PMC disabled
soc/tegra: Implement Tegra186 PMC support
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into next/drivers
ARM SOC PM domain support for 4.12
Dave Gerlach (5):
PM / Domains: Add generic data pointer to genpd data struct
PM / Domains: Do not check if simple providers have phandle cells
dt-bindings: Add TI SCI PM Domains
soc: ti: Add ti_sci_pm_domains driver
ARM: keystone: Drop PM domain support for k2g
* tag 'arm-soc-pmdomain' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone:
ARM: keystone: Drop PM domain support for k2g
soc: ti: Add ti_sci_pm_domains driver
dt-bindings: Add TI SCI PM Domains
PM / Domains: Do not check if simple providers have phandle cells
PM / Domains: Add generic data pointer to genpd data struct
Signed-off-by: Olof Johansson <olof@lixom.net>
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next/drivers
Reset controller changes for v4.12, part 2
Add reset lines for the NAND and eMMC contollers on LD11/LD20 SoCs.
* tag 'reset-for-4.12-2' of git://git.pengutronix.de/git/pza/linux:
reset: uniphier: add NAND and eMMC reset control
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/drivers
This adds a new driver for PalmChip PATA controller found on DM6446 and
DM6467 SoCs. This should eventually replace the driver in IDE subsystem.
The patches have been acked by ATA maintainer.
* tag 'davinci-for-v4.12/drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
pata_bk3710: clear status bits of BMISP on chipset initialization
pata_bk3710: disable IORDY Timer on chipset initialization
ata: add Palmchip BK3710 PATA controller driver
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/drivers
SCPI update for v4.12
Single patch to optimise the completion initialisation using reinit_*
API instead of full initialisation on each and every transfer.
* tag 'scpi-update-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
firmware: arm_scpi: reinit completion instead of full init_completion()
Signed-off-by: Olof Johansson <olof@lixom.net>
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On i.MX6QP, due to hardware erratum ERR009619, the PRE clocks may be
stalled during the power up sequencing of the PU power domain. As this
may lead to a complete loss of display output, the recommended
workaround is to keep the PU domain enabled during normal system
operation.
Implement this by rejecting the domain power down request on the
affected SoC.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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While the GPC on i.MX6QP is mostly comptible to the i.MX6Q one,
the QuadPlus requires special workarounds for hardware erratum
ERR009619.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Makes referencing a specfic domain in the driver code
less error prone.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add code allowing for control of various power domains managed by GPCv2
IP block found in i.MX7 series of SoCs. Power domains covered by this
patch are:
- PCIE PHY
- MIPI PHY
- USB HSIC PHY
- USB OTG1/2 PHY
Support for any other power domain controlled by GPC is not present, and
can be added at some later point.
Testing of this code was done against a PCIe driver.
Cc: yurovsky@gmail.com
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Dong Aisheng <dongas86@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add DT bindings for power domain driver for GPCv2 IP block found in
i.MX7 SoCs.
Cc: yurovsky@gmail.com
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Dong Aisheng <dongas86@gmail.com>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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This moves the ICST clock divider helper library from
arch/arm/common to drivers/clk/versatile so it is maintained
with the other clock drivers.
We keep the structure as a helper library intact and do not
fuse it with the clk-icst.c Versatile ICST clock driver: there
may be other users out there that need to use this library for
their clocking, and then it will be helpful to keep the
library contained. (The icst.[c|h] files could just be moved
to drivers/clk/lib or a similar location to share the library.)
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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All the Versatile platforms (Integrator, Versatile, RealView
Versatile Express) have been migrated to use the drivers/clk
subsystem. Clean out this header that is not referenced
anywhere anymore.
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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K2G will use a different power domain driver than the rest of the
keystone family in order to make use of the TI SCI protocol so prevent
the standard keystone pm_domain code from registering itself in
preparation for a new driver.
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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Introduce a ti_sci_pm_domains driver to act as a generic pm domain
provider to allow each device to attach and associate it's ti-sci-id so
that it can be controlled through the TI SCI protocol.
This driver implements a simple genpd where each device node has a
phandle to the power domain node and also must provide an index which
represents the ID to be passed with TI SCI representing the device using
a single phandle cell. The driver manually parses the phandle to get the
cell value. Through this interface the genpd dev_ops start and stop
hooks will use TI SCI to turn on and off each device as determined by
pm_runtime usage.
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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Add a generic power domain implementation, TI SCI PM Domains, that
will hook into the genpd framework and allow the TI SCI protocol to
control device power states.
Also, provide macros representing each device index as understood
by TI SCI to be used in the device node power-domain references.
These are identifiers for the K2G devices managed by the PMMC.
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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There is no reason that a platform genpd driver registered using
of_genpd_add_provider_simple needs to be constrained to having no cells
in the "power-domains" phandle. Currently the genpd framework will fail
if any arguments are passed with for a simple provider but the framework
does not actually care, so remove the check for phandle argument count.
This will allow greater flexibility for genpd providers to use their own
arguments that are passed in the phandle and interpret them however they
see fit.
Acked-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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Add a void *data pointer to struct generic_pm_domain_data. Because this
exists for each device associated with a genpd it will allow us to
assign per-device data if needed on a platform for control of that
specific device.
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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Tegra132 and Tegra210 support the flowctrl module and so add initial
support for these devices.
Please note that Tegra186 does not support the flowctrl module, so
update the initialisation function such that we do not fall back and
attempt to map the 'hardcoded' address range for Tegra186. Furthermore
64-bit Tegra devices have always had the flowctrl node defined in their
device-tree and so only use the 'hardcoded' addresses for 32-bit Tegra
devices.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add a simple platform driver for the flowctrl module so that it gets
registered as a proper device.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The flowctrl driver is required for both ARM and ARM64 Tegra devices
and in order to enable support for it for ARM64, move the Tegra flowctrl
driver into drivers/soc/tegra.
By moving the flowctrl driver, tegra_flowctrl_init() is now called by
via an early initcall and to prevent this function from attempting to
mapping IO space for a non-Tegra device, a test for 'soc_is_tegra()'
is also added.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The Tegra flowctrl.h header is included unnecessarily by the Tegra
sleep.S source file. Remove this unnecessary inclusion.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The Makefiles currently controlling compilation of this code is:
drivers/soc/tegra/Makefile:obj-y += fuse/
drivers/soc/tegra/fuse/Makefile:obj-y += fuse-tegra.o
...meaning that it currently is not being built as a module by anyone.
Lets remove the couple traces of modularity so that when reading the
driver there is no doubt it is builtin-only.
Since module_platform_driver() uses the same init level priority as
builtin_platform_driver() the init ordering remains unchanged with
this commit.
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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With the new Tegra186 PMC driver merged, anything that relies on the previous
PMC driver fails to link when that is disabled:
arch/arm/mach-tegra/pm.o: In function `tegra_pm_set':
pm.c:(.text.tegra_pm_set+0x3c): undefined reference to `tegra_pmc_enter_suspend_mode'
arch/arm/mach-tegra/pm.o: In function `tegra_suspend_enter':
pm.c:(.text.tegra_suspend_enter+0x4): undefined reference to `tegra_pmc_get_suspend_mode'
arch/arm/mach-tegra/pm.o: In function `tegra_init_suspend':
pm.c:(.init.text+0x1c): undefined reference to `tegra_pmc_get_suspend_mode'
pm.c:(.init.text+0x74): undefined reference to `tegra_pmc_set_suspend_mode'
ERROR: tegra_powergate_sequence_power_up [drivers/ata/ahci_tegra.ko] undefined!
ERROR: tegra_powergate_power_off [drivers/ata/ahci_tegra.ko] undefined!
Making the definition depend on the presence of the driver makes it build
again, though that might not be the correct fix.
Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
Fixes: 854014236290 ("soc/tegra: Implement Tegra186 PMC support")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The power management controller on Tegra186 has changed in backwards-
incompatible ways with respect to earlier generations. This implements a
new driver that supports inversion of the PMU interrupt as well as the
"recovery", "bootloader" and "forced-recovery" reboot commands.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Instead of performing full initialization of the completion structure
on each transfer in scpi_send_message(), we initialize it at boot time
(more specifically, in the relevant probe() function) and use
reinit_completion() to reset ->done counter on each message transfer.
Signed-off-by: Alexey Klimov <alexey.klimov@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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into next/drivers
Pull "Broadcom drivers changes for 4.12" from Florian Fainelli:
This pull request contains Broadcom ARM-based SoC drivers updates for 4.12,
please pull the following changes:
- Florian updates the Broadcom STB GISB arbiter driver with a bunch of
compatible strings for MIPS-based STBs found under arch/mips/boot/dts/brcm/ in
order for the SoC identification driver to recognize these chips
* tag 'arm-soc/for-4.12/drivers' of http://github.com/Broadcom/stblinux:
soc: bcm: brcmstb: Match additional compatible strings
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git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/drivers
Pull "Amlogic driver updates for v4.12" from Kevin Hilman:
- firmware: updates/fixes for meson-sm
* tag 'amlogic-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
firmware: meson-sm: Allow 0 as valid return value
firmware: meson-sm: Check for buffer output size
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Clear IORDYINT, INTRSTAT and DMAERROR bits of BMISP register
(value '1' needs to be written to the bit to clear it).
Suggested-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Tejun Heo <tj@kernel.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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Disable IORDY Timer as the driver doesn't handle IORDY Timer
interrupt anyway.
Suggested-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Tejun Heo <tj@kernel.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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Add Palmchip BK3710 PATA controller driver.
Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Tejun Heo <tj@kernel.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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Those two new SCM calls are needed from qcom-iommu driver in order
to initialize secure iommu page table.
Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Add reset lines for the Denali NAND controller on all UniPhier SoCs,
for the Cadence eMMC controller on LD11/LD20 SoCs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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It is not really necessary to provide the current .readable_reg
implementation as we know what we're doing in our driver
and the regmap core has already done the partial check for
available maximum regs.
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Actually DOMAIN_INDEX is not used by the client devices to refer to
the power domain, it uses phandle. Corrent the binding doc a bit
to avoid confusing.
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Instead of GPC_PGC_PDN_OFFS, naming it as GPC_PGC_CTRL_OFFS which is
defined in reference manual for better reading.
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The correct comment should be power up domain.
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Commit 721cabf6c660 ("soc: imx: move PGC handling to a new GPC driver")
broke the MX6SL GPC power domain support.
It always got the following error:
[ 1.248364] imx-gpc 20dc000.gpc: could not find pgc DT node
This patch adds back the legecy support.
Fixes: 721cabf6c660 ("soc: imx: move PGC handling to a new GPC driver")
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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ARRAY_SIZE(imx_gpc_domains) represents all power domains supported
by different SoCs. Driver should use SoC specific of_id_data->num_domains
instead to do power domain index sanity check.
e.g. MX6Q supports two power domains while MX6SL supports three.
Fixes: 721cabf6c660 ("soc: imx: move PGC handling to a new GPC driver")
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Without providing the proper reg_defaults, the regmap registers first
read out may be always 0 if enabling cache, which results in the
following issue we met.
e.g. During driver probe in imx6_pm_domain_power_on():
regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PUPSCR_OFFS, &val);
The PGC_PUPSCR register val is always 0 but it's actually 0xf01 in HW.
Since GPC registers are tightly related to CPU bring up and may be
changed in bootloader, we don't want to provide defaults.
And the cache really does not save too much for GPC module.
Therefore, simply disable cache to fix the issue and make life easy.
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Fixes: 721cabf6c660 ("soc: imx: move PGC handling to a new GPC driver")
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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We got a following kernel crash once supplying one more IPG
clock in GPC node in devicetree. The original error handling of
clocks get is a bit wrong that when reaching the maximum clock
get error, the index 'i' is already GPC_CLK_MAX which can't be used
as the array index for clk_put operations.
[ 3.000110] imx-gpc 20dc000.gpc: more than 6 clocks
[ 3.005141] Unable to handle kernel NULL pointer dereference at virtual address 00000000
[ 3.013487] pgd = c0004000
[ 3.016300] [00000000] *pgd=00000000
[ 3.020060] Internal error: Oops: 805 [#1] SMP ARM
[ 3.024957] Modules linked in:
[ 3.028122] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 4.11.0-rc1-00056-g813791b-dirty #1140
[ 3.037801] Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
[ 3.044435] task: ef298000 task.stack: ef294000
[ 3.049080] PC is at __clk_put+0x38/0xec
[ 3.053103] LR is at 0x7f54ce9a
[ 3.056345] pc : [<c0537984>] lr : [<7f54ce9a>] psr: 60000013
[ 3.056345] sp : ef295d48 ip : c8a582b2 fp : ef295d64
[ 3.068026] r10: ee9fc400 r9 : 00000000 r8 : ef398c10
[ 3.073354] r7 : ef398c10 r6 : c1071264 r5 : c10710f0 r4 : eea5be80
[ 3.079986] r3 : 00000000 r2 : 00000000 r1 : 00000100 r0 : 00000001
[ 3.086621] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none
[ 3.093863] Control: 10c5387d Table: 1000404a DAC: 00000051
[ 3.099712] Process swapper/0 (pid: 1, stack limit = 0xef294210)
[ 3.105823] Stack: (0xef295d48 to 0xef296000)
...
[ 3.292660] Backtrace:
[ 3.295222] [<c053794c>] (__clk_put) from [<c0531028>] (clk_put+0x18/0x1c)
[ 3.302206] r6:c1071264 r5:c10710f0 r4:c107124c r3:00000001
[ 3.307977] [<c0531010>] (clk_put) from [<c0546ba0>] (imx_pgc_get_clocks+0x64/0x78)
[ 3.315747] [<c0546b3c>] (imx_pgc_get_clocks) from [<c0547124>] (imx_gpc_probe+0x204/0x31c)
[ 3.324209] r7:00000000 r6:c1070eb0 r5:00000001 r4:ef398c00
[ 3.329980] [<c0546f20>] (imx_gpc_probe) from [<c05e65f0>] (platform_drv_probe+0x5c/0xc0)
[ 3.338270] r10:c0f00608 r9:00000000 r8:00000000 r7:fffffdfb r6:c1070f20 r5:ef398c10
[ 3.346207] r4:ef398c10
[ 3.348849] [<c05e6594>] (platform_drv_probe) from [<c05e4250>] (driver_probe_device+0x214/0x2ec)
[ 3.357835] r7:c1070f20 r6:00000000 r5:c18cea74 r4:ef398c10
[ 3.363607] [<c05e403c>] (driver_probe_device) from [<c05e43ec>] (__driver_attach+0xc4/0xc8)
[ 3.372159] r9:c0f8b858 r8:c0f8b850 r7:00000000 r6:ef398c44 r5:c1070f20 r4:ef398c10
[ 3.380017] [<c05e4328>] (__driver_attach) from [<c05e21fc>] (bus_for_each_dev+0x7c/0xb0)
[ 3.388304] r6:c05e4328 r5:c1070f20 r4:00000000 r3:00000000
[ 3.394074] [<c05e2180>] (bus_for_each_dev) from [<c05e3bc4>] (driver_attach+0x28/0x30)
[ 3.402188] r6:c107f3e8 r5:eea5be00 r4:c1070f20
[ 3.406913] [<c05e3b9c>] (driver_attach) from [<c05e3740>] (bus_add_driver+0x19c/0x224)
[ 3.415034] [<c05e35a4>] (bus_add_driver) from [<c05e52fc>] (driver_register+0x88/0x108)
[ 3.423235] r7:c10e1000 r6:00000000 r5:c0f57d2c r4:c1070f20
[ 3.429004] [<c05e5274>] (driver_register) from [<c05e6534>] (__platform_driver_register+0x40/0x54)
[ 3.438160] r5:c0f57d2c r4:00000006
[ 3.441846] [<c05e64f4>] (__platform_driver_register) from [<c0f57d44>] (imx_gpc_driver_init+0x18/0x20)
[ 3.451360] [<c0f57d2c>] (imx_gpc_driver_init) from [<c010200c>] (do_one_initcall+0x4c/0x180)
[ 3.460008] [<c0101fc0>] (do_one_initcall) from [<c0f00e40>] (kernel_init_freeable+0x130/0x1f8)
[ 3.468820] r9:c0f8b858 r8:c0f8b850 r6:c0fc2414 r5:c10e1000 r4:00000006
[ 3.475637] [<c0f00d10>] (kernel_init_freeable) from [<c0ae6aec>] (kernel_init+0x18/0x124)
[ 3.484014] r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c0ae6ad4
[ 3.491951] r4:00000000
[ 3.494590] [<c0ae6ad4>] (kernel_init) from [<c01088d0>] (ret_from_fork+0x14/0x24)
[ 3.502267] r4:00000000 r3:ef294000
[ 3.505947] Code: e5943014 e5942018 e3530000 e3a01c01 (e5823000)
[ 3.512215] ---[ end trace 375f9f2a5ddeff3c ]---
[ 3.517036] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
Cc: Lucas Stach <l.stach@pengutronix.de>
Fixes: 721cabf6c660 ("soc: imx: move PGC handling to a new GPC driver")
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Some special SMC calls (i.e. the function used to retrieve the serial
number of the Amlogic SoCs) returns 0 in the register 0 also when the
data was successfully read instead of using the register to hold the
number of bytes returned in the bounce buffer as expected.
With the current implementation of the driver this is seen as an error
and meson_sm_call_read() returns an error even though the data was
correctly read.
To deal with this when we have no information about the amount of read
data (that is 0 is returned by the SMC call) we return to the caller
the requested amount of data and 0 as return value.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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After the data is read by the secure monitor driver it is being copied
in the output buffer checking only the size of the bounce buffer but not
the size of the output buffer.
Fix this in the secure monitor driver slightly changing the API. Fix
also the efuse driver that it is the only driver using this API to not
break bisectability.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> # for nvmem
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers
Renesas ARM Based SoC Drivers Updates for v4.12
* Identify RZ/G1N and RZ/G1H
* tag 'renesas-drivers-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
soc: renesas: Identify RZ/G1N
soc: renesas: Identify RZ/G1H
Signed-off-by: Olof Johansson <olof@lixom.net>
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next/drivers
Reset controller changes for v4.12
- make reset drivers with bool Kconfig options explicitly non-modular
- fix uniphier non-static symbol warnings
- fix socfpga nr_resets property
- new drivers for the Arria10 and i.MX7 system reset controllers
- fix sunxi 64-bit compilation
* tag 'reset-for-4.12-1' of git://git.pengutronix.de/git/pza/linux:
reset: sunxi: fix for 64-bit compilation
reset: Add Altera Arria10 SR Reset Controller
dt-bindings: reset: a10sr: Add Arria10 SR Reset Controller offsets
reset: Add i.MX7 SRC reset driver
reset-socfpga: Fix nr_resets property
reset: uniphier: fix non static symbol warnings
reset: pistachio: make it explicitly non-modular
reset: ath79: make it explicitly non-modular
reset: oxnas: make it explicitly non-modular
reset: meson: make it explicitly non-modular
Signed-off-by: Olof Johansson <olof@lixom.net>
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The Allwinner reset controller has 32-bit registers, so translating
the reset cell number into a register and bit offset should not use
any architecture dependent data size. Otherwise this breaks for 64-bit
architectures like arm64.
Fix this by making it clear that it's the hardware register width which
matters here in the calculation.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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This patch adds the reset controller functionality for
Peripheral PHYs to the Arria10 System Resource Chip.
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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