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2018-12-18pinctrl: sh-pfc: r8a7791: Remove bogus ctrl marks from qspi_data4_b groupGeert Uytterhoeven1-2/+1
The qspi_data4_b_mux[] array contains pin marks for the clock and chip select pins. The qspi_data4_b_pins[] array rightfully does not contain the corresponding pin numbers, as the control pins are provided by a separate group (qspi_ctrl_b). Fixes: 2d0c386f135e4186 ("pinctrl: sh-pfc: r8a7791: Add QSPI pin groups") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-18pinctrl: sh-pfc: r8a7740: Add missing LCD0 marks to lcd0_data24_1 groupGeert Uytterhoeven1-0/+1
The lcd0_data24_1_pins[] array contains the LCD0 D1[2-5] pin numbers, but the lcd0_data24_1_mux[] array lacks the corresponding pin marks. Fixes: 06c7dd866da70f6c ("sh-pfc: r8a7740: Add LCDC0 and LCDC1 pin groups and functions") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-18pinctrl: sh-pfc: r8a7740: Add missing REF125CK pin to gether_gmii groupGeert Uytterhoeven1-1/+1
The gether_gmii_mux[] array contains the REF125CK pin mark, but the gether_gmii_pins[] array lacks the corresponding pin number. Fixes: bae11d30d0cafdc5 ("sh-pfc: r8a7740: Add GETHER pin groups and functions") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-18pinctrl: sh-pfc: r8a77990: Fix IOCTRL reg state after s2ram on R-Car E3Geert Uytterhoeven1-0/+1
Due to an interaction with commit 9f2b76a2db3c4387 ("pinctrl: sh-pfc: r8a77990: Add R8A774C0 PFC support"), the state of the I/O Control Registers is saved/restored during s2ram on RZ/G2E, but not on R-Car E3. Hence on R-Car E3, SDHI voltage state is lost after system resume. Fix this by registering the I/O Control Registers on R-Car E3, too. Fixes: 33847a71373cd6ae ("pinctrl: sh-pfc: r8a77990: Add voltage switch operations for SDHI") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-18pinctrl: rza1: Handle devm_kasprintf() failure casesNicholas Mc Guire1-0/+5
devm_kasprintf() may return NULL on failure of internal allocation thus the assignments are not safe if not checked. On error rza1_pinctrl_register() respectively rza1_parse_gpiochip() return negative values so -ENOMEM in the (unlikely) failure case of devm_kasprintf() should be fine here. Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org> Fixes: 5a49b644b307 ("pinctrl: Renesas RZ/A1 pin and gpio controller") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-12-18pinctrl: sh-pfc: r8a77990: Add support for pull-up only pinsGeert Uytterhoeven1-5/+18
The R-Car Gen3 HardWare Manual Errata for Rev. 1.00 (Jul 2, 2018) states that the USB30_OVC pin supports pull-up only. It has a bit assigned in the pull-enable register (PUEN5), but not in the pull-up/down control register (PUD5). Add a check for this, to prevent configuring a prohibited setting. Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Fixes: 83f6941a42a5e773 ("pinctrl: sh-pfc: r8a77990: Add bias pinconf support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04pinctrl: rzn1: Fix of_get_child_count() error checkPhil Edworthy1-1/+1
If we assign the result of of_get_child_count() to an unsigned int, the code will not detect any errors. Therefore assign it to an int instead. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-12-04pinctrl: rzn1: Fix check for used MDIO busPhil Edworthy1-1/+1
This fixes the check for unused mdio bus setting and the following static checker warning: drivers/pinctrl/pinctrl-rzn1.c:198 rzn1_pinctrl_mdio_select() warn: always true condition '(ipctl->mdio_func[mdio] >= 0) => (0-u32max >= 0)' Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-23pinctrl: Add RZ/A2 pin and gpio controllerChris Brandt3-0/+531
Adds support for the pin and gpio controller found in R7S9210 (RZ/A2) SoCs. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-23dt-bindings: pinctrl: Add RZ/A2 pinctrl and GPIOChris Brandt2-0/+134
Add device tree binding documentation and header file for Renesas R7S9210 (RZ/A2) SoCs. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-20pinctrl: sh-pfc: r8a77980: Add QSPI pins, groups, and functionsDmitry Shifrin1-0/+70
Add the QSPI{0|1} pins/groups/functions to the R8A77980 PFC driver. [Sergei: ported to the upstream driver, fixed up the swapped QSPI0 SPCLK/ SSL pins, fixed up the comments, moved the QSPI pins/groups/functions to be in the alphanumeric order, removed unneeded empty lines, renamed the patch.] Signed-off-by: Dmitry Shifrin <dmitry.shifrin@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19pinctrl: sh-pfc: r8a77990: Add CAN FD pins, groups and functionsTakeshi Kihara1-2/+37
This patch adds CAN FD{0,1} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> [geert: Move canfd from common to automotive] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19pinctrl: sh-pfc: r8a77990: Add CAN pins, groups and functionsTakeshi Kihara1-2/+49
This patch adds CAN{0,1} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19pinctrl: sh-pfc: r8a77965: Add CAN FD pins, groups and functionsTakeshi Kihara1-0/+42
This patch adds CAN FD{0,1} pins, groups and functions to the R8A77965 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19pinctrl: sh-pfc: r8a77965: Add CAN pins, groups and functionsTakeshi Kihara1-0/+58
This patch adds CAN{0,1} pins, groups and functions to the R8A77965 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19pinctrl: sh-pfc: r8a7796: Add I2C{0,3,5} pins, groups and functionsTakeshi Kihara1-21/+77
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7796 SoC. These pins are physically muxed with other pins. Therefore, setup of MOD_SEL is needed for exclusive control with other pins. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19pinctrl: sh-pfc: r8a7795-es1: Add I2C{0,3,5} pins, groups and functionsTakeshi Kihara1-22/+75
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7795 ES1.x SoC. These pins are physically muxed with other pins. Therefore, setup of MOD_SEL is needed for exclusive control with other pins. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19pinctrl: sh-pfc: r8a7795: Add I2C{0,3,5} pins, groups and functionsTakeshi Kihara1-21/+74
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7795 SoC. These pins are physically muxed with other pins. Therefore, setup of MOD_SEL is needed for exclusive control with other pins. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19pinctrl: sh-pfc: Add physical pin multiplexing helper macrosUlrich Hecht1-0/+22
Used by I2C controllers 0, 3 and 5 in R8A7795 and R8A7796 SoCs. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19pinctrl: sh-pfc: r8a77995: Remove unused PINMUX_IPSR_{MSEL2,PHYS}()Geert Uytterhoeven1-6/+0
The PINMUX_IPSR_MSEL2() and PINMUX_IPSR_PHYS() macros are unused, and will conflict with generic macros that are to be added. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-19pinctrl: sh-pfc: r8a77990: Add HSCIF pins, groups, and functionsTakeshi Kihara1-2/+368
This patch adds HSCIF{0,1,2,3,4} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13pinctrl: sh-pfc: r8a77990: Add VIN[4|5] groups/functionsJacopo Mondi1-2/+298
Add pin, mux and functions definitions for VIN4 and VIN5 for R-Car E3. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13pinctrl: sh-pfc: r8a77965: Add VIN[4|5] groups/functionsJacopo Mondi1-0/+270
The VIN4 and VIN5 interfaces support parallel video input. Add pin, mux and functions definitions for VIN4 and VIN5 for R-Car M3-N. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13pinctrl: sh-pfc: r8a7796: Fix VIN versioned groupsJacopo Mondi1-12/+12
Versioned VIN groups can appear on different sets of pins. Using the VIN_DATA_PIN_GROUP macro now supports proper naming of said groups through an optional 'version' argument. Use the 'version' argument for said macro to fix naming of versioned groups for the R-Car M3-W R8A7796 SoC. Fixes: a5c2949ff7bd ("pinctrl: sh-pfc: r8a7796: Deduplicate VIN4 pin definitions") Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13pinctrl: sh-pfc: r8a7795: Fix VIN versioned groupsJacopo Mondi1-12/+12
Versioned VIN groups can appear on different sets of pins. Using the VIN_DATA_PIN_GROUP macro now supports proper naming of said groups through an optional 'version' argument. Use the 'version' argument for said macro to fix naming of versioned groups for the R-Car H3 R8A7795 SoC. Fixes: 9942a5b52990 ("pinctrl: sh-pfc: r8a7795: Deduplicate VIN4 pin definitions") Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13pinctrl: sh-pfc: r8a7792: Fix VIN versioned groupsJacopo Mondi1-3/+3
Versioned VIN groups can appear on different sets of pins. Using the VIN_DATA_PIN_GROUP macro now supports proper naming of said groups through an optional 'version' argument. Use the 'version' argument for said macro to fix naming of versioned groups for the R-Car V2H R8A7792 SoC. Fixes: 7dd74bb1f058 ("pinctrl: sh-pfc: r8a7792: Add VIN pin groups") Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13pinctrl: sh-pfc: Add optional arg to VIN_DATA_PIN_GROUPJacopo Mondi1-7/+8
VIN data groups may appear on different sets of pins, usually named "vinX_data_[a|b]". The existing VIN_DATA_PIN_GROUP() does not support appending the '_a' or '_b' suffix, leading to the definition of group names not consistent with the ones defined using the SH_PFC_PIN_GROUP() macro. Fix this by making the VIN_DATA_PIN_GROUP macro a variadic one, which accepts an optional 'version' argument. Fixes: 423caa52534f ("pinctrl: sh-pfc: r8a779[01]: Move 'union vin_data' to shared header file") Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13pinctrl: sh-pfc: r8a77970: Add QSPI pins, groups, and functionsDmitry Shifrin1-0/+70
Add the QSPI{0|1} pins/groups/functions to the R8A77970 PFC driver. [Sergei: ported to the upstream driver, fixed up the swapped QSPI0 SPCLK/ SSL pins, fixed up the comments, moved the QSPI pins/groups/functions to be in the alphanumeric order, removed unneeded empty lines, renamed the patch.] Signed-off-by: Dmitry Shifrin <dmitry.shifrin@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13pinctrl: sh-pfc: r8a77990: Add voltage switch operations for SDHITakeshi Kihara1-2/+33
This patch supports the {get,set}_io_voltage operations of SDHI. This operates the IOCTRL30 register on the R8A77990 SoC and makes 1.8V/3.3V signal voltage switch possible. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13pinctrl: sh-pfc: r8a77990: Add SDHI pins, groups and functionsTakeshi Kihara1-2/+216
This patch adds SDHI{0,1,3} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-06pinctrl: sh-pfc: r8a77470: Add SDHI supportFabrizio Castro1-2/+160
Add SH_PFC_PIN_CFG_IO_VOLTAGE definition for the SDHI pins capable of switching voltage, also add pin groups and functions for SDHI0 and SDHI1. Please note that with the RZ/G1C only 1 bit of the POC Control Register is used to control each interface. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-06MAINTAINERS: Remove Laurent Pinchart as Renesas pinctrl maintainerLaurent Pinchart1-1/+0
Geert Uytterhoeven has long taken over and I'm not involved anymore with the Renesas pinctrl driver. Remove myself from the maintainers list. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-06pinctrl: sh-pfc: Reduce kernel size for narrow VIN channelsGeert Uytterhoeven3-12/+25
Some VIN channels support less than 24 lanes. As union vin_data always consumes space for 24 lanes, this wastes memory. Hence introduce new smaller unions vin_data12 and vin_data16, to accommodate VIN channels with only 12 or 16 lanes. This reduces the static pin controller driver size by 320 bytes for R-Car V2H, and by 96 bytes for R-Car E2. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2018-11-06MAINTAINERS: Add Renesas RZ/A and RZ/N files to Renesas pinctrl sectionGeert Uytterhoeven1-0/+1
Add paths for the Renesas RZ/A and RZ/N series pin controller drivers, as they are not under sh-pfc/, but still maintained with the other Renesas pin controller drivers. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2018-11-06pinctrl: sh-pfc: r8a77990: Add Audio SSI pins, groups and functionsTakeshi Kihara1-2/+238
This patch adds Audio SSI{0,1,2,3,4,5,6,7,8,9} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [simon: rebase] Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-06pinctrl: sh-pfc: r8a77990: Add Audio clock pins, groups and functionsTakeshi Kihara1-2/+205
This patch adds AUDIO_CLK{A,B,C}, AUDIO_CLKOUT, AUDIO_CLKOUT{1,2,3} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [simon: rebase] Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-05pinctrl: sh-pfc: r8a77470: Add QSPI1 pin groupsFabrizio Castro1-0/+33
Add QSPI1 pin groups and function to the RZ/G1C (a.k.a. R8A77470) pinctrl driver. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-05pinctrl: sh-pfc: r8a77470: Add VIN pin groupsFabrizio Castro1-0/+184
Add VIN[01] pin groups and functions to the RZ/G1C (a.k.a. R8A77470) pinctrl driver. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-05pinctrl: sh-pfc: r8a77470: Add DU1 pin groupsFabrizio Castro1-0/+108
Add DU1 pin groups and function to the RZ/G1C (a.k.a. R8A77470) pinctrl driver. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-05pinctrl: sh-pfc: r8a77470: Add remaining I2C pin groupsFabrizio Castro1-0/+191
This patch adds I2C[0123] groups and functions to the RZ/G1C (a.k.a. R8A77470) pinctrl driver. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-05Linux 4.20-rc1v4.20-rc1Linus Torvalds1-2/+2
2018-11-05Merge tag 'tags/upstream-4.20-rc1' of git://git.infradead.org/linux-ubifsLinus Torvalds25-292/+2418
Pull UBIFS updates from Richard Weinberger: - Full filesystem authentication feature, UBIFS is now able to have the whole filesystem structure authenticated plus user data encrypted and authenticated. - Minor cleanups * tag 'tags/upstream-4.20-rc1' of git://git.infradead.org/linux-ubifs: (26 commits) ubifs: Remove unneeded semicolon Documentation: ubifs: Add authentication whitepaper ubifs: Enable authentication support ubifs: Do not update inode size in-place in authenticated mode ubifs: Add hashes and HMACs to default filesystem ubifs: authentication: Authenticate super block node ubifs: Create hash for default LPT ubfis: authentication: Authenticate master node ubifs: authentication: Authenticate LPT ubifs: Authenticate replayed journal ubifs: Add auth nodes to garbage collector journal head ubifs: Add authentication nodes to journal ubifs: authentication: Add hashes to index nodes ubifs: Add hashes to the tree node cache ubifs: Create functions to embed a HMAC in a node ubifs: Add helper functions for authentication support ubifs: Add separate functions to init/crc a node ubifs: Format changes for authentication support ubifs: Store read superblock node ubifs: Drop write_node ...
2018-11-04Merge tag 'nfs-for-4.20-2' of git://git.linux-nfs.org/projects/trondmy/linux-nfsLinus Torvalds5-40/+17
Pull NFS client bugfixes from Trond Myklebust: "Highlights include: Bugfix: - Fix build issues on architectures that don't provide 64-bit cmpxchg Cleanups: - Fix a spelling mistake" * tag 'nfs-for-4.20-2' of git://git.linux-nfs.org/projects/trondmy/linux-nfs: NFS: fix spelling mistake, EACCESS -> EACCES SUNRPC: Use atomic(64)_t for seq_send(64)
2018-11-04Merge branch 'timers-urgent-for-linus' of ↵Linus Torvalds7-0/+432
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull more timer updates from Thomas Gleixner: "A set of commits for the new C-SKY architecture timers" * 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: dt-bindings: timer: gx6605s SOC timer clocksource/drivers/c-sky: Add gx6605s SOC system timer dt-bindings: timer: C-SKY Multi-processor timer clocksource/drivers/c-sky: Add C-SKY SMP timer
2018-11-04Merge tag 'ntb-4.20' of git://github.com/jonmason/ntbLinus Torvalds6-110/+429
Pull NTB updates from Jon Mason: "Fairly minor changes and bug fixes: NTB IDT thermal changes and hook into hwmon, ntb_netdev clean-up of private struct, and a few bug fixes" * tag 'ntb-4.20' of git://github.com/jonmason/ntb: ntb: idt: Alter the driver info comments ntb: idt: Discard temperature sensor IRQ handler ntb: idt: Add basic hwmon sysfs interface ntb: idt: Alter temperature read method ntb_netdev: Simplify remove with client device drvdata NTB: transport: Try harder to alloc an aligned MW buffer ntb: ntb_transport: Mark expected switch fall-throughs ntb: idt: Set PCIe bus address to BARLIMITx NTB: ntb_hw_idt: replace IS_ERR_OR_NULL with regular NULL checks ntb: intel: fix return value for ndev_vec_mask() ntb_netdev: fix sleep time mismatch
2018-11-04Merge branch 'sched-urgent-for-linus' of ↵Linus Torvalds2-2/+2
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull scheduler fixes from Ingo Molnar: "A memory (under-)allocation fix and a comment fix" * 'sched-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: sched/topology: Fix off by one bug sched/rt: Update comment in pick_next_task_rt()
2018-11-04Merge branch 'x86-urgent-for-linus' of ↵Linus Torvalds47-171/+198
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fixes from Ingo Molnar: "A number of fixes and some late updates: - make in_compat_syscall() behavior on x86-32 similar to other platforms, this touches a number of generic files but is not intended to impact non-x86 platforms. - objtool fixes - PAT preemption fix - paravirt fixes/cleanups - cpufeatures updates for new instructions - earlyprintk quirk - make microcode version in sysfs world-readable (it is already world-readable in procfs) - minor cleanups and fixes" * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: compat: Cleanup in_compat_syscall() callers x86/compat: Adjust in_compat_syscall() to generic code under !COMPAT objtool: Support GCC 9 cold subfunction naming scheme x86/numa_emulation: Fix uniform-split numa emulation x86/paravirt: Remove unused _paravirt_ident_32 x86/mm/pat: Disable preemption around __flush_tlb_all() x86/paravirt: Remove GPL from pv_ops export x86/traps: Use format string with panic() call x86: Clean up 'sizeof x' => 'sizeof(x)' x86/cpufeatures: Enumerate MOVDIR64B instruction x86/cpufeatures: Enumerate MOVDIRI instruction x86/earlyprintk: Add a force option for pciserial device objtool: Support per-function rodata sections x86/microcode: Make revision and processor flags world-readable
2018-11-04Merge branch 'perf-urgent-for-linus' of ↵Linus Torvalds102-539/+3616
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull perf updates and fixes from Ingo Molnar: "These are almost all tooling updates: 'perf top', 'perf trace' and 'perf script' fixes and updates, an UAPI header sync with the merge window versions, license marker updates, much improved Sparc support from David Miller, and a number of fixes" * 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (66 commits) perf intel-pt/bts: Calculate cpumode for synthesized samples perf intel-pt: Insert callchain context into synthesized callchains perf tools: Don't clone maps from parent when synthesizing forks perf top: Start display thread earlier tools headers uapi: Update linux/if_link.h header copy tools headers uapi: Update linux/netlink.h header copy tools headers: Sync the various kvm.h header copies tools include uapi: Update linux/mmap.h copy perf trace beauty: Use the mmap flags table generated from headers perf beauty: Wire up the mmap flags table generator to the Makefile perf beauty: Add a generator for MAP_ mmap's flag constants tools include uapi: Update asound.h copy tools arch uapi: Update asm-generic/unistd.h and arm64 unistd.h copies tools include uapi: Update linux/fs.h copy perf callchain: Honour the ordering of PERF_CONTEXT_{USER,KERNEL,etc} perf cs-etm: Correct CPU mode for samples perf unwind: Take pgoff into account when reporting elf to libdwfl perf top: Do not use overwrite mode by default perf top: Allow disabling the overwrite mode perf trace: Beautify mount's first pathname arg ...
2018-11-04Merge branch 'irq-urgent-for-linus' of ↵Linus Torvalds2-3/+3
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq fixes from Ingo Molnar: "An irqchip driver fix and a memory (over-)allocation fix" * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/irq-mvebu-sei: Fix a NULL vs IS_ERR() bug in probe function irq/matrix: Fix memory overallocation
2018-11-04sched/topology: Fix off by one bugPeter Zijlstra1-1/+1
With the addition of the NUMA identity level, we increased @level by one and will run off the end of the array in the distance sort loop. Fixed: 051f3ca02e46 ("sched/topology: Introduce NUMA identity node sched domain") Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
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