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2026-02-04dt-bindings: dma: qcom,gpi: Update max interrupts lines to 16Pankaj Patil1-1/+1
Update interrupt maxItems to 16 from 13 per GPI instance to support Glymur, Qualcomm's latest gen SoC Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251231133114.2752822-1-pankaj.patil@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-02-04dmaengine: fsl-edma: don't explicitly disable clocks in .remove()Jared Kangas1-1/+0
The clocks in fsl_edma_engine::muxclk are allocated and enabled with devm_clk_get_enabled(), which automatically cleans these resources up, but these clocks are also manually disabled in fsl_edma_remove(). This causes warnings on driver removal for each clock: edma_module already disabled WARNING: CPU: 0 PID: 418 at drivers/clk/clk.c:1200 clk_core_disable+0x198/0x1c8 [...] Call trace: clk_core_disable+0x198/0x1c8 (P) clk_disable+0x34/0x58 fsl_edma_remove+0x74/0xe8 [fsl_edma] [...] ---[ end trace 0000000000000000 ]--- edma_module already unprepared WARNING: CPU: 0 PID: 418 at drivers/clk/clk.c:1059 clk_core_unprepare+0x1f8/0x220 [...] Call trace: clk_core_unprepare+0x1f8/0x220 (P) clk_unprepare+0x34/0x58 fsl_edma_remove+0x7c/0xe8 [fsl_edma] [...] ---[ end trace 0000000000000000 ]--- Fix these warnings by removing the unnecessary fsl_disable_clocks() call in fsl_edma_remove(). Fixes: a9903de3aa16 ("dmaengine: fsl-edma: refactor using devm_clk_get_enabled") Signed-off-by: Jared Kangas <jkangas@redhat.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260113-fsl-edma-clock-removal-v1-1-2025b49e7bcc@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-09dmaengine: xilinx: xdma: use sg_nents_for_dma() helperAndy Shevchenko1-4/+2
Instead of open coded variant let's use recently introduced helper. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20260108105619.3513561-14-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-09dmaengine: sh: use sg_nents_for_dma() helperAndy Shevchenko1-3/+2
Instead of open coded variant let's use recently introduced helper. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20260108105619.3513561-13-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-09dmaengine: sa11x0: use sg_nents_for_dma() helperAndy Shevchenko1-4/+2
Instead of open coded variant let's use recently introduced helper. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20260108105619.3513561-12-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-09dmaengine: qcom: bam_dma: use sg_nents_for_dma() helperAndy Shevchenko1-7/+2
Instead of open coded variant let's use recently introduced helper. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20260108105619.3513561-11-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-09dmaengine: qcom: adm: use sg_nents_for_dma() helperAndy Shevchenko1-5/+4
Instead of open coded variant let's use recently introduced helper. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20260108105619.3513561-10-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-09dmaengine: pxa-dma: use sg_nents_for_dma() helperAndy Shevchenko1-3/+2
Instead of open coded variant let's use recently introduced helper. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20260108105619.3513561-9-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-09dmaengine: lgm: use sg_nents_for_dma() helperAndy Shevchenko1-7/+2
Instead of open coded variant let's use recently introduced helper. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20260108105619.3513561-8-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-09dmaengine: k3dma: use sg_nents_for_dma() helperAndy Shevchenko1-7/+2
Instead of open coded variant let's use recently introduced helper. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20260108105619.3513561-7-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-09dmaengine: dw-axi-dmac: use sg_nents_for_dma() helperAndy Shevchenko1-4/+2
Instead of open coded variant let's use recently introduced helper. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20260108105619.3513561-6-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-09dmaengine: bcm2835-dma: use sg_nents_for_dma() helperAndy Shevchenko1-18/+1
Instead of open coded variant let's use recently introduced helper. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20260108105619.3513561-5-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-09dmaengine: axi-dmac: use sg_nents_for_dma() helperAndy Shevchenko1-4/+1
Instead of open coded variant let's use recently introduced helper. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Nuno Sá <nuno.sa@analog.com> Link: https://patch.msgid.link/20260108105619.3513561-4-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-09dmaengine: altera-msgdma: use sg_nents_for_dma() helperAndy Shevchenko1-4/+2
Instead of open coded variant let's use recently introduced helper. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20260108105619.3513561-3-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-09scatterlist: introduce sg_nents_for_dma() helperAndy Shevchenko2-0/+28
Sometimes the user needs to split each entry on the mapped scatter list due to DMA length constrains. This helper returns a number of entities assuming that each of them is not bigger than supplied maximum length. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20260108105619.3513561-2-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-09dmaengine: idxd: Add Max SGL Size Support for DSA3.0Yi Sun4-1/+28
Certain DSA 3.0 opcodes, such as Gather copy and Gather reduce, require max SGL configured for workqueues prior to supporting these opcodes. Configure the maximum scatter-gather list (SGL) size for workqueues during setup on the supported HW. Application can then properly handle the SGL size without explicitly setting it. Signed-off-by: Yi Sun <yi.sun@intel.com> Co-developed-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Tested-by: Yi Lai <yi1.lai@intel.com> Acked-by: Vinicius Costa Gomes <vinicius.gomes@intel.com> Link: https://patch.msgid.link/20260107-idxd-yi-sun-dsa3-sgl-size-v2-2-dbef8f559e48@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-09dmaengine: idxd: Expose DSA3.0 capabilities through sysfsYi Sun5-0/+73
Introduce sysfs interfaces for 3 new Data Streaming Accelerator (DSA) capability registers (dsacap0-2) to enable userspace awareness of hardware features in DSA version 3 and later devices. Userspace components (e.g. configure libraries, workload Apps) require this information to: 1. Select optimal data transfer strategies based on SGL capabilities 2. Enable hardware-specific optimizations for floating-point operations 3. Configure memory operations with proper numerical handling 4. Verify compute operation compatibility before submitting jobs The output format is <dsacap2>,<dsacap1>,<dsacap0>, where each DSA capability value is a 64-bit hexadecimal number, separated by commas. The ordering follows the DSA 3.0 specification layout: Offset: 0x190 0x188 0x180 Reg: dsacap2 dsacap1 dsacap0 Example: cat /sys/bus/dsa/devices/dsa0/dsacaps 000000000000f18d,0014000e000007aa,00fa01ff01ff03ff According to the DSA 3.0 specification, there are 15 fields defined for the three dsacap registers. However, there's no need to define all register structures unless a use case requires them. At this point, support for the Scatter-Gather List (SGL) located in dsacap0 is necessary, so only dsacap0 is defined accordingly. For reference, the DSA 3.0 specification is available at: Link: https://software.intel.com/content/www/us/en/develop/articles/intel-data-streaming-accelerator-architecture-specification.html Signed-off-by: Yi Sun <yi.sun@intel.com> Co-developed-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Tested-by: Yi Lai <yi1.lai@intel.com> Acked-by: Vinicius Costa Gomes <vinicius.gomes@intel.com> Link: https://patch.msgid.link/20260107-idxd-yi-sun-dsa3-sgl-size-v2-1-dbef8f559e48@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-09dmaengine: sh: rz-dmac: Make channel irq localGeert Uytterhoeven1-9/+6
The channel IRQ is only used inside the function rz_dmac_chan_probe(), so there is no need to store it in the rz_dmac_chan structure for later use. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/312c2e3349f4747e0bca861632bfc3592224b012.1767718556.git.geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-01dmaengine: pl08x: Fix comment stating the difference between PL080 and PL081Vladimir Zapolskiy1-1/+1
Fix a trivial typo in the comment, otherwise it takes an effort to understand what it actually means to say. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Link: https://patch.msgid.link/20251225173847.1395928-1-vz@mleia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-01dmaengine: at_xdmac: get the number of DMA channels from device treeTony Han1-3/+23
In case of kernel runs in non-secure mode, the number of DMA channels can be got from device tree since the value read from GTYPE register is "0" as it's always secured. As the number of channels can never be negative, update them to the type "unsigned". This is required for LAN969x. Signed-off-by: Tony Han <tony.han@microchip.com> Signed-off-by: Robert Marko <robert.marko@sartura.hr> Link: https://patch.msgid.link/20251203121208.1269487-1-robert.marko@sartura.hr Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-01dt-bindings: dma: atmel: add microchip,lan9691-dmaRobert Marko1-1/+3
Document Microchip LAN969x DMA compatible which is compatible to SAMA7G5. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251229184004.571837-10-robert.marko@sartura.hr Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-01dt-bindings: dma: snps,dw-axi-dmac: Add compatible string for Agilex5Khairul Anuar Romli1-5/+9
The address bus on Agilex5 is limited to 40 bits. When SMMU is enable this will cause address truncation and translation faults. Hence introducing "altr,agilex5-axi-dma" to enable platform specific configuration to configure the dma addressable bit mask. Add a fallback capability for the compatible property to allow driver to probe and initialize with a newly added compatible string without requiring additional entry in the driver. Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/dbc775f114445c06c6e4ce424333e1f3cbb92583.1766966955.git.khairul.anuar.romli@altera.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-01dt-bindings: dma: pl08x: Do not use plural form of a proper noun PrimeCellVladimir Zapolskiy1-1/+1
As a proper noun PrimeCell is a single entity and it can not have a plural form, fix the typo. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251225181519.1401953-1-vz@mleia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dt-bindings: dma: Update ADMA bindings for tegra264sheetal1-1/+14
- Update ADMA device tree bindings for tegra264 to support up to 64 interrupt channels by setting 'interrupts' property maxItems to 64. - Also, update the 'allOf' conditional schema to ensure correct maxItems for 'interrupts' based on compatible string, including tegra210 (22) and tegra186 (32) ADMA controllers. Signed-off-by: sheetal <sheetal@nvidia.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://patch.msgid.link/20250929105930.1767294-2-sheetal@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dma: dma-axi-dmac: simplify axi_dmac_parse_dt()Nuno Sá1-8/+5
Simplify axi_dmac_parse_dt() by using the cleanup device_node class for automatically releasing the of_node reference when going out of scope. Signed-off-by: Nuno Sá <nuno.sa@analog.com> base-commit: 398035178503bf662281bbffb4bebce1460a4bc5 change-id: 20251104-axi-dmac-fixes-and-improvs-e3ad512a329c Acked-by: Michael Hennerich <michael.hennerich@analog.com> Link: https://patch.msgid.link/20251104-axi-dmac-fixes-and-improvs-v1-4-3e6fd9328f72@analog.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dma: dma-axi-dmac: support bigger than 32bits addressesNuno Sá1-0/+24
In some supported platforms as ARCH_ZYNQMP, part of the memory is mapped above 32bit addresses and since the DMA mask, by default, is set to 32bits, we would need to rely on swiotlb (which incurs a performance penalty) for the DMA mappings. Thus, we can write either the SRC or DEST high addresses with 1's and read them back. The last bit set on the return value will reflect the IP address bus width and so we can update the device DMA mask accordingly. While at it, support bigger that 32 bits transfers in IP without HW scatter gather support. Signed-off-by: Nuno Sá <nuno.sa@analog.com> base-commit: 398035178503bf662281bbffb4bebce1460a4bc5 change-id: 20251104-axi-dmac-fixes-and-improvs-e3ad512a329c Acked-by: Michael Hennerich <michael.hennerich@analog.com> Link: https://patch.msgid.link/20251104-axi-dmac-fixes-and-improvs-v1-3-3e6fd9328f72@analog.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dma: dma-axi-dmac: fix HW scatter-gather not looking at the queueNuno Sá1-5/+3
For HW scatter gather transfers we still need to look for the queue. The HW is capable of queueing 3 concurrent transfers and if we try more than that we'll get the submit queue full and should return. Otherwise, if we go ahead and program the new transfer, we end up discarding it. Fixes: e97dc7435972 ("dmaengine: axi-dmac: Add support for scatter-gather transfers") Signed-off-by: Nuno Sá <nuno.sa@analog.com> base-commit: 398035178503bf662281bbffb4bebce1460a4bc5 change-id: 20251104-axi-dmac-fixes-and-improvs-e3ad512a329c Acked-by: Michael Hennerich <michael.hennerich@analog.com> Link: https://patch.msgid.link/20251104-axi-dmac-fixes-and-improvs-v1-2-3e6fd9328f72@analog.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dma: dma-axi-dmac: fix SW cyclic transfersNuno Sá1-2/+1
If 'hw_cyclic' is false we should still be able to do cyclic transfers in "software". That was not working for the case where 'desc->num_sgs' is 1 because 'chan->next_desc' is never set with the current desc which means that the cyclic transfer only runs once and in the next SOT interrupt we do nothing since vchan_next_desc() will return NULL. Fix it by setting 'chan->next_desc' as soon as we get a new desc via vchan_next_desc(). Fixes: 0e3b67b348b8 ("dmaengine: Add support for the Analog Devices AXI-DMAC DMA controller") Signed-off-by: Nuno Sá <nuno.sa@analog.com> base-commit: 398035178503bf662281bbffb4bebce1460a4bc5 change-id: 20251104-axi-dmac-fixes-and-improvs-e3ad512a329c Acked-by: Michael Hennerich <michael.hennerich@analog.com> Link: https://patch.msgid.link/20251104-axi-dmac-fixes-and-improvs-v1-1-3e6fd9328f72@analog.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dmaengine: st_fdma: add COMPILE_TEST supportRosen Penev1-1/+1
Add COMPILE_TEST as an option to allow test building the driver. Signed-off-by: Rosen Penev <rosenp@gmail.com> Link: https://patch.msgid.link/20251106022015.84970-3-rosenp@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dmaengine: st_fdma: change dreg_line to longRosen Penev2-2/+2
The code is encoding a pointer into an int which works fine with a 32-bit build. Not with a 64-bit one. Signed-off-by: Rosen Penev <rosenp@gmail.com> Link: https://patch.msgid.link/20251106022015.84970-2-rosenp@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dt-bindings: dma: qcom,gpi: Document GPI DMA engine for Kaanapali and Glymur ↵Jyothi Kumar Seerapu1-0/+2
SoCs Document the GPI DMA engine on the Kaanapali and Glymur platforms. Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20251105-knp-bus-v2-1-ed3095c7013a@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dmaengine: mediatek: mtk-uart-apdma: Add support for Dimensity 9200AngeloGioacchino Del Regno1-0/+1
Add a compatible string and match data for the APDMA IP version found in the MediaTek Dimensity 9200 MT6985 SoC; this supports extended addressing with up to 35 bits. Other SoCs with this IP version also include the Dimensity 9400 MT6991 and Kompanio Ultra MT8196 (which don't need a specific compatible in this driver and can reuse the mt6985 one). Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://patch.msgid.link/20251113122229.23998-9-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dmaengine: mediatek: mtk-uart-apdma: Add support for Dimensity 6300AngeloGioacchino Del Regno1-0/+1
Add a compatible string and match data for the APDMA IP version found in the MediaTek Dimensity 6300 MT6835 SoC; this supports extended addressing with up to 34 bits. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://patch.msgid.link/20251113122229.23998-8-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dmaengine: mediatek: mtk-uart-apdma: Rename support_33bits to support_ext_addrAngeloGioacchino Del Regno1-5/+5
In preparation for adding support for SoCs with APDMA IP versions supporting more than 33 bits addressing, rename the support_33bits variable to support_ext_addr to signal support for extended, above 4GB, addressing. This change is cosmetic only, and brings no functional differences. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://patch.msgid.link/20251113122229.23998-7-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dmaengine: mediatek: uart-apdma: Fix above 4G addressing TX/RXAngeloGioacchino Del Regno1-5/+5
The VFF_4G_SUPPORT register is named differently in datasheets, and its name is "VFF_ADDR2"; was this named correctly from the beginning it would've been clearer that there was a mistake in the programming sequence. This register is supposed to hold the high bits to support the DMA addressing above 4G (so, more than 32 bits) and not a bit to "enable" the support for VFF 4G. Fix the name of this register, and also fix its usage by writing the upper 32 bits of the dma_addr_t on it when the SoC supports such feature. Fixes: 9135408c3ace ("dmaengine: mediatek: Add MediaTek UART APDMA support") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://patch.msgid.link/20251113122229.23998-6-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dmaengine: mediatek: uart-apdma: Get addressing bits from match dataAngeloGioacchino Del Regno1-7/+6
The only SoC that declares mediatek,dma-33bits in its devicetree currently is MT6795, which obviously also declares a SoC-specific compatible string: in preparation for adding new SoCs with 34 bits addressing, replace the parsing of said vendor property with logic to get the number of addressing bits from platform data associated to compatible strings. While at it, also make the bit_mask variable unsigned and move the `int rc` declaration as last to beautify the code. Thanks to the correct declaration of the APDMA node is in all of the MediaTek device trees that are currently upstream, this commit brings no functional differences. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251113122229.23998-5-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dt-bindings: dma: mediatek,uart-dma: Support all SoC generationsAngeloGioacchino Del Regno1-0/+18
Add support for the APDMA IP found in all of the SoC generations that are currently supported upstream; this includes: - MT8173, MT8183, fully compatible with MT6577 (32-bits) - MT7988, MT8186, MT8188, MT8192, MT8195 and MT6835 (34-bits) - MT6991, MT8196 and MT6985 (35-bits) ...where: - MT6835 is the first SoC where the AP_DMA IP supports 34-bits addressing; and - MT6985 is the first SoC where the AP_DMA IP supports 35-bits addressing. While at it, also add myself in the maintainers list. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251113122229.23998-4-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dt-bindings: dma: mediatek,uart-dma: Deprecate mediatek,dma-33bitsAngeloGioacchino Del Regno1-0/+1
While this property wants to express a capability of the hardware, this is only used by the driver itself to vary the DMA bits during probe. Different hardware shall instead have different compatible strings. Following the driver cleanup and the introduction of a specific compatible string for the APDMA IP version found in MT6795, set the "mediatek,dma-33bits" vendor property as deprecated. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251113122229.23998-3-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dt-bindings: dma: mediatek,uart-dma: Allow MT6795 single compatibleAngeloGioacchino Del Regno1-0/+1
While it is true that this SoC is compatible with the MT6577 APDMA IP, that is valid only when the IP is used in 32-bits addressing mode, and, by the way there is no good reason to do so. Since the APDMA IP in MT6795 supports 33 bits addressing, this means that it is a newer revision compared to the one found in MT6577, hence only partially compatible with it. Allow nodes to specify "mediatek,mt6795-uart-dma" as their only compatible in the case of MT6795; this is done in lieu of the fact that there are other SoCs integrating the same version of this IP as MT6795, and those will eventually get their own compatible that expresses full compatibility with this SoC. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251113122229.23998-2-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dmaengine: stm32-mdma: initialize m2m_hw_period and ccr to fix warningsClément Le Goffic1-1/+1
m2m_hw_period is initialized only when chan_config->m2m_hw is true. This triggers a warning: ‘m2m_hw_period’ may be used uninitialized [-Wmaybe-uninitialized] Although m2m_hw_period is only used when chan_config->m2m_hw is true and ignored otherwise, initialize it unconditionally to 0. ccr is initialized by stm32_mdma_set_xfer_param() when the sg list is not empty. This triggers a warning: ‘ccr’ may be used uninitialized [-Wmaybe-uninitialized] Indeed, it could be used uninitialized if the sg list is empty. Initialize it to 0. Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com> Reviewed-by: Clément Le Goffic <legoffic.clement@gmail.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://patch.msgid.link/20251217-mdma_warnings_fix-v2-1-340200e0bb55@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dmaengine: xilinx_dma: Add support for residue on direct AXIDMA S2MMTomi Valkeinen1-0/+21
AXIDMA IP supports reporting the amount of bytes transferred on the S2MM channel in direct mode (i.e. non-SG), but the driver does not. Thus the driver always reports that all of the buffer was filled. Add xilinx_dma_get_residue_axidma_direct_s2mm() which gets the residue amount for direct AXIDMA for S2MM direction. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Reviewed-by: Suraj Gupta <suraj.gupta2@amd.com> Link: https://patch.msgid.link/20251218-xilinx-dma-residue-fix-v1-1-7cd221d69d6b@ideasonboard.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dmaengine: sun6i: Add debug messages for cyclic DMA prepareChen-Yu Tsai1-0/+10
The driver already has debug messages for memcpy and linear transfers, but is missing them for cyclic transfers. Cyclic transfers are one of the main uses of the DMA controller, used for audio data transfers. And since these are likely the first DMA peripherals to be enabled, it helps to have these debug messages. Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Chen-Yu Tsai <wens@kernel.org> Link: https://patch.msgid.link/20251221064754.1783369-1-wens@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dmaengine: sun6i: Choose appropriate burst length under maxburstChen-Yu Tsai1-6/+20
maxburst, as provided by the client, specifies the largest amount of data that is allowed to be transferred in one burst. This limit is normally provided to avoid a data burst overflowing the target FIFO. It does not mean that the DMA engine can only do bursts in that size. Let the driver pick the largest supported burst length within the given limit. This lets the driver work correctly with some clients that give a large maxburst value. In particular, the 8250_dw driver will give a quarter of the UART's FIFO size as maxburst. On some systems the FIFO size is 256 bytes, giving a maxburst of 64 bytes, while the hardware only supports bursts of up to 16 bytes. Signed-off-by: Chen-Yu Tsai <wens@kernel.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251221080450.1813479-1-wens@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dmaengine: idxd: uapi: use UAPI typesThomas Weißschuh1-137/+133
Using libc types and headers from the UAPI headers is problematic as it introduces a dependency on a full C toolchain. Use the fixed-width integer types provided by the UAPI headers instead. Signed-off-by: Thomas Weißschuh <thomas.weissschuh@linutronix.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Link: https://patch.msgid.link/20251222-uapi-idxd-v1-1-baa183adb20d@linutronix.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23dmaengine: sh: Discard pm_runtime_put() return valueRafael J. Wysocki1-1/+1
Clobbering an error value to be returned from shdma_tx_submit() with a pm_runtime_put() return value is not particularly useful, especially if the latter is 0, so stop doing that. This will facilitate a planned change of the pm_runtime_put() return type to void in the future. Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/9626129.rMLUfLXkoz@rafael.j.wysocki Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-16dmaengine: shdma: correct most kernel-doc issues in shdma-base.hRandy Dunlap1-14/+14
Fix kernel-doc comments in include/linux/shdma-base.h to avoid most warnings: - prefix an enum name with "enum" - prefix enum values with '@' - prefix struct member names with '@' shdma-base.h:28: warning: cannot understand function prototype: 'enum shdma_pm_state ' Warning: shdma-base.h:103 struct member 'desc_completed' not described in 'shdma_ops' Warning: shdma-base.h:103 struct member 'halt_channel' not described in 'shdma_ops' Warning: shdma-base.h:103 struct member 'channel_busy' not described in 'shdma_ops' Warning: shdma-base.h:103 struct member 'slave_addr' not described in 'shdma_ops' Warning: shdma-base.h:103 struct member 'desc_setup' not described in 'shdma_ops' Warning: shdma-base.h:103 struct member 'set_slave' not described in 'shdma_ops' Warning: shdma-base.h:103 struct member 'setup_xfer' not described in 'shdma_ops' Warning: shdma-base.h:103 struct member 'start_xfer' not described in 'shdma_ops' Warning: shdma-base.h:103 struct member 'embedded_desc' not described in 'shdma_ops' Warning: shdma-base.h:103 struct member 'chan_irq' not described in 'shdma_ops' This one is not fixed: from 4f46f8ac80416: Warning: shdma-base.h:103 struct member 'get_partial' not described in 'shdma_ops' Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Link: https://patch.msgid.link/20251104002001.445297-1-rdunlap@infradead.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-16dmaengine: dw_edma: correct kernel-doc warnings in <linux/dma/edma.h>Randy Dunlap1-13/+11
Use the correct enum name in its kernel-doc heading. Add ending ':' to struct member names. Drop the @id: kernel-doc entry since there is no struct member named 'id'. edma.h:46: warning: expecting prototype for struct dw_edma_core_ops. Prototype was for struct dw_edma_plat_ops instead Warning: edma.h:101 struct member 'ops' not described in 'dw_edma_chip' Warning: edma.h:101 struct member 'flags' not described in 'dw_edma_chip' Warning: edma.h:101 struct member 'reg_base' not described in 'dw_edma_chip' Warning: edma.h:101 struct member 'll_wr_cnt' not described in 'dw_edma_chip' Warning: edma.h:101 struct member 'll_rd_cnt' not described in 'dw_edma_chip' Warning: edma.h:101 struct member 'll_region_wr' not described in 'dw_edma_chip' Warning: edma.h:101 struct member 'll_region_rd' not described in 'dw_edma_chip' Warning: edma.h:101 struct member 'dt_region_wr' not described in 'dw_edma_chip' Warning: edma.h:101 struct member 'dt_region_rd' not described in 'dw_edma_chip' Warning: edma.h:101 struct member 'mf' not described in 'dw_edma_chip' Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Link: https://patch.msgid.link/20251101191524.1991135-1-rdunlap@infradead.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-16dmaengine: zynqmp_dma: Remove redundant pm_runtime_mark_last_busy() callsSakari Ailus1-2/+0
pm_runtime_put_autosuspend(), pm_runtime_put_sync_autosuspend(), pm_runtime_autosuspend() and pm_request_autosuspend() now include a call to pm_runtime_mark_last_busy(). Remove the now-reduntant explicit call to pm_runtime_mark_last_busy(). Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Reviewed-by: Abin Joseph <abin.joseph@amd.com> Link: https://patch.msgid.link/20251027133232.392898-6-sakari.ailus@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-16dmaengine: ti: Remove redundant pm_runtime_mark_last_busy() callsSakari Ailus1-5/+0
pm_runtime_put_autosuspend(), pm_runtime_put_sync_autosuspend(), pm_runtime_autosuspend() and pm_request_autosuspend() now include a call to pm_runtime_mark_last_busy(). Remove the now-reduntant explicit call to pm_runtime_mark_last_busy(). Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Link: https://patch.msgid.link/20251027133232.392898-5-sakari.ailus@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-16dmaengine: ste_dma40: Remove redundant pm_runtime_mark_last_busy() callsSakari Ailus1-12/+2
pm_runtime_put_autosuspend(), pm_runtime_put_sync_autosuspend(), pm_runtime_autosuspend() and pm_request_autosuspend() now include a call to pm_runtime_mark_last_busy(). Remove the now-reduntant explicit call to pm_runtime_mark_last_busy(). Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://patch.msgid.link/20251027133232.392898-4-sakari.ailus@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2026-05-02 16:12:08 +0300