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2026-01-14phy: apple: atc: Actually check return value of devm_apple_tunable_parseSven Peter1-3/+3
Let's actually check the return value of devm_apple_tunable_parse instead of trying to check IS_ERR on a pointer to the return value which is always going to be valid. This prevent a oops when the tunables are invalid or when they don't exist: [ 57.664567] Unable to handle kernel paging request at virtual address fffffffffffffffe [ 57.664584] Mem abort info: [ 57.664589] ESR = 0x0000000096000007 [ 57.664595] EC = 0x25: DABT (current EL), IL = 32 bits [ 57.664602] SET = 0, FnV = 0 [ 57.664607] EA = 0, S1PTW = 0 [ 57.664611] FSC = 0x07: level 3 translation fault [ 57.664617] Data abort info: [ 57.664621] ISV = 0, ISS = 0x00000007, ISS2 = 0x00000000 [ 57.664626] CM = 0, WnR = 0, TnD = 0, TagAccess = 0 [ 57.664631] GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0 [ 57.664640] swapper pgtable: 16k pages, 47-bit VAs, pgdp=0000000b4391c000 [ 57.664647] [fffffffffffffffe] pgd=0000000000000000, p4d=0000000000000000, pud=0000000b44188403, pmd=0000000b4418c403, pte=0000000000000000 [ 57.664670] Internal error: Oops: 0000000096000007 [#1] SMP [ 57.665047] CPU: 1 UID: 0 PID: 23 Comm: kworker/1:0 Tainted: G S 6.18.2+ #2 PREEMPTLAZY [ 57.665061] Tainted: [S]=CPU_OUT_OF_SPEC [ 57.665066] Hardware name: Apple Mac mini (M1, 2020) (DT) [ 57.665072] Workqueue: events cd321x_update_work [tps6598x] [ 57.665100] pstate: 61400009 (nZCv daif +PAN -UAO -TCO +DIT -SSBS BTYPE=--) [ 57.665111] pc : apple_tunable_apply+0x8/0x80 [apple_tunable] [ 57.665121] lr : atcphy_mux_set+0x3e0/0x1138 [phy_apple_atc] [ 57.665133] sp : ffffc000802a7c00 [ 57.665138] x29: ffffc000802a7c00 x28: 0000000000000003 x27: ffff800016c84080 [ 57.665151] x26: 0000000000000002 x25: ffff800016c84090 x24: ffff800016c8408f [ 57.665163] x23: 0000000000020004 x22: 0000000000000001 x21: 0000000000000006 [ 57.665175] x20: ffff80000d6da9b0 x19: ffff80000d6da880 x18: 0000000000000002 [ 57.665188] x17: 0000000000000000 x16: ffffe22de59e0e38 x15: 0000000000000002 [ 57.665199] x14: ffffe22de76ecff8 x13: 0000000000000001 x12: ffff9dd5f90bc000 [ 57.665211] x11: 00000000000000c0 x10: 048abc15ceba0919 x9 : ffffe22dbc5fde10 [ 57.665223] x8 : ffff80000175e0d8 x7 : 0000000000000004 x6 : 0000000000000000 [ 57.665234] x5 : 0000000000000001 x4 : 0000000d6d132db7 x3 : 00000000000155db [ 57.665246] x2 : 0000000000000000 x1 : fffffffffffffffe x0 : ffffc00082b80000 [ 57.665258] Call trace: [ 57.665265] apple_tunable_apply+0x8/0x80 [apple_tunable] (P) [ 57.665276] typec_mux_set+0x74/0xe0 [typec] [ 57.665315] cd321x_update_work+0x440/0x8c0 [tps6598x] [ 57.665332] process_one_work+0x178/0x3d0 [ 57.665346] worker_thread+0x260/0x390 [ 57.665354] kthread+0x150/0x250 [ 57.665369] ret_from_fork+0x10/0x20 [ 57.665386] Code: e69a0ae8 ffffe22d aa1e03e9 d503201f (f9400022) [ 57.665394] ---[ end trace 0000000000000000 ]--- Reported-by: Thomas Glanzmann <thomas@glanzmann.de> Fixes: 8e98ca1e74db ("phy: apple: Add Apple Type-C PHY") Signed-off-by: Sven Peter <sven@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260104-atcphy-tunable-fix-v2-1-84e5c2a57aaa@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-14phy: qcom: edp: Fix NULL pointer dereference for phy v6 (x1e80100)Val Packett1-0/+1
For Glymur SoC support, the com_clk_fwd_cfg callback was added, and a stub implementation was added for the v4 of the hardware. However it was omitted for the v6, causing a NULL pointer dereference oops on Hamoa/Purwa (X1E/X1P) SoC devices. Fix by adding the appropriate stub. Fixes: add66a6673bc ("phy: qcom: edp: Add Glymur platform support") Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Val Packett <val@packett.cool> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Tested-by: Yijie Yang <yijie.yang@oss.qualcomm.com> # Purwa-IoT-EVK Link: https://patch.msgid.link/20260111083317.604754-1-val@packett.cool Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-14Merge tag 'phy_common_properties' into nextVinod Koul9-103/+858
phy common properties Vladimir Oltean <vladimir.oltean@nxp.com> wrote: Introduce "rx-polarity" and "tx-polarity" device tree properties with Kunit tests
2026-01-14phy: add phy_get_rx_polarity() and phy_get_tx_polarity()Vladimir Oltean6-0/+697
Add helpers in the generic PHY folder which can be used using 'select PHY_COMMON_PROPS' from Kconfig, without otherwise needing to enable GENERIC_PHY. These helpers need to deal with the slight messiness of the fact that the polarity properties are arrays per protocol, and with the fact that there is no default value mandated by the standard properties, all default values depend on driver and protocol (PHY_POL_NORMAL may be a good default for SGMII, whereas PHY_POL_AUTO may be a good default for PCIe). Push the supported mask of polarities to these helpers, to simplify drivers such that they don't need to validate what's in the device tree (or other firmware description). Add a KUnit test suite to make sure that the API produces the expected results. The fact that we use fwnode structures means we can validate with software nodes, and as opposed to the device_property API, we can bypass the need to have a device structure. Co-developed-by: Bjørn Mork <bjorn@mork.no> Signed-off-by: Bjørn Mork <bjorn@mork.no> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Link: https://patch.msgid.link/20260111093940.975359-6-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-14dt-bindings: phy-common-props: RX and TX lane polarity inversionVladimir Oltean2-0/+53
Differential signaling is a technique for high-speed protocols to be more resilient to noise. At the transmit side we have a positive and a negative signal which are mirror images of each other. At the receiver, if we subtract the negative signal (say of amplitude -A) from the positive signal (say +A), we recover the original single-ended signal at twice its original amplitude. But any noise, like one coming from EMI from outside sources, is supposed to have an almost equal impact upon the positive (A + E, E being for "error") and negative signal (-A + E). So (A + E) - (-A + E) eliminates this noise, and this is what makes differential signaling useful. Except that in order to work, there must be strict requirements observed during PCB design and layout, like the signal traces needing to have the same length and be physically close to each other, and many others. Sometimes it is not easy to fulfill all these requirements, a simple case to understand is when on chip A's pins, the positive pin is on the left and the negative is on the right, but on the chip B's pins (with which A tries to communicate), positive is on the right and negative on the left. The signals would need to cross, using vias and other ugly stuff that affects signal integrity (introduces impedance discontinuities which cause reflections, etc). So sometimes, board designers intentionally connect differential lanes the wrong way, and expect somebody else to invert that signal to recover useful data. This is where RX and TX polarity inversion comes in as a generic concept that applies to any high-speed serial protocol as long as it uses differential signaling. I've stopped two attempts to introduce more vendor-specific descriptions of this only in the past month: https://lore.kernel.org/linux-phy/20251110110536.2596490-1-horatiu.vultur@microchip.com/ https://lore.kernel.org/netdev/20251028000959.3kiac5kwo5pcl4ft@skbuf/ and in the kernel we already have merged: - "st,px_rx_pol_inv" - "st,pcie-tx-pol-inv" - "st,sata-tx-pol-inv" - "mediatek,pnswap" - "airoha,pnswap-rx" - "airoha,pnswap-tx" and maybe more. So it is pretty general. One additional element of complexity is introduced by the fact that for some protocols, receivers can automatically detect and correct for an inverted lane polarity (example: the PCIe LTSSM does this in the Polling.Configuration state; the USB 3.1 Link Layer Test Specification says that the detection and correction of the lane polarity inversion in SuperSpeed operation shall be enabled in Polling.RxEQ.). Whereas for other protocols (SGMII, SATA, 10GBase-R, etc etc), the polarity is all manual and there is no detection mechanism mandated by their respective standards. So why would one even describe rx-polarity and tx-polarity for protocols like PCIe, if it had to always be PHY_POL_AUTO? Related question: why would we define the polarity as an array per protocol? Isn't the physical PCB layout protocol-agnostic, and aren't we describing the same physical reality from the lens of different protocols? The answer to both questions is because multi-protocol PHYs exist (supporting e.g. USB2 and USB3, or SATA and PCIe, or PCIe and Ethernet over the same lane), one would need to manually set the polarity for SATA/Ethernet, while leaving it at auto for PCIe/USB 3.0+. I also investigated from another angle: what if polarity inversion in the PHY is one layer, and then the PCIe/USB3 LTSSM polarity detection is another layer on top? Then rx-polarity = <PHY_POL_AUTO> doesn't make sense, it can still be rx-polarity = <PHY_POL_NORMAL> or <PHY_POL_INVERT>, and the link training state machine figures things out on top of that. This would radically simplify the design, as the elimination of PHY_POL_AUTO inherently means that the need for a property array per protocol also goes away. I don't know how things are in the general case, but at least in the 10G and 28G Lynx SerDes blocks from NXP Layerscape devices, this isn't the case, and there's only a single level of RX polarity inversion: in the SerDes lane. In the case of PCIe, the controller is in charge of driving the RDAT_INV bit autonomously, and it is read-only to software. So the existence of this kind of SerDes lane proves the need for PHY_POL_AUTO to be a third state. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260111093940.975359-5-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-14dt-bindings: phy-common-props: ensure protocol-names are uniqueVladimir Oltean1-0/+1
Rob Herring points out that "The default for .*-names is the entries don't have to be unique.": https://lore.kernel.org/linux-phy/20251204155219.GA1533839-robh@kernel.org/ Let's use uniqueItems: true to make sure the schema enforces this. It doesn't make sense in this case to have duplicate properties for the same SerDes protocol. Note that this can only be done with the $defs + $ref pattern as established by the previous commit. When the tx-p2p-microvolt-names constraints were expressed directly under "properties", it would have been validated by the string-array meta-schema, which does not support the 'uniqueItems' keyword as can be seen below. properties:tx-p2p-microvolt-names: Additional properties are not allowed ('uniqueItems' was unexpected) from schema $id: http://devicetree.org/meta-schemas/string-array.yaml Suggested-by: Rob Herring <robh@kernel.org> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260111093940.975359-4-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-14dt-bindings: phy-common-props: create a reusable "protocol-names" definitionVladimir Oltean1-15/+19
Other properties also need to be defined per protocol than just tx-p2p-microvolt-names. Create a common definition to avoid copying a 55 line property. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260111093940.975359-3-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-14dt-bindings: phy: rename transmit-amplitude.yaml to phy-common-props.yamlVladimir Oltean1-4/+4
I would like to add more properties similar to tx-p2p-microvolt, and I don't think it makes sense to create one schema for each such property (transmit-amplitude.yaml, lane-polarity.yaml, transmit-equalization.yaml etc). Instead, let's rename to phy-common-props.yaml, which makes it a more adequate host schema for all the above properties. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260111093940.975359-2-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-14dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Add QMP UFS PHY compatiblePradeep P V K1-0/+4
Document QMP UFS PHY compatible for x1e80100 SoC. Use SM8550 as a fallback since x1e80100 is fully compatible with it. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com> Link: https://patch.msgid.link/20260106154207.1871487-2-pradeep.pragallapati@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-14dt-bindings: phy: qcom,m31-eusb2-phy: Document M31 eUSB2 PHY for KaanapaliRonak Raheja1-0/+1
Document M31 eUSB2 PHY for Kaanapali which handles the USB2 path. Use fallback to indicate the compatibility of the M31 eUSB2 PHY on the Kaanapali with that on the SM8750. Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com> Co-developed-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260108052459.1819970-3-krishna.kurapati@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-14dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add Kaanapali QMP PHYRonak Raheja1-26/+32
Document QMP combo PHY for Kaanapali. Use fallback to indicate the compatibility of the QMP PHY on the Kaanapali with that on the SM8750. Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com> Co-developed-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Link: https://patch.msgid.link/20260108052459.1819970-2-krishna.kurapati@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-14phy: cadence-torrent: Add PCIe + XAUI multilink configuration for 100MHz refclkSwapnil Jakhade1-7/+136
Add register sequences for PCIe + XAUI multilink configuration for 100MHz reference clock. The register sequences are fetched from a table by indexing entries based on unique 'keys' generated by the Bitwise OR defined below: REFCLK0_RATE | REFCLK1_RATE | LINK0_TYPE | LINK1_TYPE | SSC_TYPE As of now, LINK_TYPE is a 3-bit value corresponding to the PHY type. With the introduction of TYPE_XAUI, we need a 4-bit value to represent the LINK_TYPE as TYPE_XAUI has the numerical value 8. Hence, extend the LINKx_MASK macros to 4-bit masks. While at it, extend REFCLKx_MASK macros as well to 4-bit masks to support reference clock frequencies that will be added in the future. Adjust the 'LINKx_SHIFT' and the 'REFCLKx_SHIFT' macros to account for the aforementioned changes made to the masks. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> [s-vadapalli: elaborated on changes made to macros in the commit message] Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/20260112054636.108027-3-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-14dt-bindings: phy: Add PHY_TYPE_XAUI definitionSwapnil Jakhade1-0/+1
XAUI (eXtended Attachment Unit Interface) is a high-speed serial interface standard for 10 Gigabit Ethernet (10GbE). It uses four lanes with each lane operating at 3.125 Gbps (totaling 10 Gbps), to extend the XGMII interface across circuit boards, commonly used in backplanes for networking switches and high-performance computing. XAUI is defined as a standardized instantiation of XGMII Extender in the IEEE 802.3 specification. Add definition for XAUI PHY type. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> [s-vadapalli: added detailed description of XAUI in the commit message] Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260112054636.108027-2-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-14phy: qcom: qmp-combo: Add polarity inversion support for SAR2130PKrishna Kurapati1-0/+7
On SAR2130P QXR Platform, the CC Lines are inverted and the lane programming is to be done reverse compared to other targets. As per the HW specifics, Bit-2 of TYPEC_CTRL register indicates port select polarity. This bit is to be set for SAR2130P. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20251017203438.744197-1-krishna.kurapati@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-14phy: qcom-qmp-ufs: Add Milos supportLuca Weiss1-0/+96
Add the init sequence tables and config for the UFS QMP phy found in the Milos SoC. Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260112-milos-ufs-v2-4-d3ce4f61f030@fairphone.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-14dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: document the Milos QMP UFS PHYLuca Weiss1-0/+2
Document the QMP UFS PHY on the Milos SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://patch.msgid.link/20260112-milos-ufs-v2-3-d3ce4f61f030@fairphone.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-14phy: sun4i-usb: replace use of system_wq with system_percpu_wqMarco Crivellari1-7/+7
Currently if a user enqueues a work item using schedule_delayed_work() the used wq is "system_wq" (per-cpu wq) while queue_delayed_work() use WORK_CPU_UNBOUND (used when a cpu is not specified). The same applies to schedule_work() that is using system_wq and queue_work(), that makes use again of WORK_CPU_UNBOUND. This lack of consistency cannot be addressed without refactoring the API. This patch continues the effort to refactor worqueue APIs, which has begun with the change introducing new workqueues and a new alloc_workqueue flag: commit 128ea9f6ccfb ("workqueue: Add system_percpu_wq and system_dfl_wq") commit 930c2ea566af ("workqueue: Add new WQ_PERCPU flag") Replace system_wq with system_percpu_wq, keeping the same behavior. The old wq (system_wq) will be kept for a few release cycles. Suggested-by: Tejun Heo <tj@kernel.org> Signed-off-by: Marco Crivellari <marco.crivellari@suse.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251105152023.259813-1-marco.crivellari@suse.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-01phy: qcom: edp: Add Glymur platform supportAbel Vesa1-8/+219
The Qualcomm Glymur platform has the new v8 version of the eDP/DP PHY. So rework the driver to support this new version and add the platform specific configuration data. While at it, add the rest of the AUX_CFG reset values for the v4 and v5 platforms, which makes the handling of the platforms specific array cleaner, as they are single sized now. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20251224-phy-qcom-edp-add-glymur-support-v6-4-4fcba75a6fa9@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-01phy: qcom-qmp: qserdes-com: Add v8 DP-specific qserdes register offsetsAbel Vesa1-0/+52
Starting with Glymur, the PCIe and DP PHYs qserdes register offsets differ for the same version number. So in order to be able to differentiate between them, add these ones with DP prefix. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20251224-phy-qcom-edp-add-glymur-support-v6-3-4fcba75a6fa9@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-01phy: qcom: edp: Fix the DP_PHY_AUX_CFG registers countAbel Vesa1-1/+1
On all platforms supported by this driver, there are 13 DP_PHY_AUX_CFGx registers. This hasn't been an issue so far on currently supported platforms, because the init sequence never spanned beyond DP_PHY_AUX_CFG9. However, on the new upcoming Glymur platform, these are updated along with the rest of the init sequence. So update the size of the array holding the config to 13. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20251224-phy-qcom-edp-add-glymur-support-v6-2-4fcba75a6fa9@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-01dt-bindings: phy: Add DP PHY compatible for GlymurAbel Vesa1-0/+2
The Glymur platform is the first one to use the eDP PHY version 8. This makes it incompatible with any of the earlier platforms and therefore requires a dedicated compatible. So document it. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20251224-phy-qcom-edp-add-glymur-support-v6-1-4fcba75a6fa9@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-01phy: qcom: edp: Make the number of clocks flexibleAbel Vesa1-8/+8
On X Elite, the DP PHY needs another clock called ref, while all other platforms do not. The current X Elite devices supported upstream work fine without this clock, because the boot firmware leaves this clock enabled. But we should not rely on that. Also, even though this change breaks the ABI, it is needed in order to make the driver disables this clock along with the other ones, for a proper bring-down of the entire PHY. So in order to handle these clocks on different platforms, make the driver get all the clocks regardless of how many there are provided. Cc: stable@vger.kernel.org # v6.10 Fixes: db83c107dc29 ("phy: qcom: edp: Add v6 specific ops and X1E80100 platform support") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://patch.msgid.link/20251224-phy-qcom-edp-add-missing-refclk-v5-2-3f45d349b5ac@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-01dt-bindings: phy: qcom-edp: Add missing clock for X EliteAbel Vesa1-1/+27
On X Elite platform, the eDP PHY uses one more clock called ref. The current X Elite devices supported upstream work fine without this clock, because the boot firmware leaves this clock enabled. But we should not rely on that. Also, even though this change breaks the ABI, it is needed in order to make the driver disables this clock along with the other ones, for a proper bring-down of the entire PHY. So attach the this ref clock to the PHY. Cc: stable@vger.kernel.org # v6.10 Fixes: 5d5607861350 ("dt-bindings: phy: qcom-edp: Add X1E80100 PHY compatibles") Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://patch.msgid.link/20251224-phy-qcom-edp-add-missing-refclk-v5-1-3f45d349b5ac@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-01phy: qcom: qmp-pcie: Add support for Glymur PCIe Gen4x2 PHYAbel Vesa1-0/+19
Glymur platform has two Gen4 2-lanes controllers, the fourth and sixth instances. Add support for their PHYs. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://patch.msgid.link/20251224-phy-qcom-pcie-add-glymur-v3-2-57396145bc22@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-01dt-bindings: phy: sc8280xp-qmp-pcie: Document Glymur PCIe Gen4 2-lanes PHYAbel Vesa1-0/+3
The fourth and sixth PCIe instances on Glymur are both Gen4 2-lane PHY. So document the compatible. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20251224-phy-qcom-pcie-add-glymur-v3-1-57396145bc22@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-01phy: renesas: rcar-gen2: Simplify with scoped for each OF child loopKrzysztof Kozlowski1-3/+1
Use scoped for-each loop when iterating over device nodes to make code a bit simpler. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20251224124407.208354-6-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-01phy: core: Simplify with scoped for each OF child loopKrzysztof Kozlowski1-5/+2
Use scoped for-each loop when iterating over device nodes to make code a bit simpler. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20251224124407.208354-5-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-01phy: rockchip: usb: Simplify with scoped for each OF child loopKrzysztof Kozlowski1-5/+2
Use scoped for-each loop when iterating over device nodes to make code a bit simpler. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20251224124407.208354-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-01phy: spacemit: support K1 USB2.0 PHY controllerZe Huang5-0/+217
The SpacemiT K1 SoC includes three USB ports: - One USB2.0 OTG port - One USB2.0 host-only port - One USB3.0 port with an integrated USB2.0 DRD interface Each of these ports is connected to a USB2.0 PHY responsible for USB2 transmission. This commit adds support for the SpacemiT K1 USB2.0 PHY, which is compliant with the USB 2.0 specification and supports both 8-bit 60MHz and 16-bit 30MHz parallel interfaces. Signed-off-by: Ze Huang <huang.ze@linux.dev> Tested-by: Aurelien Jarno <aurelien@aurel32.net> Tested-by: Junzhong Pan <panjunzhong@linux.spacemit.com> Link: https://patch.msgid.link/20251017-k1-usb2phy-v6-2-7cf9ea2477a1@linux.dev Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-01dt-bindings: phy: spacemit: add K1 USB2 PHYZe Huang1-0/+40
Add support for USB2 PHY found on SpacemiT K1 SoC. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Ze Huang <huang.ze@linux.dev> Tested-by: Aurelien Jarno <aurelien@aurel32.net> Tested-by: Junzhong Pan <panjunzhong@linux.spacemit.com> Link: https://patch.msgid.link/20251017-k1-usb2phy-v6-1-7cf9ea2477a1@linux.dev Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-01phy: renesas: phy-rcar-gen2: fix typo in function name referenceJulia Lawall1-1/+1
Replace cmpxcgh by cmpxchg. Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251230141050.93856-1-Julia.Lawall@inria.fr Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-01phy: adjust function name referenceJulia Lawall1-1/+1
There is no function clk_bulk_prepare_disable. Refer instead to clk_bulk_disable_unprepare, which is called in the function defined just below. Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Reviewed-by: Daniel Golle <daniel@makrotopia.org> Link: https://patch.msgid.link/20251230140601.93474-1-Julia.Lawall@inria.fr Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-01phy: core: Reinstate pm_runtime_enabled() check in phy_pm_runtime_put()Geert Uytterhoeven1-0/+3
On Koelsch (R-Car M2-W), during boot and s2ram: phy phy-e6590100.usb-phy-controller.0: Runtime PM usage count underflow! While phy_pm_runtime_get{,_sync}() and phy_pm_runtime_put_sync() still contain pm_runtime_enabled() checks, the same check in phy_pm_runtime_put() was deemed redundant and removed, causing count underflows with PHY drivers like drivers/phy/renesas/phy-rcar-gen2.c that do not use Runtime PM yet, Fix this by reinstating the check. Fixes: caad07ae07e3fb17 ("phy: core: Discard pm_runtime_put() return values") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/3ca9f8166d21685bfbf97535da30172f74822130.1767107014.git.geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-29phy: Kconfig: spacemit: add COMMON_CLK dependencyAlex Elder1-0/+1
The SpacemiT PCIe PHY driver depends on the common clock framework. Not specifying that led to a failure when doing a COMPILE_TEST build for the SPARC architecture. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202512251903.sTVZgg6c-lkp@intel.com/ Signed-off-by: Alex Elder <elder@riscstar.com> Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Link: https://patch.msgid.link/20251226173228.2020411-1-elder@riscstar.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-24phy: ti: phy-j721e-wiz: convert from round_rate() to determine_rate()Brian Masney1-4/+7
The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney <bmasney@redhat.com> Link: https://patch.msgid.link/20251212-phy-clk-round-rate-v3-9-beae3962f767@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-24phy: rockchip: phy-rockchip-samsung-hdptx: convert from round_rate() to ↵Brian Masney1-6/+9
determine_rate() The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Brian Masney <bmasney@redhat.com> Link: https://patch.msgid.link/20251212-phy-clk-round-rate-v3-8-beae3962f767@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-24phy: rockchip: phy-rockchip-inno-hdmi: convert from round_rate() to ↵Brian Masney1-14/+16
determine_rate() The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Brian Masney <bmasney@redhat.com> Link: https://patch.msgid.link/20251212-phy-clk-round-rate-v3-7-beae3962f767@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-24phy: mediatek: phy-mtk-mipi-dsi-mt8183: convert from round_rate() to ↵Brian Masney1-4/+6
determine_rate() The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney <bmasney@redhat.com> Link: https://patch.msgid.link/20251212-phy-clk-round-rate-v3-6-beae3962f767@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-24phy: mediatek: phy-mtk-mipi-dsi-mt8173: convert from round_rate() to ↵Brian Masney1-4/+6
determine_rate() The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney <bmasney@redhat.com> Link: https://patch.msgid.link/20251212-phy-clk-round-rate-v3-5-beae3962f767@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-24phy: mediatek: phy-mtk-hdmi-mt8195: convert from round_rate() to ↵Brian Masney1-5/+5
determine_rate() The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Tested-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Signed-off-by: Brian Masney <bmasney@redhat.com> Link: https://patch.msgid.link/20251212-phy-clk-round-rate-v3-4-beae3962f767@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-24phy: mediatek: phy-mtk-hdmi-mt8173: convert from round_rate() to ↵Brian Masney1-8/+8
determine_rate() The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney <bmasney@redhat.com> Link: https://patch.msgid.link/20251212-phy-clk-round-rate-v3-3-beae3962f767@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-24phy: mediatek: phy-mtk-hdmi-mt2701: convert from round_rate() to ↵Brian Masney1-4/+4
determine_rate() The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney <bmasney@redhat.com> Link: https://patch.msgid.link/20251212-phy-clk-round-rate-v3-2-beae3962f767@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-24phy: freescale: phy-fsl-samsung-hdmi: convert from round_rate() to ↵Brian Masney1-5/+8
determine_rate() The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney <bmasney@redhat.com> Link: https://patch.msgid.link/20251212-phy-clk-round-rate-v3-1-beae3962f767@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-24phy: qualcomm: phy-qcom-eusb2-repeater: Add squelch detect param updateKrishna Kurapati1-0/+22
Add support for overriding Squelch Detect parameter. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20251219173108.2119296-3-krishna.kurapati@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-24dt-bindings: phy: qcom,snps-eusb2-repeater: Add squelch param updateKrishna Kurapati1-0/+8
Add squelch detect parameter update for synopsys eusb2 repeater. The values (indicated in basis-points) depict a percentage change with respect to the nominal value. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20251219173108.2119296-2-krishna.kurapati@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-24dt-bindings: phy: samsung,usb3-drd-phy: add power-domainsAndré Draszik1-0/+3
The USB phy can be part of a power domain, so we need to allow the relevant property 'power-domains'. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://patch.msgid.link/20251224-power-domains-dt-bindings-phy-samsung-ufs-phy-v2-2-581089639982@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-24dt-bindings: phy: samsung,ufs-phy: add power-domainsAndré Draszik1-0/+3
The UFS phy can be part of a power domain, so we need to allow the relevant property 'power-domains'. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://patch.msgid.link/20251224-power-domains-dt-bindings-phy-samsung-ufs-phy-v2-1-581089639982@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: rockchip: naneng-combphy: use existing DT property check for rk3528Chukun Pan1-7/+5
The naneng-combphy driver already has DT property checks for "rockchip,enable-ssc" and "rockchip,ext-refclk", use it for the rk3528_combphy_cfg. Also aligned the indentation of the rk3528_combphy_grfcfgs parameters (using tabs). Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Reviewed-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://patch.msgid.link/20250910122000.951100-1-amadeus@jmu.edu.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: qualcomm: qmp-combo: Add DP offsets and settings for Glymur platformsAbel Vesa3-4/+428
Starting with Glymur, the PCIe and DP PHYs qserdes register offsets differ for the same version number. So in order to be able to differentiate between them, add these ones with DP prefix. Add the necessary PHY setting tables for enabling the DP path within the QMP subsystem. Introduced some new callbacks for v8 specific sequences, such as for clock configurations based on the different link speeds. Wesley Cheng added some updated settings from the hardware programming guides on existing PHY tables and clock settings. Co-developed-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://patch.msgid.link/20251209-linux-next-12825-v8-9-42133596bda0@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: qualcomm: qmp-combo: Update QMP PHY with Glymur settingsWesley Cheng7-0/+1212
For SuperSpeed USB to work properly, there is a set of HW settings that need to be programmed into the USB blocks within the QMP PHY. Ensure that these settings follow the latest settings mentioned in the HW programming guide. The QMP USB PHY on Glymur is a USB43 based PHY that will have some new ways to define certain registers, such as the replacement of TXA/RXA and TXB/RXB register sets. This was replaced with the LALB register set. There are also some PHY init updates to modify the PCS MISC register space. Without these, the QMP PHY PLL locking fails. Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://patch.msgid.link/20251209-linux-next-12825-v8-8-42133596bda0@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2026-05-01 14:25:58 +0300