summaryrefslogtreecommitdiff
AgeCommit message (Expand)AuthorFilesLines
2021-01-29drm/i915: Nuke not needed members of dram_infoJosé Roberto de Souza3-42/+12
2021-01-28drm/i915: Fix the MST PBN divider calculationImre Deak1-1/+3
2021-01-28drm/dp/mst: Export drm_dp_get_vc_payload_bw()Imre Deak2-6/+19
2021-01-28drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MSTSean Paul1-11/+1
2021-01-28drm/i915/display: Prevent double YUV range correction on HDR planesAndres Calderon Jaramillo2-55/+12
2021-01-28drm/i915: WARN if plane src coords are too bigVille Syrjälä2-0/+11
2021-01-27drm/i915/display/vrr: Skip the VRR HW state readout on DSI transcoderManasi Navare1-1/+1
2021-01-26drm/i915/adl_s: Update combo PHY master/slave relationshipsMatt Roper1-2/+9
2021-01-26drm/i915/adl_s: Add vbt port and aux channel settings for adlsAditya Swarup1-11/+46
2021-01-26drm/i915/adl_s: Add adl-s ddc pin mappingAditya Swarup3-2/+35
2021-01-26drm/i915/adl_s: Initialize display for ADL-SAditya Swarup1-1/+7
2021-01-26drm/i915/adl_s: Configure Port clock registers for ADL-SAditya Swarup3-24/+72
2021-01-26drm/i915/adl_s: Configure DPLL for ADL-SAditya Swarup2-6/+54
2021-01-26drm/i915/adl_s: Add PHYs for Alderlake SAnusha Srivatsa2-6/+11
2021-01-26drm/i915/adl_s: Add Interrupt SupportAnusha Srivatsa1-2/+1
2021-01-26drm/i915/adl_s: Add PCH supportAnusha Srivatsa2-1/+10
2021-01-26x86/gpu: Add Alderlake-S stolen memory supportCaz Yokoyama1-0/+1
2021-01-26drm/i915: Do a bit more initial readout for dbufVille Syrjälä2-6/+48
2021-01-26drm/i915: Encapsulate dbuf state handling harderVille Syrjälä5-271/+140
2021-01-26drm/i915: Extract intel_crtc_dbuf_weights()Ville Syrjälä1-55/+88
2021-01-26drm/i915: Add pipe ddb entries into the dbuf stateVille Syrjälä2-11/+12
2021-01-26drm/i915: Introduce skl_ddb_entry_for_slices()Ville Syrjälä1-37/+18
2021-01-26drm/i915: Introduce intel_dbuf_slice_size()Ville Syrjälä2-16/+21
2021-01-26drm/i915: Pass the crtc to skl_compute_dbuf_slices()Ville Syrjälä1-12/+10
2021-01-26drm/i915: Extract intel_crtc_ddb_weight()Ville Syrjälä1-18/+27
2021-01-26drm/i915: Fix vblank evasion with vrrVille Syrjälä1-1/+4
2021-01-26drm/i915: Fix vblank timestamps with VRRVille Syrjälä4-6/+34
2021-01-26drm/i915: Add vrr state dumpVille Syrjälä1-0/+7
2021-01-26drm/i915/display: Helpers for VRR vblank min and max startVille Syrjälä2-0/+38
2021-01-26drm/i915/display: Add HW state readout for VRRManasi Navare3-0/+26
2021-01-26drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP SinkManasi Navare2-1/+20
2021-01-26drm/i915/display/vrr: Disable VRR in modeset disable pathManasi Navare3-0/+16
2021-01-26drm/i915/display/vrr: Send VRR push to flip the frameManasi Navare3-0/+18
2021-01-26drm/i915/display/vrr: Configure and enable VRR in modeset enableManasi Navare3-0/+28
2021-01-26drm/i915: Rename VRR_CTL reg fieldsVille Syrjälä1-7/+7
2021-01-26drm/i915/display: VRR + DRRS cannot be enabled togetherVille Syrjälä1-0/+3
2021-01-26drm/i915/display/dp: Do not enable PSR if VRR is enabledManasi Navare1-0/+7
2021-01-26drm/i915/display/dp: Compute VRR state in atomic_checkManasi Navare5-0/+95
2021-01-26drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp()Ville Syrjälä1-14/+24
2021-01-26drm/i915: Extract intel_mode_vblank_start()Ville Syrjälä1-3/+11
2021-01-26drm/i915: Store framestart_delay in dev_privVille Syrjälä2-11/+14
2021-01-26drm/i915/display/dp: Attach and set drm connector VRR propertyAditya Swarup2-2/+10
2021-01-26drm/i915/display/vrr: Create VRR file and add VRR capability checkManasi Navare4-0/+49
2021-01-22drm/i915/tgl: Add Clear Color support for TGL Render DecompressionRadhakrishna Sripada4-5/+116
2021-01-22drm/i915/gem: Add a helper to read data from a GEM object pageImre Deak2-0/+73
2021-01-22drm/framebuffer: Format modifier for Intel Gen 12 render compression with Cle...Radhakrishna Sripada1-0/+19
2021-01-22drm/i915/hdcp: Fix uninitialized symbolAnshuman Gupta1-10/+10
2021-01-22drm/i915/hdcp: Fix WARN_ON(data->k > INTEL_NUM_PIPES)Anshuman Gupta1-0/+2
2021-01-22drm/i915/dp: Don't use DPCD backlights that need PWM enable/disableLyude Paul1-1/+6
2021-01-21drm/i915: Unify the sanity checks for the buf trans tablesVille Syrjälä1-13/+10
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-15 21:53:19 +0300