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AgeCommit message (Expand)AuthorFilesLines
2012-08-09drm/i915: add parentheses around PIXCLK_GATE definitionsPaulo Zanoni1-2/+2
2012-08-09drm/i915: reindent Haswell register definitionsPaulo Zanoni1-99/+85
2012-08-09drm/i915: completely reset the value of DDI_FUNC_CTLPaulo Zanoni1-6/+1
2012-08-09drm/i915: correctly set the DDI_FUNC_CTL bpc fieldPaulo Zanoni2-6/+21
2012-08-09drm/i915: set the DDI sync polarity bitsPaulo Zanoni2-0/+8
2012-08-09drm/i915: fix pipe DDI mode selectPaulo Zanoni2-1/+7
2012-08-09drm/i915: dump the device infoDaniel Vetter3-23/+48
2012-08-09drm/i915: fixup desired rps frequency computationDaniel Vetter1-6/+6
2012-08-08drm/i915: Add I915_GEM_PARAM_HAS_SEMAPHORESChris Wilson2-0/+4
2012-08-08drm/i915: Only apply the SNB pipe control w/a to gen6Chris Wilson1-13/+20
2012-07-27drm/i915: prevent possible pin leak on error pathEugeni Dodonov1-1/+1
2012-07-26drm/i915: rip out sanitize_pm againDaniel Vetter4-39/+5
2012-07-26drm/i915: Only set the down rps limit when at the loweset frequencyDaniel Vetter1-18/+25
2012-07-26drm/i915: Export ability of changing cache levels to userspaceChris Wilson4-4/+78
2012-07-26drm/i915: Segregate memory domains in the GTT using coloringChris Wilson4-14/+128
2012-07-25drm/i915: Expand DPF support to HaswellBen Widawsky1-1/+1
2012-07-25drm/i915: Macro to determine DPF supportBen Widawsky4-5/+7
2012-07-25drm/i915: Add contexts for HSWBen Widawsky2-1/+12
2012-07-25drm/i915: Avoid concurrent access when marking the device as idle/busyChris Wilson6-138/+41
2012-07-25drm/i915: Split i915_gem_flush_ring() into seperate invalidate/flush funcsChris Wilson5-37/+44
2012-07-25drm/i915: Clear the pending_gpu_fenced_access flag at the start of execbufferChris Wilson1-0/+1
2012-07-25drm/i915: Replace the complex flushing logic with simple invalidate/flush allDaniel Vetter1-202/+20
2012-07-25drm/i915: Remove the explicit flush of the GPU write domainChris Wilson1-34/+0
2012-07-25drm/i915: Remove explicit flush from i915_gem_object_flush_fence()Chris Wilson1-14/+2
2012-07-25drm/i915: Remove the per-ring write listChris Wilson5-70/+3
2012-07-25drm/i915: Remove the defunct flushing listChris Wilson4-91/+14
2012-07-25drm/i915: Replace the pending_gpu_write flag with an explicit seqnoChris Wilson5-43/+51
2012-07-25drm/i915: Remove assertion over write domain after i915_gem_object_sync()Chris Wilson1-1/+1
2012-07-25drm/i915: Allow late allocation of request for i915_add_request()Chris Wilson3-36/+21
2012-07-25drm/i915: add inte_crt->adpa_regDaniel Vetter2-7/+17
2012-07-25drm/i915: create VLV_DSIPLAY_BASE #defineDaniel Vetter2-1/+3
2012-07-25drm/i915: Return a mask of the active rings in the high word of busy_ioctlChris Wilson2-1/+9
2012-07-25drm/i915: add register read IOCTLBen Widawsky5-1/+57
2012-07-25drm/i915: Reserve ioctl numbers for set/get_cachingDaniel Vetter1-0/+15
2012-07-25drm/i915: Support for ns2501-DVOThomas Richter5-2/+596
2012-07-25drm/i915: add port field to struct intel_dp and use itPaulo Zanoni3-34/+34
2012-07-25drm/i915: move common code to intel_dp_set_link_trainPaulo Zanoni1-34/+51
2012-07-25drm/i915: add port parameter to intel_hdmi_initDaniel Vetter4-38/+22
2012-07-25drm/i915: simplify possible_clones computationDaniel Vetter9-61/+35
2012-07-25drm/i915: group ADPA #defines togetherDaniel Vetter1-25/+22
2012-07-25drm/i915: Cleanup context switching through do_switch()Chris Wilson1-31/+26
2012-07-25drm/i915: Move DP structs to shared locationShobhit Kumar2-32/+32
2012-07-25drm/i915: unbreak lastclose for failed driver initDaniel Vetter1-1/+7
2012-07-25drm/i915: Set the context before setting up regs for the context.Eric Anholt1-4/+4
2012-07-25drm/i915: constify mode in crtc_mode_fixupDaniel Vetter1-1/+1
2012-07-25drm/i915/lvds: ditch ->prepare special caseDaniel Vetter1-7/+1
2012-07-25drm/i915: dereferencing an error pointerDan Carpenter1-1/+3
2012-07-25drm/i915: fix invalid reference handling of the default ctx objChris Wilson1-14/+4
2012-07-25drm/i915: Add -EIO to the list of known errors for __wait_seqnoChris Wilson1-0/+1
2012-07-25drm/i915: Flush the context object from the CPU caches upon switchingChris Wilson1-0/+11
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