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2020-12-03ARM: dts: at91: sama5d2: map securam as deviceClaudiu Beznea1-0/+1
Due to strobe signal not being propagated from CPU to securam the securam needs to be mapped as device or strongly ordered memory to work properly. Otherwise, updating to one offset may affect the adjacent locations in securam. Fixes: d4ce5f44d4409 ("ARM: dts: at91: sama5d2: Add securam node") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/1606903025-14197-3-git-send-email-claudiu.beznea@microchip.com
2020-12-03ARM: dts: at91: sam9x60ek: remove bypass propertyClaudiu Beznea1-4/+0
atmel,osc-bypass property sets the bit 1 at main oscillator register. On SAM9X60 this bit is not valid according to datasheet (chapter 28.16.9 PMC Clock Generator Main Oscillator Register). Fixes: 1e5f532c2737 ("ARM: dts: at91: sam9x60: add device tree for soc and board") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Marco Cardellini <marco.cardellini@microchip.com> Link: https://lore.kernel.org/r/1606903025-14197-2-git-send-email-claudiu.beznea@microchip.com
2020-12-03ARM: dts: exynos: Reduce assigned-clocks entries for SPI0 on Artik5 boardMarek Szyprowski1-5/+2
Commit 2024b130b0c8 ("ARM: dts: exynos: Add Ethernet to Artik 5 board") added ethernet chip on SPI0 bus and the whole bunch of assigned clock entries to ensure proper clock rates and topology. Limit the assigned clock parents only to the direct clocks of the SPI0 device and assume that MPLL clock is already properly configured. The applied clock topology was incorrect as some clocks between were missing, what resulted in the following warning: clk: failed to reparent div_mpll_pre to mout_mpll: -22 Fixes: 2024b130b0c8 ("ARM: dts: exynos: Add Ethernet to Artik 5 board") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/20201202122029.22198-1-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-12-02ARM: dts: s3c6410: correct SMDK6410 board compatibleKrzysztof Kozlowski1-1/+1
The SMDK6410 DTS was incorrectly called mini6410, probably copy-paste from FriendlyARM Mini6410 board. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20201117201106.128813-4-krzk@kernel.org
2020-12-02ARM: dts: s3c24xx: add SMDK2416 board compatibleKrzysztof Kozlowski1-1/+1
Add a compatible for SMDK2416 board next to the SoC compatible. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20201117201106.128813-3-krzk@kernel.org
2020-12-02dt-bindings: arm: samsung: document S3C6410-based boards bindingKrzysztof Kozlowski1-0/+7
Add bindings for the FriendlyARM Mini6410 and Samsung SMDK6410 boards. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20201117201106.128813-2-krzk@kernel.org
2020-12-02dt-bindings: arm: samsung: document SMDK2416 board bindingKrzysztof Kozlowski1-0/+6
Add binding for the SMDK2416 board. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20201117201106.128813-1-krzk@kernel.org
2020-12-01ARM: dts: at91: remove deprecated ADC propertiesAlexandre Belloni6-154/+0
atmel,adc-res, atmel,adc-res-names and the trigger nodes are not parsed by the driver anymore and the information is now defined in the driver data. Also remove the leftover #address-cells and #size-cells that were used when the trigger nodes had a unit-address. Finally, the default is already to use the highest resoution. Remove atmel,adc-use-res from the SoC dtsi. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/20201128222818.1910764-11-alexandre.belloni@bootlin.com
2020-12-01ARM: dts: at91: at91sam9rl: fix ADC triggersAlexandre Belloni1-8/+11
The triggers for the ADC were taken from at91sam9260 dtsi but are not correct. Fixes: a4c1d6c75822 ("ARM: at91/dt: sam9rl: add lcd, adc, usb gadget and pwm support") Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20201128222818.1910764-10-alexandre.belloni@bootlin.com
2020-12-01ARM: dts: at91: sama5d3: use proper ADC compatibleAlexandre Belloni1-1/+1
The ADC is different from the at91sam9x5 ADC. Not only it doesn't have the same resolution but it even has only one and the LOWRES bit doesn't exist. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/20201128222818.1910764-9-alexandre.belloni@bootlin.com
2020-12-01ARM: dts: at91: kizbox: switch to new pwm-atmel-tcb bindingAlexandre Belloni1-15/+30
Switch to the new pwm-atmel-tcb binding that avoid wasting TCB channels. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Cc: Antoine Aubert <a.aubert@overkiz.com> Link: https://lore.kernel.org/r/20201030183658.1007395-5-alexandre.belloni@bootlin.com
2020-12-01arm64: dts: imx8mm-beacon-som: Assign PMIC clockAdam Ford1-0/+4
The PMIC throws an errors because the clock isn't assigned to it. Fix this by assigning the clocks info. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-12-01arm64: dts: imx8mm-beacon-som: Configure RTC aliasesAdam Ford1-1/+6
On the i.MX8MM Beacon SOM, there is an RTC chip which is fed power from the baseboard during power off. The SNVS RTC integrated into the SoC is not fed power. Depending on the order the modules are loaded, this can be a problem if the external RTC isn't rtc0. Make the alias for rtc0 point to the external RTC all the time and rtc1 point to the SVNS in order to correctly hold date/time over a power-cycle. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-12-01ARM: dts: imx28: Fix label name for L2 switchLukasz Majewski1-1/+1
The 'eth_switch' name has been misspelled in the imx28.dtsi file, so this change fixes it. Signed-off-by: Lukasz Majewski <lukma@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-12-01arm64: dts: imx8mn: Add node for SPDIFAdam Ford1-0/+24
The i.MX8M Nano can support SPDIF which is compatible to the IP used on the i.MX35. Add the node. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-12-01arm64: dts: imx8mn: Add support for micfilAdam Ford1-0/+19
The i.MX8M Nano has supports the MICFIL digital interface. It's a 16-bit audio signal from a PDM microphone bitstream. The driver is already in the kernel, but the node is missing. Add the micfil node. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-12-01arm64: dts: imx8mn: Add SAI nodesAdam Ford1-0/+72
The i.MX8M Nano has several SAI nodes available to it. Enable them. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-12-01arm64: dts: imx8mn: Enable Asynchronous Sample Rate ConverterAdam Ford1-0/+28
The driver exists for the Enhanced Asynchronous Sample Rate Converter (EASRC) Controller, but there isn't a device tree entry for it. On the vendor kernel, they put this on a spba-bus for SDMA support. Add the node for the spba-bus with the easrc node inside. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-12-01arm64: dts: ls1028a: make the eMMC and SD card controllers use fixed indicesVladimir Oltean3-0/+6
As the boot order in the kernel continues to change, sometimes it may happen that the eSDHC controller mmc@2150000 (the one for eMMC) gets probed before the one at mmc@2140000 (for external SD cards). The effect is that the eMMC controller gets the /dev/mmcblk0 name, and the SD card gets /dev/mmcblk1. Since the introduction of this SoC, that has never happened in practice, even though it was never guaranteed in theory. Setting "root=/dev/mmcblk0p2" in /proc/cmdline has always caused the kernel to use the second partition from the SD card as the rootfs. The NXP development boards are typically shipped with either - LSDK, which uses "root=UUID=", or - OpenIL, which uses "root=/dev/mmcblkNp2" So for OpenIL, let's preserve that old behavior by adding some aliases which create naming consistency (for LSDK it doesn't matter): - the SD card controller uses /dev/mmcblk0 - the eMMC controller uses /dev/mmcblk1 For the Kontron SL28 boards, Michael Walle says that they are shipped with "root=UUID=" already, so the probing order doesn't matter, but it is more natural to him for /dev/mmcblk0 to be the eMMC, so let's do it the other way around there. The aliases are parsed by mmc_alloc_host() in drivers/mmc/core/host.c. Cc: Ashish Kumar <Ashish.Kumar@nxp.com> Cc: Yangbo Lu <yangbo.lu@nxp.com> Cc: Michael Walle <michael@walle.cc> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Michael Walle <michael@walle.cc> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-12-01ARM: dts: add Protonic WD3 boardOleksij Rempel2-0/+554
Protonic WD3 is a proof of concept platform for tractor e-cockpit applications Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-12-01dt-bindings: arm: fsl: add Protonic WD3 boardOleksij Rempel1-0/+1
Add Protonic Holland WD3 iMX6qp based board Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-12-01dt-bindings: vendor-prefixes: add "virtual" prefixOleksij Rempel1-0/+2
"virtual" is used for vendor-less "devices". For example for the GPIO based MDIO bus "virtual,mdio-gpio". This patch is needed to fix the checkpatch warning for the Protonic WD3 board. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-12-01ARM: dts: imx6qdl-kontron-samx6i: increase i2c-frequencyMarco Felsch1-3/+3
Set it to max. allowed 375kHz for faster transfers. The limit is given by the erratum [1]. [1] https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-12-01arm64: dts: meson-sm1: fix typo in opp tableDongjin Kim1-1/+1
The freqency 1512000000 should be 1500000000. Signed-off-by: Dongjin Kim <tobetter@gmail.com> Fixes: 3d9e76483049 ("arm64: dts: meson-sm1-sei610: enable DVFS") Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201130060320.GA30098@anyang-linuxfactory-or-kr
2020-12-01arm64: dts: meson: add KHAMSIN IR remote node to SML5442TWChristian Hewitt1-0/+4
Set the IR keymap to the KHAMSIN remote shipped with the SML5442TW. Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201126050440.6273-1-christianshewitt@gmail.com
2020-12-01arm64: dts: meson: update the Khadas VIM3/3L LED bindingsChristian Hewitt1-4/+7
Update the VIM3/3L common dtsi to use the new function/color bindings. Suggested-by: Artem Lapkin <art@khadas.com> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201125052914.4092-1-christianshewitt@gmail.com
2020-12-01arm64: dts: meson: fix spi-max-frequency on Khadas VIM2Artem Lapkin1-1/+1
The max frequency for the w25q32 (VIM v1.2) and w25q128 (VIM v1.4) spifc chip should be 104Mhz not 30MHz. Fixes: b8b74dda3908 ("ARM64: dts: meson-gxm: Add support for Khadas VIM2") Signed-off-by: Artem Lapkin <art@khadas.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201125024001.19036-1-christianshewitt@gmail.com
2020-12-01arm64: dts: meson: add rtc aliases to meson-khadas-vim3.dtsiChristian Hewitt1-1/+3
Tweak the node name to make it aliasable, then add aliases for the on-board RTC chip and meson-vrtc timer so they probe as rtc0 and rtc1 respectively. before: VIM3:~ # dmesg | grep rtc [ 3.622530] meson-vrtc ff8000a8.rtc: registered as rtc0 [ 3.622574] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:03 UTC (3) [ 3.646936] rtc-hym8563 0-0051: no valid clock/calendar values available [ 3.647125] rtc-hym8563 0-0051: registered as rtc1 [ 3.852382] rtc-hym8563 0-0051: no valid clock/calendar values available after: VIM3:~ # dmesg | grep rtc [ 3.583735] meson-vrtc ff8000a8.rtc: registered as rtc1 [ 3.633888] rtc-hym8563 0-0051: no valid clock/calendar values available [ 3.634120] rtc-hym8563 0-0051: registered as rtc0 [ 3.635250] rtc-hym8563 0-0051: no valid clock/calendar values available [ 3.635267] rtc-hym8563 0-0051: hctosys: unable to read the hardware clock [ 3.852632] rtc-hym8563 0-0051: no valid clock/calendar values available Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201124145338.17137-1-christianshewitt@gmail.com
2020-12-01arm64: dts: meson: Add capacity-dmips-mhz attributes to GXMChristian Hewitt1-0/+20
GXM (S912) is a big-little design with CPUs 0-3 clocked at 1.5GHz and CPUs 4-7 at 1.0GHz. Adding capacity-dmips-mhz attributes allows the scheduler to factor the different clock speeds into capacity calculations and prefer the higher-clocked cluster to improve overall performance. This was inspired by the similar change for G12B [0] boards. The diference here is that all cores are A53's so the same dmips-mhz value is used. VIM2:~ # cat /sys/devices/system/cpu/cpu*/cpufreq/scaling_cur_freq 1512000 1512000 1512000 1512000 1000000 1000000 1000000 1000000 before: VIM2:~ # cat /sys/devices/system/cpu/cpu*/cpu_capacity 1024 1024 1024 1024 1024 1024 1024 1024 after: VIM2:~ # cat /sys/devices/system/cpu/cpu*/cpu_capacity 1024 1024 1024 1024 677 677 677 677 The after value matches my table-napkin calculation: (1000000 / 1512000 = 0.661) * 1024 = 677 [0] https://github.com/torvalds/linux/commit/6eeaf4d2452ec8b1ece58776812140734fc2e088 Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201124121740.25704-1-christianshewitt@gmail.com
2020-12-01arm64: dts: meson-axg-s400: enable PCIe M.2 Key E slotsNeil Armstrong1-0/+10
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201120153229.3920123-5-narmstrong@baylibre.com
2020-12-01arm64: dts: meson-axg: add PCIe nodesNeil Armstrong1-0/+61
This adds the nodes for the : - AXG PCIe PHY, using the shared analog PCIe/MIPI DSI PHY - 2x AXG PCIe controllers Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201120153229.3920123-4-narmstrong@baylibre.com
2020-12-01arm64: dts: meson-axg: add MIPI DSI PHY nodesNeil Armstrong1-0/+19
This adds the nodes for : - MIPI DSI+PCIe analog phy - MIPI D-PHY Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201120152131.3918814-3-narmstrong@baylibre.com
2020-12-01arm64: dts: meson-axg: add PWRC nodeNeil Armstrong1-0/+42
This adds the power controller PWRC node and the corresponding ethernet power domain. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201120152131.3918814-2-narmstrong@baylibre.com
2020-12-01arm64: dts: meson: enable rtc node on Khadas VIM1/VIM2 boardsChristian Hewitt2-4/+2
Enable the rtc node on VIM1/VIM2 boards so users can simply attach a power cell and use the on-board RTC without modifying the device-tree. Cold boot with no cell attached is gracefully handled: VIM2:~ # dmesg | grep rtc [ 7.716150] rtc-hym8563 1-0051: no valid clock/calendar values available [ 7.716957] rtc-hym8563 1-0051: registered as rtc0 [ 7.729850] rtc-hym8563 1-0051: no valid clock/calendar values available [ 7.729877] rtc-hym8563 1-0051: hctosys: unable to read the hardware clock [ 8.126768] rtc-hym8563 1-0051: no valid clock/calendar values available Warm boot (and any boot with cell attached) recalls stored values resulting in consistently faster (re)boot times: VIM2:~ # dmesg | grep rtc [ 7.441671] rtc-hym8563 1-0051: registered as rtc0 [ 7.442663] rtc-hym8563 1-0051: setting system clock to 2020-11-16T05:49:59 UTC (1605505799) Suggested-by: Artem Lapkin <art@khadas.com> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201116064147.12062-1-christianshewitt@gmail.com
2020-12-01Merge tag 'clk-meson-v5.11-headers-1' of git://github.com/BayLibre/clk-meson ↵Kevin Hilman1-0/+25
into v5.11/dt64-deps Amlogic clock headers updates for v5.11 * Add axg's video clocks * tag 'clk-meson-v5.11-headers-1' of git://github.com/BayLibre/clk-meson: dt-bindings: clk: axg-clkc: add MIPI DSI Host clock binding dt-bindings: clk: axg-clkc: add Video Clocks
2020-11-30arm64: dts: qcom: c630: Define eDP bridge and panelBjorn Andersson1-0/+100
The Lenovo Yoga C630 drives the Boe NV133FHM-N61 eDP display from DSI using a TI SN65DSI86 bridge chip on I2C 10. Define the bridge and eDP panel and enable the display blocks. Tested-by: Steev Klimaszewski <steev@kali.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20201128034231.89750-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-30arm64: dts: qcom: c630: Fix pinctrl pins propertiesBjorn Andersson1-4/+4
The "pins" property takes an array of pin _names_, not pin numbers. Fix this. Tested-by: Steev Klimaszewski <steev@kali.org> Fixes: 44acee207844 ("arm64: dts: qcom: Add Lenovo Yoga C630") Link: https://lore.kernel.org/r/20201130170028.319798-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-30arm64: dts: qcom: c630: Polish i2c-hid devicesBjorn Andersson1-13/+18
The numbering of the i2c busses differs from ACPI and a number of typos was made in the original patch. Further more the irq flags for the various resources was not correct and i2c3 only has one of the two client devices active in any one device. Also label the various devices, for easier comparison with the ACPI tables. Tested-by: Steev Klimaszewski <steev@kali.org> Fixes: 44acee207844 ("arm64: dts: qcom: Add Lenovo Yoga C630") Link: https://lore.kernel.org/r/20201130165924.319708-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-30arm64: dts: qcom: sc7180: Add lpass cpu node for I2S driverAjit Pandey1-0/+69
Add the I2S controller node to sc7180 dtsi. Add pinmux for primary and secondary I2S. Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Ajit Pandey <ajitp@codeaurora.org> Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Signed-off-by: V Sujith Kumar Reddy <vsujithk@codeaurora.org> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> Link: https://lore.kernel.org/r/1600450426-14063-1-git-send-email-srivasam@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-30arm64: dts: ipq6018: Add the QPIC peripheral nodesKathiravan T2-0/+57
Add the QPIC BAM and QPIC NAND controller support and enable the same in board DTS file. Co-developed-by: Anusha Canchi Ramachandra Rao <anusharao@codeaurora.org> Signed-off-by: Anusha Canchi Ramachandra Rao <anusharao@codeaurora.org> Signed-off-by: Kathiravan T <kathirav@codeaurora.org> Link: https://lore.kernel.org/r/1606734105-12414-2-git-send-email-kathirav@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-30arm64: dts: sdm845: Add interconnect properties for QUPGeorgi Djakov1-0/+160
Add the interconnects DT property to describe the ports for GENI QUPs on the sdm845 platform. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Link: https://lore.kernel.org/r/20201105135211.7160-3-georgi.djakov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-30interconnect: qcom: sdm845: Add the missing nodes for QUPGeorgi Djakov1-0/+3
The QUP nodes are currently defined just as entries in the topology, but they are not referenced by any of the NoCs. Let's fix this and "attach" them to their NoCs, so that the QUP drivers are able to use them as path endpoints and scale their bandwidth. This is based on the information from the downstream msm-4.9 kernel. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Link: https://lore.kernel.org/r/20201105135211.7160-2-georgi.djakov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-30dt-bindings: interconnect: sdm845: Add IDs for the QUP portsGeorgi Djakov1-0/+2
The QUP ports exist in the topology, but are not exposed as an endpoints in DT. Fix this by creating IDs and attach them to their NoCs, so that the various QUP drivers (i2c/spi/uart etc.) are able to request their interconnect paths and scale their bandwidth. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Link: https://lore.kernel.org/r/20201105135211.7160-1-georgi.djakov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-30arm64: dts: qcom: c630: Expose LID eventsBjorn Andersson1-0/+39
The LID state can be read from GPIO 124 and the "tablet mode" from GPIO 95, expose these to the system using gpio-keys and mark the falling edge of the LID state as a wakeup-source - to wake the system from suspend. Tested-by: Steev Klimaszewski <steev@kali.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20201125060838.165576-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-30arm64: dts: qcom: c630: Re-enable apps_smmuBjorn Andersson1-5/+0
Re-enable the apps_smmu now that the arm-smmu driver supports stream mapping handoff from firmware. Tested-by: Steev Klimaszewski <steev@kali.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20201124184414.380796-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-30dts: qcom: sdm845: Add dt entries to support crypto engine.Thara Gopinath1-0/+30
Add crypto engine (CE) and CE BAM related nodes and definitions to "sdm845.dtsi". Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org> Link: https://lore.kernel.org/r/20201119155233.3974286-6-thara.gopinath@linaro.org [bjorn: Replaced RPMH_CE_CLK constant, for now] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-30arm64: dts: rockchip: add isp and sensors for ScarletEddie Cai1-0/+74
Enable ISP and camera sensor ov2685 and ov5695 for Scarlet Chromebook Verified with: make ARCH=arm64 dtbs_check Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com> Signed-off-by: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Helen Koike <helen.koike@collabora.com> Reviewed-by: Tomasz Figa <tfiga@chromium.org> Link: https://lore.kernel.org/r/20201020193850.1460644-10-helen.koike@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-11-30arm64: dts: rockchip: add isp0 node for rk3399Shunqian Zheng1-0/+26
RK3399 has two ISPs, but only isp0 was tested. Add isp0 node in rk3399 dtsi Verified with: make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/media/rockchip-isp1.yaml Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Signed-off-by: Helen Koike <helen.koike@collabora.com> Link: https://lore.kernel.org/r/20201020193850.1460644-9-helen.koike@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-11-30arm64: dts: armada-3720-turris-mox: add 3W power capability to SFP cageMarek Behún1-0/+1
Add maximum-power-milliwatt = 3000 to SFP node of Turris MOX. Signed-off-by: Marek Behún <kabel@kernel.org> Fixes: 7109d817db2e ("arm64: dts: marvell: add DTS for Turris Mox") Cc: Gregory CLEMENT <gregory.clement@bootlin.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-11-30arm64: dts: marvell: keep SMMU disabled by default for Armada 7040 and 8040Tomasz Nowicki2-8/+0
FW has to configure devices' StreamIDs so that SMMU is able to lookup context and do proper translation later on. For Armada 7040 & 8040 and publicly available FW, most of the devices are configured properly, but some like ap_sdhci0, PCIe, NIC still remain unassigned which results in SMMU faults about unmatched StreamID (assuming ARM_SMMU_DISABLE_BYPASS_BY_DEFAUL=y). Since there is dependency on custom FW let SMMU be disabled by default. People who still willing to use SMMU need to enable manually and use ARM_SMMU_DISABLE_BYPASS_BY_DEFAUL=n (or via kernel command line) with extra caution. Fixes: 83a3545d9c37 ("arm64: dts: marvell: add SMMU support") Cc: <stable@vger.kernel.org> # 5.9+ Signed-off-by: Tomasz Nowicki <tn@semihalf.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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