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2016-02-25clk: shmobile: check for failureSudip Mukherjee1-1/+5
We were not checking the return from devm_add_action() which can fail. Start using the helper devm_add_action_or_reset() and return directly as we know that the cleanup has been done by this helper. Signed-off-by: Sudip Mukherjee <sudip.mukherjee@codethink.co.uk> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-23clk: samsung: exynos5433: Fix typos in *_ISP_MPWM clock namesSylwester Nawrocki2-4/+4
This fixes "MPWM" -> "WPWM" typo in 3 *ISP_MWPM clock definitions. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-02-23clk: Update some outdated commentsStephen Boyd1-3/+3
__clk_init() was renamed to __clk_core_init() but these comments weren't updated. Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-23Revert "clk: avoid circular clock topology"Stephen Boyd1-40/+0
This reverts commit 858d5881564026cbc4e6f5e25ae878a27df5d4c9. Joachim reports that this commit breaks lpc18xx boot. This is because the hardware has circular clk topology where PLLs can feed into dividers and the same dividers can feed into the PLLs. The hardware is designed this way so that you can choose to put the divider before the PLL or after the PLL depending on what you configure to be the parent of the divider and what you configure to be the parent of the PLL. So let's drop this patch for now because we have hardware that actually has loops. A future patch could check for circular parents when we change parents and fail the switch, but that's probably best left to some debugging Kconfig option so that we don't suffer the sanity checking cost all the time. Reported-by: Joachim Eastwood <manabian@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-23clk: socfpga: allow for multiple parents on Arria10 periph clocksDinh Nguyen2-9/+4
There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can have multiple parents. Fix up the __socfpga_periph_init() to call of_clk_parent_fill() that will return the appropriate number of parents. Also, update __socfpga_gate_init() to call of_clk_parent_fill() helper function. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-23clk: ti: dpll: convert DPLL support code to use clk_hw instead of clk ptrsTero Kristo6-30/+54
Convert DPLL support code to use clk_hw pointers for reference and bypass clocks. This allows us to use clk_hw_* APIs for accessing any required parameters for these clocks, avoiding some locking problems at least with DPLL enable code; this used clk_get_rate which uses mutex but isn't good under clk_enable / clk_disable. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-23Merge branch 'clk-fixes' into clk-nextStephen Boyd1-1/+2
* clk-fixes: clk: ti: omap3+: dpll: use non-locking version of clk_get_rate
2016-02-23clk: qcom: msm8960: fix ce3_core clk enable registerSrinivas Kandagatla1-1/+1
This patch corrects the enable register offset which is actually 0x36cc instead of 0x36c4 Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-23clk: ti: omap3+: dpll: use non-locking version of clk_get_rateTero Kristo1-1/+2
As the code in this file is being executed within irq context in some cases, we must avoid the clk_get_rate which uses mutex internally. Switch the code to use clk_hw_get_rate instead which is non-locking. This fixes an issue where PM runtime will hang the system if enabled with a serial console before a suspend-resume cycle. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com> Fixes: a53ad8ef3dcc ("clk: ti: Convert to clk_hw based provider APIs") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-22Merge branch 'clk-samsung' into clk-nextMichael Turquette2-7/+15
2016-02-22clk: samsung: Don't build ARMv8 clock drivers on ARMv7Krzysztof Kozlowski2-3/+11
Currently the Exynos5433 (ARMv8 SoC) clock driver depends on ARCH_EXYNOS so it is built also on ARMv7. This does not bring any kind of benefit. There won't be a single kernel image for ARMv7 and ARMv8 SoCs (like multi_v7 for ARMv7). Instead build clock drivers only for respective SoC's architecture. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-02-22clk: sunxi: Improve divs_clk error handling and reportingAndre Przywara1-3/+15
We catch errors in the base clock registration, failure to ioremap and failures in the final of_clk_add_provider() call. Also we unmap the registers when we need to rollback. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-22clk: sunxi: improve divider_clk error handling and reportingAndre Przywara1-3/+33
We now report a failing ioremap, failing output names parsing, failures in table registration and in the final step. Also there was a bug where clk_register_divider_table() would return an ERR_PTR value instead of NULL, which we were checking for. We now implement proper rollback in case of an error. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-22clk: sunxi: improve mux_clk error handling and reportingAndre Przywara1-6/+15
We now catch and report a failing ioremap, also a failure in the final step of the clock registration is now handled and reported. Also warnings are turned into errors. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-19Merge branch 'clk-shmobile-for-v4.6' of ↵Michael Turquette3-1/+238
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
2016-02-19Merge branch 'clk-fixes' into clk-nextStephen Boyd12-14/+1
* clk-fixes: clk: gpio: Really allow an optional clock= DT property Revert "clk: qcom: Specify LE device endianness"
2016-02-19clk: gpio: Really allow an optional clock= DT propertyStephen Boyd1-1/+1
We mis-merged the original patch from Russell here and so the patch went almost all the way, except that we still failed to probe when there wasn't a clocks property in the DT node. Allow that case by making a negative value from of_clk_get_parent_count() into "no parents", like the original patch did. Fixes: 7ed88aa2efa5 ("clk: fix clk-gpio.c with optional clock= DT property") Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-18clk: imx: correct pwm7 clock name in driver for i.MX6ULAnatolij Gustschin1-1/+1
Don't capitalize p in the pwm7 clock name. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-02-18clk: shmobile: r8a7795: Add INTC-EX clockMagnus Damm1-0/+1
Add the "intc-ex" clock to the r8a7795 CPG MSSR driver. According to information from the hardware team the INTC-EX parent clock is CP. The next data sheet version will include this information. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-18clk: Make of_clk_get_from_provider() available to modulesAndrew F. Davis1-0/+1
Export symbol of_clk_get_from_provider so it can be used in loadable kernel modules Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-02-17clk: samsung: Enable COMPILE_TEST for Samsung clocksKrzysztof Kozlowski1-4/+4
Enable the COMPILE_TEST to get build coverage of some of Samsung clock controller drivers. Still some of them will be built only if appropriate SoC is chosen (like SOC_EXYNOS4415 or ARCH_S3C64XX). Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Andi Shyti <andi.shyti@samsung.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-02-16Merge branch 'clk-bcm2835' into clk-nextMichael Turquette1-16/+9
2016-02-16clk: bcm2835: Reuse CLK_DIVIDER_MAX_AT_ZERO for recalc_rate()Eric Anholt1-11/+2
We were rolling this ourselves, but clk-divider can do it now. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-02-16clk: bcm2835: Fix setting of PLL divider clock ratesEric Anholt1-5/+7
Our dividers weren't being set successfully because CM_PASSWORD wasn't included in the register write. It looks easier to just compute the divider to write ourselves than to update clk-divider for the ability to OR in some arbitrary bits on write. Fixes about half of the video modes on my HDMI monitor (everything except 720x400). Cc: stable@vger.kernel.org Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-02-16clk: sunxi: Fix sun8i-a23-apb0-clk divider flagsChen-Yu Tsai1-1/+1
The APB0 clock on A23 is a zero-based divider, not a power-of-two based divider. Note that this patch does not apply cleanly to kernels before 4.5-rc1, which added CLK_OF_DECLARE support to this driver. Fixes: 57a1fbf28424 ("clk: sunxi: Add A23 APB0 divider clock support") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-16clk: shmobile: cpg-mssr: Update serial port clock in exampleGeert Uytterhoeven1-1/+1
Cfr. commit a9ec81f4ed5c05db ("serial: sh-sci: Drop the interface clock"). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Michael Turquette <mturquette@baylibre.com>
2016-02-15Merge tag 'v4.6-rockchip-clk1' of ↵Michael Turquette9-154/+159
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Introduction of a factor type and a variant containing a gate to be able to also declare factor clocks in their correct place in the clock tree instead of having to register factor clocks in the init callback separately. And as always some more clock-ids and non-regression fixes for mistakes introduced in past kernel releases.
2016-02-14clk: imx: Add clock support for imx6qpBai Ping2-28/+120
most of the clock tree structures on i.MX6 Quad Plus are same as on i.MX6Q. there still some differences between these two SOCs. compared to the i.XM6Q, the differents of clocks on i.MX6QP is mainly on: 1. New clock gate added to support the PRE and PRG modules 2. 24MHz OSC clock option added to the UART, IPG, ECSPI, and CAN clock roots. 3. MMDC channel 1 clock gate is now controllable. 4. clock gating added to the LDB_DIx_IPU clocks on i.MX6QP 5. EMI clock root divider fix 6. other updates fo CSCMRx, CSCDRx and CS2CDR registers. detailed infomation, please refer to the i.MX6QP RM. Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-02-13Revert "clk: qcom: Specify LE device endianness"Stephen Boyd11-13/+0
This reverts commit 329cabcecf94d8d7821e729dda284ba9dec44c87. The commit that caused us to specify LE device endianness here, 29bb45f25ff3 (regmap-mmio: Use native endianness for read/write, 2015-10-29), has been reverted in mainline so now when we specify LE it actively breaks big endian kernels because the byte swapping in regmap-mmio is incorrect. Let's revert this change because it will 1) fix the big endian kernels and 2) be redundant to specify LE because that will become the default soon. Cc: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@baylibre.com> Cc: Mark Brown <broonie@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-12clk: qcom: mmcc8974: Use gdscs .parent and remove genpd callsRajendra Nayak1-13/+2
With gdsc driver capable of handling hierarchical power domains, specify oxili_gdsc as parent of oxilicx_gdsc. Remove all direct calls to genpd from the mmcc clock driver. The adding and removing of subdomains is now handled from within the gdsc driver. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-12clk: qcom: gdsc: Add mmcc gdscs for msm8996 familyRajendra Nayak2-0/+174
Add all gdsc data which are part of mmcc on msm8996 family Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-12clk: qcom: gdsc: Add GDSCs in msm8996 GCCRajendra Nayak2-0/+103
Add all data for the GDSCs which are part of msm8996 GCC block Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-12clk: qcom: gdsc: Add support for votable gdscsRajendra Nayak2-7/+26
Some gdscs might be controlled via voting registers and might not really disable when the kernel intends to disable them (due to other votes keeping them enabled) Mark these gdscs with a flag for we do not check/wait on a disable status for these gdscs within the kernel disable callback. Also at boot, if these GDSCs are found to be ON, we make sure we vote for them before we inform the genpd framework about their status. If genpd gets no users, it then disables (removes the vote) them as part of genpd_poweroff_unused() Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-12clk: qcom: gdsc: Add support for gdscs with gds hw controllerRajendra Nayak2-17/+29
Some gdsc power domains can have a gds_hw_controller block inside to help ensure all slave devices within the power domain are idle before the gdsc is actually switched off. This is mainly useful in power domains which host a MMU, in which case its necessary to make sure there are no outstanding MMU operations or pending bus transactions before the power domain is turned off. In gdscs with gds_hw_controller block, its necessary to check the gds_hw_ctrl status bits instead of the ones in gdscr, to determine the state of the powerdomain. While at it, also move away from using jiffies and use ktime APIs instead for busy looping on status bits. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-12clk: qcom: gdsc: Add support for hierarchical power domainsRajendra Nayak3-10/+50
Some qcom SoCs' can have hierarchical power domains. Let the gdsc structs specify the parents (if any) and the driver add genpd subdomains for them. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-11clk: sunxi: Remove clk_register_clkdev callsMaxime Ripard8-19/+4
Now that our protection code doesn't use the global name lookup anymore, we can remove the clkdev registrations. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-11clk: sunxi: Remove old probe and protection codeMaxime Ripard1-108/+0
Now that we don't have any user left for the old registration code, we can remove it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-11clk: sunxi: convert current clocks registration to CLK_OF_DECLAREMaxime Ripard1-17/+133
The current clock registration and protection code has a few drawbacks, the two main ones being that we create a lot of orphans clock in the registration phase, which will be troublesome when we will start being less relaxed about them. The protection code also relies on clkdev, which we don't really use but for this particular case. Fix both at the same time by moving everyone to the CLK_OF_DECLARE that will probe our clock tree in the right and thus avoid orphans, and by protecting directly the clock returned by our registration function. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-11clk: sunxi: Make clocks setup functions take const pointerMaxime Ripard1-3/+3
All the data structure that we pass to the clocks setup functions are declared const, while our setup functions expects a regular pointer. This was hidden by the fact that we cast a void * pointer back to these structures, which made it go unnoticed. Fix the functions prototype. Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-11clk: sunxi: Make clocks setup functions return their clockMaxime Ripard1-7/+10
The clocks registration code in clk-sunxi was most of the time not returning the struct clk (or struct clk array) that was registered, preventing the users of such functions to manipulate it, for example to protect it. Make them return it so that we can start using it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-10clk: lpc32xx: add HCLK PLL output configurationSylvain Lemieux2-5/+2
This patch add the support to setup the HCLK PLL output using the "assigned-clock-rates" parameter in the device tree. If the option is not use, the clock setup by the kickstart and/or bootloader remain unchanged. The previous kernel version did not change the clock frequency output setup by the kickstart and/or bootloader; this version always setup the clock frequency output to 208MHz. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-10Merge branch 'clk-fixes' into clk-nextStephen Boyd1-0/+3
* clk-fixes: clk: versatile: mask VCO bits before writing
2016-02-10clk: versatile: mask VCO bits before writingLinus Walleij1-0/+3
The Versatile syscon ICST driver OR:s the bits into place but forgets to mask the previous value, making the code only work if the register is zero or giving haphazard results. Mask the 19 bits used by the Versatile syscon interface register. Regression caused and now fixed by yours truly. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-clk@vger.kernel.org Fixes: 179c8fb3c2a6 ("clk: versatile-icst: convert to use regmap") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-10clk: lpc32xx: do not register clock "0"Sylvain Lemieux1-2/+2
The following errors are display in the console during the power-on: [ 0.000000] lpc32xx_usb_clk_init: failed to register (null) clock: -12 [ 0.000000] lpc32xx_clk_init: failed to register (null) clock: -12 There is no need to register clock "0"; the first clock used is 1; Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Acked-by: Vladimir Zapolskiy <vz@mleia.com> [sboyd@codeaurora.org: s/prepare/register/] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-09clk: fix __clk_init_parent() for single parent clocksMasahiro Yamada1-1/+1
Before commit b3d192d5121f ("clk: simplify __clk_init_parent()"), __clk_init_parent() called .get_parent() only for multi-parent clocks. That commit changed the behavior to call .get_parent() if available even for single-parent clocks and root clocks. It turned out a problem because there are some single-parent clocks that implement .get_parent() callback and return non-zero index. The SOCFPGA clock is the case; the commit broke the SOCFPGA boards. To keep the original behavior, invoke .get_parent() only when num_parents is greater than 1. Fixes: b3d192d5121f ("clk: simplify __clk_init_parent()") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-09clk: qcom: common: check for failureSudip Mukherjee1-6/+11
We were not checking the return from devm_add_action() which can fail. Start using the helper and devm_add_action_or_reset() and return directly as we know that the cleanup has been done by this helper. Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-09devm: add helper devm_add_action_or_reset()Sudip Mukherjee1-0/+12
Add a helper function devm_add_action_or_reset() which will internally call devm_add_action(). But if devm_add_action() fails then it will execute the action mentioned and return the error code. Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-09clk: meson: Fix meson_clk_register_clks() signature type mismatchAndreas Färber1-1/+1
As preparation for arm64 based mesongxbb, which pulls in this code once enabling ARCH_MESON, fix a size_t vs. unsigned int type mismatch. The loop uses a local unsigned int variable, so adopt that type, matching the header. Fixes: 7a29a869434e ("clk: meson: Add support for Meson clock controller") Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-09clk: socfpga: fix __init annotationArnd Bergmann1-1/+1
clang found a bug with the __socfpga_pll_init definition: drivers/clk/socfpga/clk-pll-a10.c:77:15: error: '__section__' attribute only applies to functions and global variables This moves the __init annotation to the right place so the function actually gets discarded. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-09drivers/clk/Kconfig: Move the TI CDCE chips close togetherMike Looijmans1-8/+8
There are two TI CDCE clock chips in this file. Move them close together so they're easier to find. No functional change, just cosmetic. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> [sboyd@codeaurora.org: Alphabetize] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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