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2016-02-02clk: remove unused first argument of __clk_init()Masahiro Yamada1-3/+2
The "struct device *dev" is not used at all in this function. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-30Merge branch 'clk-fixes' into clk-nextStephen Boyd3-27/+27
* clk-fixes: clk: rockchip: rk3368: fix some clock gates clk: rockchip: rk3036: rename emac ext source clock clk: rockchip: rk3036: fix the div offset for emac clock clk: rockchip: rk3036: fix uarts clock error clk: rockchip: rk3036: fix the FLAGs for clock mux
2016-01-30Merge tag 'v4.5-rockchip-clkfixes1' of ↵Stephen Boyd3-27/+27
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes Pull rockchip fixes from Heiko Stuebner: Fixes for wrong register offsets in both rk3036 and rk3368. Also rename the external input for the emac on rk3036, which should still be ok to do, as that binding was only introduced during this merge-window. * tag 'v4.5-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: rk3368: fix some clock gates clk: rockchip: rk3036: rename emac ext source clock clk: rockchip: rk3036: fix the div offset for emac clock clk: rockchip: rk3036: fix uarts clock error clk: rockchip: rk3036: fix the FLAGs for clock mux
2016-01-30clk: st: avoid uninitialized variable useArnd Bergmann1-2/+6
My previous patch fixed some warnings about printing a couple of variables that are always uninitialized in quadfs_pll_fs660c32_set_rate(), but I now got a warning that only shows up in some configurations (i.e. without gcc -Os) about the params.ndiv being used uninitialized in the error case: drivers/clk/st/clkgen-fsyn.c: In function 'quadfs_pll_fs660c32_set_rate': drivers/clk/st/clkgen-fsyn.c:584:75: warning: 'params.ndiv' may be used uninitialized in this function [-Wmaybe-uninitialized] drivers/clk/st/clkgen-fsyn.c:574:16: note: 'params.ndiv' was declared here This changes the error handling so we bail for invalid arguments rather than continuing with uninitialized data. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-30clk: axi-clkgen: Remove sometimes impossible checkStephen Boyd1-4/+1
The size of unsigned long on 64-bit architectures is equal to the size of u64, so this check is impossible there. This throws off static checkers: drivers/clk/clk-axi-clkgen.c:331 axi_clkgen_recalc_rate() warn: impossible condition '(tmp > (~0)) => (0-u64max > u64max)' Let's change this code to use min_t() instead so that we get the same effect on architectures where sizeof(unsigned long) doesn't equal sizeof(u64). Cc: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-30clk: axi-clkgen: Add multi-parent supportLars-Peter Clausen2-7/+38
The clock generator has two clock inputs that can be used as the reference clock. Add support for switching between them at runtime. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-30clk: axi-clkgen: Remove version 1 supportLars-Peter Clausen1-121/+4
Version 1 of the axi-clkgen core has not been used in new designs for over two years now. This is a soft peripheral used in FPGAs and anybody who has updated their kernel to the latest version will also have updated the bitstream containing the clock generator. So it should be safe to drop support for this now. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-30clk: palmas: fix a possible NULL dereferenceLABBE Corentin1-3/+3
of_match_device could return NULL, and so cause a NULL pointer dereference later. Even if the probability of this case is very low, fixing it made static analyzers happy. Solving this with of_device_get_match_data made also code simplier. Reported-by: coverity (CID 1324137) Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-30clk: palmas: constify the palmas_clks_of_match_data structureLABBE Corentin1-6/+6
The palmas_clks_of_match_data structures are never modified. This patch constify them. Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-30clk: optimize the divider walk in clk_divider_bestdiv()Masahiro Yamada1-3/+2
Because _next_div() returns a valid divider, there is no need to consult _is_valid_div() for the validity of the divider in every iteration. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-30clk: vt8500: fix sign of possible PLL valuesAndrzej Hajda1-3/+6
With unsigned values underflow in loops can occur resulting in theoretically infinite loops. The problem has been detected using proposed semantic patch scripts/coccinelle/tests/unsigned_lesser_than_zero.cocci [1]. [1]: http://permalink.gmane.org/gmane.linux.kernel/2038576 Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-30clk: add clk_unregister_fixed_rate()Masahiro Yamada2-1/+14
Allow to unregister fixed rate clock. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-30clk: add clk_unregister_fixed_factor()Masahiro Yamada2-0/+14
Allow to unregister fixed factor clock. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-30clk:gcc-msm8916: add missing mss_q6_bimc_axi clockSrinivas Kandagatla2-0/+19
This clock is required for loading the qdsp firmware. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-30Merge branch 'clk-iproc' into clk-nextStephen Boyd5-16/+139
* clk-iproc: clk: iproc: Remove __init from header clk: iproc: Add support for Cygnus audio clocks Documentation: dt-bindings: Add DT bindings for Cygnus audio clock
2016-01-30clk: iproc: Remove __init from headerRay Jui1-11/+11
Remove __init macro from all function prototypes in clk-iproc.h Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-30clk: iproc: Add support for Cygnus audio clocksSimran Rai4-5/+122
This patch adds support for Broadcom Cygnus audio PLL and leaf clocks Signed-off-by: Simran Rai <ssimran@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-30Documentation: dt-bindings: Add DT bindings for Cygnus audio clockSimran Rai1-0/+6
This patch adds audio clock device tree binding documentation to an existing Cygnus clock DT bindings document. Signed-off-by: Simran Rai <ssimran@broadcom.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Lori Hikichi <lhikichi@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-30clk: Move vendor's Kconfig into CCF menu sectionJames Liao3-6/+4
Move all vendor's Kconfig into CCF menu section to prevent new drivers putting their Kconfig files in a wrong place. Some Kconfigs need to be modified at the same time to avoid build warnings. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> [sboyd@codeaurora.org: Fix typos in commit message] Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-30clk: mediatek: Fix memory leak on clock init failJames Liao1-2/+4
mtk_clk_register_composite() may leak memory due to some error handling path don't free all allocated memory. This patch free all pointers that may allocate memory before error return. And it's safe because kfree() can handle NULL pointers. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: move the common clock's to_clk_*(_hw) macros to clk-provider.hGeliang Tang25-51/+33
to_clk_*(_hw) macros have been repeatedly defined in many places. This patch moves all the to_clk_*(_hw) definitions in the common clock framework to public header clk-provider.h, and drop the local definitions. Signed-off-by: Geliang Tang <geliangtang@163.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: xgene: Remove return from void functionStephen Boyd1-1/+1
This function doesn't return anything because it's void. Drop the return statement. Cc: Loc Ho <lho@apm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: xgene: Add SoC and PMD PLL clocks with v2 hardwareLoc Ho1-37/+66
Add X-Gene SoC and PMD PLL clocks support for v2 hardware. X-Gene SoC v2 and above use an slightly different SoC and PMD PLL hardware logic. Signed-off-by: Loc Ho <lho@apm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29Documentation: Update APM X-Gene clock binding for v2 hardwareLoc Ho1-0/+2
Update APM X-Gene clock binding documentation for SoC and PCP PLL for v2 hardware. Signed-off-by: Loc Ho <lho@apm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: s2mps11: remove redundant codeAndi Shyti1-20/+16
The definition of s2mps11_name is meant to resolve the name of a given clock. Remove it because the clocks have the same name we can get it directly from the s2mps11_clks_init structure. While in the probe function the s2mps11_clks is used only to iterate through the s2mps11_clks. The naming itself brings confusion and the readability does not improve much. Signed-off-by: Andi Shyti <andi.shyti@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: s2mps11: remove redundant static variables declarationAndi Shyti1-9/+10
The clk_table and clk_data are declared static. The clk_table contains the three clock data structures belonging to the s2mps11 driver. In the probe function it gets stored into clk_data. Remove clk_table and refer directly to clk_data. clk_data, itself, is also declared static. Declare locally it and allocate it inside the probe function, as it is not used anywhere else. Signed-off-by: Andi Shyti <andi.shyti@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: s2mps11: allocate only one structure for clock initAndi Shyti1-44/+7
The driver allocates three structures, s2mpsxx_clk_init, for three different clock types (s2mps11, s2mps13 and s2mps14). They are quite similar but they differ only by the name. Only one of these structures is used, while the others lie unused in the memory. The clock's name, though, is not such a meaningful information and by assigning the same name to the initial data we can avoid over allocation. The common name chosen will be s2mps11, coherently with the device driver name, instead of the clock device. Therefore, remove the structures associated to s2mps13 and s2mps14 and use only the one referred to s2mps11 for all kind of clocks. Signed-off-by: Andi Shyti <andi.shyti@samsung.com> Suggested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: s2mps11: merge two for loops in oneAndi Shyti1-6/+0
The driver already loops once, there is no reason to loop again for a different purpose. Merge the second loop into the first. Signed-off-by: Andi Shyti <andi.shyti@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk-divider: make sure read-only dividers do not write to their registerHeiko Stuebner4-3/+15
Commit e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1") removed the special ops struct for read-only clocks and instead opted to handle them inside the regular ops. On the rk3368 this results in breakage as aclkm now gets set a value. While it is the same divider value, the A53 core still doesn't like it, which can result in the cpu ending up in a hang. The reason being that "ACLKENMasserts one clock cycle before the rising edge of ACLKM" and the clock should only be touched when STANDBYWFIL2 is asserted. To fix this, reintroduce the read-only ops but do include the round_rate callback. That way no writes that may be unsafe are done to the divider register in any case. The Rockchip use of the clk_divider_ops is adapted to this split again, as is the nxp, lpc18xx-ccu driver that was included since the original commit. On lpc18xx-ccu the divider seems to always be read-only so only uses the new ops now. Fixes: e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1") Reported-by: Zhang Qing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: tango4: rename ARCH_TANGOX to ARCH_TANGOMarc Gonzalez1-1/+1
Requested by arm-soc maintainer Kevin Hilman in v9 review. http://article.gmane.org/gmane.linux.ports.arm.kernel/456331 Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: scpi: Fix checking return value of platform_device_register_simple()Axel Lin1-1/+1
platform_device_register_simple() returns ERR_PTR on error. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: mvebu: Mark ioremapped memory as __iomemStephen Boyd1-1/+1
Silence the following sparse warning drivers/clk/mvebu/dove-divider.c:252:14: warning: incorrect type in assignment (different address spaces) drivers/clk/mvebu/dove-divider.c:252:14: expected void *base drivers/clk/mvebu/dove-divider.c:252:14: got void [noderef] <asn:2>* drivers/clk/mvebu/dove-divider.c:256:13: warning: incorrect type in argument 2 (different address spaces) drivers/clk/mvebu/dove-divider.c:256:13: expected void [noderef] <asn:2>*base drivers/clk/mvebu/dove-divider.c:256:13: got void *base drivers/clk/mvebu/dove-divider.c:257:25: warning: incorrect type in argument 1 (different address spaces) drivers/clk/mvebu/dove-divider.c:257:25: expected void volatile [noderef] <asn:2>*iomem_cookie drivers/clk/mvebu/dove-divider.c:257:25: got void *base Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: sunxi: rewrite sun8i-a23-mbus-clk using the simpler composite clkChen-Yu Tsai1-45/+76
sun8i-a23-mbus-clk used sunxi's factors clk, which is nice for very complicated clocks, but is not really needed here. Convert sun8i-a23-mbus-clk to use clk_composite, as it is a gate + mux + divider. This makes the code easier to understand. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-29clk: sunxi: rewrite sun6i-ar100 using factors clkChen-Yu Tsai1-174/+61
sun6i's AR100 clock is a classic factors clk case: AR100 = ((parent mux) >> p) / (m + 1) Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-29clk: sunxi: rewrite sun6i-a31-ahb1-clk using factors clk with custom recalcChen-Yu Tsai1-208/+83
The factors clk implementation has been extended to support custom recalc callbacks to support clocks that use one factor for certain parents only, like a pre-divider. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-29clk: sunxi: factors: Drop round_rate from clk opsChen-Yu Tsai1-16/+0
The common clock framework requires either determine_rate or round_rate to be implemented. We use determine_rate so we can pass the parent index to the get_factors callback. This cannot be done easily with round_rate, so just drop it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-29clk: sunxi: factors: Support custom formulasChen-Yu Tsai2-2/+32
Some clocks cannot be modelled using the standard factors clk formula, such as clocks with special pre-dividers on one parent, or clocks with all power-of-two dividers. Add support for a custom .recalc callback for factors clk. Also pass the current parent index to the .get_factor and .recalc callbacks. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-29clk: rockchip: Allow sclk_i2s0 and i2s0_frac to change their parents rate on ↵Alexander Kochetkov1-2/+2
rk3188 Allow sclk_i2s0 and i2s0_frac to change their parents rate as that the upstream dividers are purely there to feed sclk_i2s0 Tested on radxarock-lite. Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-28clk: rockchip: fix wrong mmc phase shift for rk3228Shawn Lin1-3/+3
mmc sample shift is 0 for rk3228 refer to user manaul. So it's broken if we enable mmc tuning for rk3228. Fixes: 307a2e9ac ("clk: rockchip: add clock controller for rk3228") Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-27clk: sunxi: factors: Consolidate get_factors parameters into a structChen-Yu Tsai6-219/+155
The .get_factors callback of factors_clk has 6 parameters. To extend factors_clk in any way that requires adding parameters to .get_factors would make that list even longer, not to mention changing all the function declarations. Do this once now and consolidate all the parameters into a struct. Also drop the space before function pointer arguments, since checkpatch complains. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-27clk: sunxi: factors: Add unregister functionChen-Yu Tsai2-0/+30
sunxi's factors clk did not have an unregister function. This means multiple structs were leaked whenever a factors clk was unregistered. Add an unregister function for it. Also keep pointers to the mux and gate structs so they can be freed. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-27clk: sunxi: factors: Add clk cleanup in sunxi_factors_register() error pathChen-Yu Tsai1-15/+29
sunxi_factors_register() does not check for failures or cleanup after clk_register_composite() or other clk-related calls. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-27clk: sunxi: factors: Make struct clk_factors_config table constChen-Yu Tsai5-17/+17
struct clk_factors_config contains shifts/widths for the factors of the factors clk. This is used to read out the factors from the register value. In no case is it written to, so make it const. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-26clk: rockchip: add hclk_cpubus to the list of rk3188 critical clocksAlexander Kochetkov1-0/+1
hclk_cpubus needs to keep running because it is needed for devices like the rom, i2s0 or spdif to be accessible via cpu. Without that all accesses to devices (readl/writel) return wrong data. So add it to the list of critical clocks. Fixes: 78eaf6095cc763c ("clk: rockchip: disable unused clocks") Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Cc: stable@vger.kernel.org # 4.1.x- Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-26clk: rockchip: add tsadc clock on rk3066Paweł Jarosz1-1/+1
Set clock id for sclk_tsadc gating clock of tsadc in rk3066 Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-26Merge branch 'v4.6-shared/clkids' into v4.6-clk/nextHeiko Stuebner1-0/+1
2016-01-26clk: rockchip: Add new id for rk3066 tsadc clockPaweł Jarosz1-0/+1
This patch adds new id for the sclk supplying the tsadc on rk3066 socs. Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-25clk: rockchip: fix usbphy-related clocksHeiko Stuebner3-20/+9
The otgphy clocks really only drive the phy blocks. These in turn contain plls that then generate the 480m clocks the clock controller uses to supply some other clocks like uart0, gpu or the video-codec. So fix this structure to actually respect that hirarchy and removed that usb480m fixed-rate clock working as a placeholder till now, as this wouldn't even work if the supplying phy gets turned off while its pll-output gets used elsewhere. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Douglas Anderson <dianders@chromium.org> Acked-by: Michael Turquette <mturquette@baylibre.com>
2016-01-25clk: tegra: Remove improper flags for lock_enableRhyland Klein1-28/+14
Most PLL's don't actually have LOCK_ENABLE bits. However, most PLL's also had that flag set, which meant that the clk code was trying to enable locks, and inadvertantly flipping bits in other fields. For PLLM, ensure the correct register is used for the misc_register. PLL_MISC0 contains the EN_LCKDET bit which should be used for enabling the lock, and PLLM_MISC1 shouldn't be used at all. Lastly, remove some of the settings which would point to the EN_LCKDET bits for some PLLs. There is no need to enable the locks, and that is done as part of the set_defaults logic already. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-01-25clk: tegra: Fix divider on VI_I2CRhyland Klein1-1/+1
VI-I2C has 16 bits available for its divider. Switch the divider width to 16 instead of 8 so correct rates can be set. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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