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2019-06-22drm/amdgpu/mes10.1: implement ucode CPU buffer destructionJack Xiao1-0/+6
It implements the CPU buffer destruction of ucode. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu/mes10.1: load mes firmware file to CPU bufferJack Xiao1-0/+43
It requests MES firmware binary and uploads to CPU buffer. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu/mes10.1: add mes firmware info fieldsJack Xiao1-0/+16
The newly added fields is to store mes firmware related information. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu/ucode: add mes firmware file supportJack Xiao1-0/+15
The newly added firmware struct is for mes firmware file. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu/ucode: add the definitions of MES ucode and ucode dataJack Xiao1-0/+2
MES requires two seperate firmwares: ucode and ucode data. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu/sdma5: incorrect variable type for gpu addressJack Xiao1-1/+2
Incorrect programming with 64bit gpu address assignment for 32bit variable. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu/sdma5: fix a sdma potential hang in VK_Examples testtiancyin1-1/+2
[why] When page fault happens, it could lead to sdma hang is RESP_MODE = 0 for non-PRT case. [how] Setting SDMAx_UTCL1_CNTL.RESP_MODE to 0b011 to avoid SDMA halt. Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: tiancyin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: remove uvd_gated/vce_gated from smu_power_context (v2)Hawking Zhang1-10/+4
It's not needed for navi. v2: remove unused variable (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu/nv: set vcn pg flagJack Xiao1-1/+1
Enable VCN power gating by default. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu: enable vcn dpm scheme for naviJack Xiao1-2/+2
On navi1x, vcn dpm scheme was merged into powergating scheme. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu/vcn2: don't access register when power gatedJack Xiao1-1/+2
It will cause bus hang to access register UVD_STATUS when VCN is in the state of power gated. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: add new interface for vcn powergatingKenneth Feng2-0/+32
add new interface for vcn powrergating and vcn dpm as well. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: enable vcn powergating v2Kenneth Feng1-0/+3
enable vcn powergating in driver for navi10 v2: set vcn pg bit according to AMD_PG_SUPPORT_VCN flag Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu/vcn2: notify SMU power up/down VCNJack Xiao1-0/+7
For sw control power gating, it needs notify SMU to power up/down VCN when enter/exit working state. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu/gfx10: fix issues for suspend/resumeJack Xiao1-5/+30
1). use PREEMPT_QUEUE instead of RESET_QUEUE for gfx ring disablement. 2). Need wait for unmapping queue done before continue execution. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Tianci Yin <tianci.yin@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: set dpm_enabled flag but don't enable vcn dpmHuang Rui2-6/+3
This patch sets dpm_enabled flag but don't enable vcn dpm, because vcn dpm doesn't work so far and we needs to enable the sysfs interfaces. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: update smu11_driver_if_navi10.hKenneth Feng1-11/+6
update the smu11_driver_if_navi10.h since navi10 smu fw update to 42.15.0 Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu/gfx10: fix resume failure when enabling async gfx ringXiaojie Yuan1-12/+14
'adev->in_suspend' code path is missing in gfx_v10_0_gfx_init_queue() Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu: disable some gfx light sleepTianci Yin1-4/+0
temporarily disable to avoid s3 test failure. s3 test failure log: "[drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring sdma0 timeout, signaled seq=8278, emitted seq=8281" Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Tianci Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu/gfx10: update gfx golden settingsTianci Yin1-0/+3
add new registers: mmCGTT_SPI_CLK_CTRL, mmDB_DEBUG3 and mmGL2C_CGTT_SCLK_CTRL. Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Tianci Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: do not set dpm_enabled flag before VCN/DCN DPM is workableHuang Rui1-0/+3
This dpm_enabled flag will be recognized as the VCN DPM enabled as well. In fact VCN/DCN DPM on Navi10 is not good so far, so we cannot enable it for now. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: fix the incorrect type of pptableKenneth Feng1-1/+1
This patch is to fix the incorrect type of pptable, otherwise, the data will be totally wrong in parsing phase. Signed-off-by: Kenneth Feng <Kenneth.Feng@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: don't include the smu11 driver if header in smu v11 (v2)Huang Rui3-4/+6
This header is actually for each asic, so we should not include in smu_v11_0.c. And rename the one for navi10. v2: add hack for XGMI (Alex) Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: move getting MAX_FAN_RPM value to asic levelHuang Rui2-6/+6
Getting MAX_FAN_RPM value needs to be read by pptable, so it should be moved to asic level. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: introduce smu power source type to handle AC/DC source ↵Huang Rui5-1/+52
for each asic This patch introduces new smu power source type, it's to handle the different AC/DC source defines for each asic with the same smu ip. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: move Watermarks_t uses into asic levelHuang Rui3-61/+67
This patch moves the rest of Watermarks_t uses into asic level. It's to avoid the conflicts with different asic. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: move SmuMetrics_t uses into asic levelHuang Rui3-50/+62
This patch moves the rest of SmuMetrics_t uses into asic level. It's to avoid the conflicts with different asic. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: move PPTable_t uses into asic levelHuang Rui3-32/+35
This patch moves the rest of PPTable_t uses into asic level. It's to avoid the conflicts with different asic. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: use the table size member in the structure instead of ↵Huang Rui1-2/+4
getting directly This patch uses the table size member in the structure instead of getting directly, because the table is different in each asic. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: modify smu_update_table to use SMU_TABLE_xxx as the inputHuang Rui2-14/+18
Table id may be different for each asic, so it's good to use this as the input for common interface. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay/smu11: remove smu_update_table_with_argAlex Deucher2-7/+3
Nothing was using it. Just replace with smu_update_table which is what everything was using via a wrapper anyway. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: add tables_init interface for each asicHuang Rui5-15/+42
The smc tables defines should be in the asic level. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: init table_count for smu tables on asic levelHuang Rui3-3/+9
TABLE_COUNT should be inited in asic level. Because the value may be different on each asic even on the same ip. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: introduce smu table id type to handle the smu table for ↵Huang Rui4-0/+79
each asic This patch introduces new smu table type, it's to handle the different smu table defines for each asic with the same smu ip. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: introduce smu feature type to handle feature mask for ↵Huang Rui7-61/+251
each asic This patch introduces new smu feature type, it's to handle the different feature mask defines for each asic with the same smu ip. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: introduce smu clk type to handle ppclk for each asicHuang Rui5-35/+113
This patch introduces new smu clk type, it's to handle the different ppclk defines for each asic with the same smu ip. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu: enable sw smu driver for navi10 by defaultHawking Zhang2-7/+8
Navi10 will use sw smu driver for dynamic power managment, while vega20 could also use sw smu driver when amdgpu_dpm is set to 2 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: enable DCEFCLK dpm supportKenneth Feng1-1/+2
Enabale DCEFCLK dpm on navi10 Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: gfxoff-seperate the Vega20 caseKenneth Feng1-6/+17
seperate the Vega20 case from navi10 for gfxoff so that gfxoff won't be allowed on Vega20 Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/amdgpu: fw version check with gfxoffKenneth Feng2-1/+11
1. check the firmware version when enabling gfxoff 2. overwrite the pptable to make sure gfxoff is really enabled on navi10 Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd: add gfxoff support on navi10Kenneth Feng5-6/+46
add the gfxoff interface to navi10,it's disabled by default. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: add allowed feature mask for navi10Kevin Wang1-2/+5
add smu feature mask: 1.FEATURE_DPM_PREFETCHER_BIT 2.FEATURE_DPM_PREFETCHER_BIT 3.FEATURE_ATHUB_PG Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: optimization feature mask function for asicKevin Wang4-17/+57
1.change function return value type: from "unallowed" to "allowed" 2.replace feature mask number with feature macro, the code will clear. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: remove duplicate code from smu hw initKevin Wang1-4/+0
remove duplicate code (un-used) in smu Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: implement smc firmware v2.1 for smu11Kevin Wang4-30/+84
1.add smc_firmware_header_v2_1 hfirmware support, support more pptable in smc firmware. 2.optimization current pptable load framework. 3.rename read_pptable_from_vbios with setup_pptable. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: add smu11 smu_if_version check for navi10Kevin Wang1-0/+1
add smu11 fw version check for navi10 Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: move the function of is_dpm_running to asic fileKevin Wang3-24/+24
the function os is_dpm_running is aisc related function, so move them to asic file. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: move the function of read_sensor to asic fileKevin Wang3-8/+31
The read_sensor functions has asic related parts code, so move them to asic file to implement. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: move the function of uvd&vce dpm to asic fileKevin Wang3-28/+28
Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: move the function of get[set]_power_profile to asic fileKevin Wang3-198/+199
The callback of get[set]_power_profile is asic related function, so move theme into vega20_ppt file. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-02 23:44:34 +0300