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2019-11-04Merge tag 'tegra-for-5.5-arm-dt' of ↵Olof Johansson15-1653/+8910
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt ARM: tegra: Device tree changes for v5.5-rc1 Adds support for CPU frequency scaling on Tegra20 and Tegra30, EMC frequency scaling on Tegra30, SMMU support for VDE on Tegra30, the STMPE ADC found on Toradex T30 modules as well as fixes for eDP support on Venice2. * tag 'tegra-for-5.5-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: cardhu-a04: Add CPU Operating Performance Points ARM: tegra: cardhu-a04: Set up voltage regulators for DVFS ARM: tegra: trimslice: Add CPU Operating Performance Points ARM: tegra: paz00: Add CPU Operating Performance Points ARM: tegra: paz00: Set up voltage regulators for DVFS ARM: tegra: Add CPU Operating Performance Points for Tegra30 ARM: tegra: Add CPU Operating Performance Points for Tegra20 ARM: tegra: Add Tegra30 CPU clock ARM: tegra: Add Tegra20 CPU clock ARM: tegra: Add External Memory Controller node on Tegra30 ARM: tegra: nyan-big: Add timings for RAM codes 4 and 6 ARM: tegra: Connect SMMU with Video Decoder Engine on Tegra30 ARM: tegra: Add eDP power supplies on Venice2 ARM: tegra: Add SOR0_OUT clock on Tegra124 ARM: tegra: Add stmpe-adc DT node to Toradex T30 modules Link: https://lore.kernel.org/r/20191102144521.3863321-6-thierry.reding@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-04Merge tag 'tegra-for-5.5-dt-bindings' of ↵Olof Johansson7-125/+724
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt dt-bindings: Changes for v5.5-rc1 This contains various updates to device tree bindings and includes that are related to driver changes in other Tegra branches. * tag 'tegra-for-5.5-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: memory: Add binding for NVIDIA Tegra30 External Memory Controller dt-bindings: memory: Add binding for NVIDIA Tegra30 Memory Controller dt-bindings: memory: tegra30: Convert to Tegra124 YAML dt-bindings: regulator: Document regulators coupling of NVIDIA Tegra20/30 SoCs dt-bindings: clock: tegra: Rename SOR0_LVDS to SOR0_OUT Link: https://lore.kernel.org/r/20191102144521.3863321-1-thierry.reding@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-04Merge tag 'sunxi-dt-for-5.5-1' of ↵Olof Johansson22-1/+493
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt Our usual bunch of DT patches, with this time mostly: - Mali GPU support for the H6 - Two new crypto drivers enablement - A few fixes to our DTs, fixed through the validation effort - New boards: NanoPi Duo2 * tag 'sunxi-dt-for-5.5-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (22 commits) dt-bindings: arm: sunxi: add FriendlyARM NanoPi Duo2 ARM: dts: sun8i: add FriendlyARM NanoPi Duo2 arm64: allwinner: h6: Enable GPU node for Tanix TX6 arm64: dts: allwinner: bluetooth for Emlid Neutis N5 ARM: dts: sunxi: h3/h5: add missing uart2 rts/cts pins ARM: dts: sun9i: a80: Add Security System node ARM: dts: sun8i: a83t: Add Security System node arm64: dts: allwinner: sun50i: Add Crypto Engine node on H6 arm64: dts: allwinner: sun50i: Add crypto engine node on H5 arm64: dts: allwinner: sun50i: Add Crypto Engine node on A64 ARM: dts: sun8i: H3: Add Crypto Engine node ARM: dts: sun8i: R40: add crypto engine node dt-bindings: crypto: Add DT bindings documentation for sun8i-ce Crypto Engine arm64: dts: allwinner: Add mali GPU supply for H6 boards arm64: dts: allwinner: Add ARM Mali GPU node for H6 ARM: dts: sun8i: a83t: a711: Add touchscreen node ARM: dts: sun5i: olinuxino micro: Fix AT24 node name ARM: dts: sun9i: Add missing watchdog clocks arm64: dts: sun50i: sopine-baseboard: Expose serial1, serial2 and serial3 arm64: dts: allwinner: orange-pi-3: Enable UART1 / Bluetooth ... Link: https://lore.kernel.org/r/1bf18c83-f41d-4353-9ca2-9585b8693df2.lettre@localhost Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-04ARM: dts: atlas7: Fix "debounce-interval" property misspellingGeert Uytterhoeven1-1/+1
"debounce_interval" was never supported. Link: https://lore.kernel.org/r/20191101160356.32034-3-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Barry Song <baohua@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-04arm64: dts: lg1313: DT fix s/#interrupts-cells/#interrupt-cells/Geert Uytterhoeven1-1/+1
The standard DT property is called "#interrupt-cells". Link: https://lore.kernel.org/r/20191101160356.32034-2-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Chanho Min <chanho.min@lge.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-04arm64: dts: lg1312: DT fix s/#interrupts-cells/#interrupt-cells/Geert Uytterhoeven1-1/+1
The standard DT property is called "#interrupt-cells". Link: https://lore.kernel.org/r/20191101160356.32034-1-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Chanho Min <chanho.min@lge.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-04Merge tag 'renesas-dt-bindings-for-v5.5-tag2' of ↵Olof Johansson5-20/+45
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt Renesas DT binding updates for v5.5 (take two) - JSON schema conversion, - Core support for the new R-Car M3-W+ (r8a77961) SoC, - Board compatible updates. * tag 'renesas-dt-bindings-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: dt-bindings: power: rcar-sysc: Document r8a77961 support dt-bindings: reset: rcar-rst: Document r8a77961 support dt-bindings: arm: renesas: Add Salvator-XS board with R-Car M3-W+ dt-bindings: arm: renesas: Document R-Car M3-W+ SoC DT bindings dt-bindings: arm: renesas: Add R-Car M3-N ULCB with Kingfisher dt-bindings: arm: renesas: Convert 'renesas,prr' to json-schema Link: https://lore.kernel.org/r/20191101155842.31467-7-geert+renesas@glider.be Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-04Merge tag 'renesas-arm64-dt-for-v5.5-tag2' of ↵Olof Johansson11-2/+1373
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt Renesas ARM64 DT updates for v5.5 (take two) - Video-Input and Serial-ATA support on RZ/G2N, - Color Management Module support on various R-Car Gen3 SoCs, - Initial support for the R-Car M3-W+ (r8a77961) SoC on the Salvator-XS board. * tag 'renesas-arm64-dt-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: dts: renesas: Add support for Salvator-XS with R-Car M3-W+ arm64: dts: renesas: Add Renesas R8A77961 SoC support arm64: dts: renesas: Prepare for rename of ARCH_R8A7796 to ARCH_R8A77960 dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions dt-bindings: power: Add r8a77961 SYSC power domain definitions arm64: dts: renesas: r8a774b1: Add SATA controller node arm64: dts: renesas: rcar-gen3: Add CMM units arm64: dts: renesas: r8a774b1: Add VIN and CSI-2 support Link: https://lore.kernel.org/r/20191101155842.31467-5-geert+renesas@glider.be Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-04Merge tag 'omap-for-v5.5/prm-signed' of ↵Olof Johansson11-1/+599
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt PRM reset control dts changes for v5.5 merge window This series of changes adds the PRM reset driver nodes for am3/4, omap4/5 and dra7 SoCs. The reset driver changes make it easier to add support for various accelerators for TI SoCs in a more generic way. Note that this branch is based on the PRM reset driver changes branch. * tag 'omap-for-v5.5/prm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: omap5: Add PRM data ARM: dts: am43xx: Add PRM data ARM: dts: am33xx: Add PRM data ARM: dts: omap4: add PRM nodes ARM: dts: dra7: add PRM nodes soc: ti: omap-prm: add omap5 PRM data soc: ti: omap-prm: add am4 PRM data soc: ti: omap-prm: add dra7 PRM data soc: ti: omap-prm: add data for am33xx soc: ti: omap-prm: add omap4 PRM data soc: ti: omap-prm: add support for denying idle for reset clockdomain soc: ti: omap-prm: poll for reset complete during de-assert soc: ti: add initial PRM driver with reset control support dt-bindings: omap: add new binding for PRM instances Link: https://lore.kernel.org/r/pull-1572623173-281197@atomide.com Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-04ARM: dts: mmp3-dell-ariel: Add a serial point aliasLubomir Rintel1-0/+4
Make sure UART3, where the console is, is called ttyS2. That is consistent with the early console. Link: https://lore.kernel.org/r/20191031163455.1711872-5-lkundrak@v3.sk Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-04ARM: dts: mmp3-dell-ariel: Add a name to /memory nodeLubomir Rintel1-1/+1
Ponted out by DTC: <stdout>: Warning (unit_address_vs_reg): /memory: node has a reg or ranges property, but no unit name Link: https://lore.kernel.org/r/20191031163455.1711872-4-lkundrak@v3.sk Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-04ARM: dts: mmp3: Fix /soc/watchdog node nameLubomir Rintel1-1/+1
There's a typo there that rightfully upsets DTS: <stdout>: Warning (simple_bus_reg): /soc/watchdog@2c000620: simple-bus unit address format error, expected "e0000620" Link: https://lore.kernel.org/r/20191031163455.1711872-3-lkundrak@v3.sk Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-04ARM: dts: mmp3: Add a name to /clocks nodeLubomir Rintel1-1/+1
It should have one and DTC is indeed unhappy about its absence: <stdout>: Warning (unit_address_vs_reg): /soc/clocks: node has a reg or ranges property, but no unit name Link: https://lore.kernel.org/r/20191031163455.1711872-2-lkundrak@v3.sk Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-04ARM: dts: Add RDA8810PL GPIO controllersManivannan Sadhasivam1-0/+48
Add GPIO controllers for RDA8810PL SoC. There are 4 GPIO controllers in this SoC with maximum of 32 gpios. Except GPIOC, all controllers are capable of generating edge/level interrupts from first 8 lines. Link: https://lore.kernel.org/r/20191030101154.6312-2-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-04Merge tag 'hisi-arm64-dt-for-5.5' of git://github.com/hisilicon/linux-hisi ↵Olof Johansson1-0/+38
into arm/dt ARM64: DT: Hisilicon SoCs DT updates for 5.5 - add Mali450 MP4 GPU node in the hi6220 SoC * tag 'hisi-arm64-dt-for-5.5' of git://github.com/hisilicon/linux-hisi: arm64: dts: hisilicon: Add Mali-450 MP4 GPU DT entry Link: https://lore.kernel.org/r/5DB95AAB.8060405@hisilicon.com Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-04Merge tag 'realtek-arm64-dt-for-5.5' of ↵Olof Johansson10-13/+362
git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek into arm/dt Realtek ARM64 based SoC DT for v5.5 Add RTD1293 and RTD1296 DTs. Add the watchdog for all of RTD129x DTs. Add reset controllers for RTD129x and start using them for UARTs. * tag 'realtek-arm64-dt-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek: arm64: dts: realtek: Add RTD129x UART resets arm64: dts: realtek: Add RTD129x reset controller nodes dt-bindings: reset: Add Realtek RTD1295 arm64: dts: realtek: Add watchdog node for RTD129x arm64: dts: realtek: Add oscillator for RTD129x arm64: dts: realtek: Add RTD1296 and Synology DS418 dt-bindings: arm: realtek: Document RTD1296 and Synology DS418 arm64: dts: realtek: Add RTD1293 and Synology DS418j arm64: dts: realtek: Change dual-license from MIT to BSD dt-bindings: arm: realtek: Document RTD1293 and Synology DS418j dt-bindings: arm: realtek: Tidy up conversion to json-schema Link: https://lore.kernel.org/r/20191030041000.31848-2-afaerber@suse.de Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-04Merge branch 'for_5.5/keystone-dts' of ↵Olof Johansson6-6/+103
git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into arm/dt * 'for_5.5/keystone-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone: ARM: configs: keystone: enable cpts ARM: dts: k2l-netcp: add cpts refclk_mux node ARM: dts: k2hk-netcp: add cpts refclk_mux node ARM: dts: k2e-netcp: add cpts refclk_mux node ARM: dts: k2e-clocks: add input ext. fixed clocks tsipclka/b ARM: dts: keystone-clocks: add input fixed clocks Link: https://lore.kernel.org/r/1572372856-20598-2-git-send-email-santosh.shilimkar@oracle.com Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-02Merge tag 'socfpga_dts_updates_for_v5.5' of ↵Olof Johansson4-3/+93
git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt SoCFPGA DTS updates for v5.5 - Arria10 - modify QSPI read-delay property - Agilex - Add QSPI support - Enable USB and LEDs - Add service layer, fpga manager support - Stratix10 - Update QSPI reg address * tag 'socfpga_dts_updates_for_v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: arm64: dts: agilex: add service layer, fpga manager and fpga region arm64: agilex: enable USB and LEDs on agilex devkit arm64: dts: altera: update QSPI reg addresses for Stratix10 arm64: dts: agilex: add QSPI support for Intel Agilex ARM: dts: arria10: Modify QSPI read_delay for Arria10 Link: https://lore.kernel.org/r/20191029143737.24850-1-dinguyen@kernel.org Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-02dt-bindings: arm: sunxi: add FriendlyARM NanoPi Duo2Karl Palsson1-0/+5
Adds bindings for the newly added NanoPi Duo2 board. Signed-off-by: Karl Palsson <karlp@tweak.net.au> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-11-02ARM: dts: sun8i: add FriendlyARM NanoPi Duo2Karl Palsson2-0/+175
This is an Allwinner H3 based board, with 512MB ram, a USB OTG port, microsd slot, an onboard AP6212A wifi/bluetooth module, and a CSI connector. Full details and schematic available from vendor: http://wiki.friendlyarm.com/wiki/index.php/NanoPi_Duo2 Signed-off-by: Karl Palsson <karlp@tweak.net.au> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-11-02arm64: allwinner: h6: Enable GPU node for Tanix TX6Clément Péron1-0/+4
Unlike other H6 boards, Tanix TX6 doesn't have a PMIC so we can enable the GPU without providing a specific power supply. Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-11-01arm64: dts: renesas: Add support for Salvator-XS with R-Car M3-W+Geert Uytterhoeven2-0/+32
Add initial support for the Renesas Salvator-X 2nd version development board equipped with an R-Car M3-W+ SiP with 8 (2 x 4) GiB of RAM. The memory map is as follows: - Bank0: 4GiB RAM : 0x000048000000 -> 0x000bfffffff 0x000480000000 -> 0x004ffffffff - Bank1: 4GiB RAM : 0x000600000000 -> 0x006ffffffff Based on a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191023123342.13100-10-geert+renesas@glider.be
2019-11-01arm64: dts: renesas: Add Renesas R8A77961 SoC supportGeert Uytterhoeven1-0/+723
Add initial support for the Renesas R-Car M3-W+ (R8A77961) SoC. This includes: - Cortex-A57 and Cortex-A53 CPU cores (incl. L2 caches and power state definitions), - Power Management Unit, - PSCI firmware, - Pin Function Controller, - Clock, Reset, System, and Interrupt Controllers, - SCIF2 serial console, - Product Register, - ARM Architectured Timer, and various placeholders to allow to use salvator-xs.dtsi. Based on r8a7796.dtsi. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191023123342.13100-9-geert+renesas@glider.be
2019-11-01arm64: dts: renesas: Prepare for rename of ARCH_R8A7796 to ARCH_R8A77960Geert Uytterhoeven1-0/+3
CONFIG_ARCH_R8A7796 for R-Car M3-W (R8A77960) will be renamed to CONFIG_ARCH_R8A77960, to avoid confusion with R-Car M3-W+ (R8A77961), which will use CONFIG_ARCH_R8A77961. Relax dependencies by handling both symbols. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191023123342.13100-8-geert+renesas@glider.be
2019-11-01Merge tag 'renesas-r8a77961-dt-binding-defs-tag' into renesas-arm64-dt-for-v5.5Geert Uytterhoeven2-0/+97
Renesas R-Car M3-W+ DT Binding Definitions Clock and Power Domain definitions for the Renesas R-Car M3-W+ (R8A77961) SoC, shared by driver and DT source files.
2019-11-01dt-bindings: power: rcar-sysc: Document r8a77961 supportGeert Uytterhoeven1-0/+1
Add DT binding documentation for the System Controller in the Renesas R-Car M3-W+ (R8A77961) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Eugeniu Rosca <erosca@de.adit-jv.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20191023122911.12166-5-geert+renesas@glider.be
2019-11-01dt-bindings: reset: rcar-rst: Document r8a77961 supportGeert Uytterhoeven1-0/+1
Add DT binding documentation for the Reset block in the Renesas R-Car M3-W+ (R8A77961) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Eugeniu Rosca <erosca@de.adit-jv.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20191023122911.12166-4-geert+renesas@glider.be
2019-11-01dt-bindings: arm: renesas: Add Salvator-XS board with R-Car M3-W+Geert Uytterhoeven1-0/+2
Add device tree binding documentation for the Renesas Salvator-XS board equipped with an R-Car M3-W+ (R8A77961) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Eugeniu Rosca <erosca@de.adit-jv.com> Link: https://lore.kernel.org/r/20191023122911.12166-3-geert+renesas@glider.be
2019-11-01dt-bindings: arm: renesas: Document R-Car M3-W+ SoC DT bindingsGeert Uytterhoeven1-0/+4
Add device tree binding documentation for the Renesas R-Car M3-W+ (R8A77961) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Eugeniu Rosca <erosca@de.adit-jv.com> Link: https://lore.kernel.org/r/20191023122911.12166-2-geert+renesas@glider.be
2019-11-01dt-bindings: clock: Add r8a77961 CPG Core Clock DefinitionsGeert Uytterhoeven1-0/+65
Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car M3-W+ (R8A77961) SoC, as listed in Table 8.2b ("List of Clocks [R-Car M3-W/R-Car M3-W+]") of the R-Car Series, 3rd Generation Hardware User's Manual (Rev. 2.00, Jul. 31, 2019). A gap is added for CSIREF, to preserve compatibility with the definitions for R-Car M3-W (R8A77960). Note that internal CPG clocks (S0, S1, S2, S3, SDSRC, SSPSRC, and POST2) are not included, as they are used as internal clock sources only, and never referenced from DT. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20191023122941.12342-3-geert+renesas@glider.be
2019-11-01dt-bindings: power: Add r8a77961 SYSC power domain definitionsGeert Uytterhoeven1-0/+32
Add power domain indices for the R-Car M3-W+ (R8A77961) SoC. Based on Rev. 2.00 of the R-Car Series, 3rd Generation, Hardware User’s Manual (Jul. 31, 2019). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Eugeniu Rosca <erosca@de.adit-jv.com> Link: https://lore.kernel.org/r/20191023122911.12166-6-geert+renesas@glider.be
2019-11-01arm64: dts: allwinner: bluetooth for Emlid Neutis N5Georgii Staroselskii1-0/+13
The Emlid Neutis N5 board has AP6212 BT+WiFi chip. This patch is in line with 8558c6e21ceb ("ARM: dts: sun8i: h3: bluetooth for Banana Pi M2 Zero board") and other commits that add Bluetooth support for similar boards. Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-11-01ARM: dts: sunxi: h3/h5: add missing uart2 rts/cts pinsKarl Palsson1-0/+5
uart1 and uart3 had existing pin definitions for the rts/cts pairs. Add definitions for uart2 as well. Signed-off-by: Karl Palsson <karlp@tweak.net.au> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-11-01ARM: dts: sun9i: a80: Add Security System nodeCorentin Labbe1-0/+9
The Security System is a hardware cryptographic accelerator that support AES/MD5/SHA1/DES/3DES/PRNG/RSA algorithms. It could be found on Allwinner SoC A80 and A83T This patch adds it on the Allwinner A80 SoC Device-tree. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-11-01ARM: dts: sun8i: a83t: Add Security System nodeCorentin Labbe1-0/+9
The Security System is a hardware cryptographic accelerator that support AES/MD5/SHA1/DES/3DES/PRNG/RSA algorithms. It could be found on Allwinner SoC A80 and A83T This patch adds it on the Allwinner A83T SoC Device-tree. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-11-01arm64: dts: allwinner: sun50i: Add Crypto Engine node on H6Corentin Labbe1-0/+9
The Crypto Engine is a hardware cryptographic accelerator that supports many algorithms. This patch enables the Crypto Engine on the Allwinner H6 SoC Device-tree. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-11-01arm64: dts: allwinner: sun50i: Add crypto engine node on H5Corentin Labbe1-0/+9
The Crypto Engine is a hardware cryptographic accelerator that supports many algorithms. It could be found on most Allwinner SoCs. This patch enables the Crypto Engine on the Allwinner H5 SoC Device-tree. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-11-01arm64: dts: allwinner: sun50i: Add Crypto Engine node on A64Corentin Labbe1-0/+9
The Crypto Engine is a hardware cryptographic accelerator that supports many algorithms. It could be found on most Allwinner SoCs. This patch enables the Crypto Engine on the Allwinner A64 SoC Device-tree. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-11-01ARM: dts: sun8i: H3: Add Crypto Engine nodeCorentin Labbe1-0/+9
The Crypto Engine is a hardware cryptographic accelerator that supports many algorithms. It could be found on most Allwinner SoCs. This patch enables the Crypto Engine on the Allwinner H3 SoC Device-tree. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-11-01ARM: dts: sun8i: R40: add crypto engine nodeCorentin Labbe1-0/+9
The Crypto Engine is a hardware cryptographic offloader that supports many algorithms. It could be found on most Allwinner SoCs. This patch enables the Crypto Engine on the Allwinner R40 SoC Device-tree. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-11-01dt-bindings: crypto: Add DT bindings documentation for sun8i-ce Crypto EngineCorentin Labbe1-0/+88
This patch adds documentation for Device-Tree bindings for the Crypto Engine cryptographic accelerator driver. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-10-31arm64: dts: allwinner: Add mali GPU supply for H6 boardsClément Péron4-0/+24
Enable and add supply to the Mali GPU node on all the H6 boards. Regarding the datasheet the maximum time for supply to reach its voltage is 32ms. Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-10-31arm64: dts: allwinner: Add ARM Mali GPU node for H6Clément Péron1-0/+14
Add the mali gpu node to the H6 device-tree. Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-10-31ARM: dts: sun8i: a83t: a711: Add touchscreen nodeMylène Josserand1-0/+16
Enable a FocalTech EDT-FT5x06 Polytouch touchscreen. Signed-off-by: Ondrej Jirman <megous@megous.com> Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> Signed-off-by: Maxime Ripard <mripard@kernel.org>
2019-10-29ARM: tegra: cardhu-a04: Add CPU Operating Performance PointsDmitry Osipenko1-0/+24
Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on Cardhu A04. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: cardhu-a04: Set up voltage regulators for DVFSDmitry Osipenko1-0/+24
Set minimum and maximum voltages, and couple CPU/CORE regulators. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: trimslice: Add CPU Operating Performance PointsDmitry Osipenko1-0/+11
Utilize common Tegra20 CPU OPP table. CPU voltage scaling is available now on TrimSlice. Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: paz00: Add CPU Operating Performance PointsDmitry Osipenko1-0/+14
Utilize common Tegra20 CPU OPP table. CPU DVFS is available now on AC100. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: paz00: Set up voltage regulators for DVFSDmitry Osipenko1-7/+20
Set minimum and maximum voltages, and couple CPU/CORE/RTC regulators. Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29ARM: tegra: Add CPU Operating Performance Points for Tegra30Dmitry Osipenko2-0/+2003
Operating Point are specified per HW version. The OPP voltages are kept in a separate DTSI file because some boards may not define CPU regulator in their device-tree if voltage scaling isn't necessary for them. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-27 10:07:57 +0300