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2022-07-20spi: npcm-fiu: add Arbel NPCM8XX supportMark Brown2-3/+38
Merge series from Tomer Maimon <tmaimon77@gmail.com>: This patch set adds Arbel NPCM8XX Flash Interface Unit (FIU) support to FIU NPCM driver and modify direct read dummy configuration. NPCM8XX FIU supports four controllers. The NPCM FIU driver tested on NPCM845 evaluation board.
2022-07-20spi: dt-bindings: qcom,spi-geni-qcom: allow three interconnectsKrzysztof Kozlowski1-1/+4
Recent Qualcomm Geni SPI nodes, e.g. on SM8450, come also with three interconnects. This fixes dtbs_check warnings like: sm8450-qrd.dtb: spi@a98000: interconnects: [[46, 1, 0, 46, 4, 0], [47, 2, 0, 48, 12, 0], [49, 1, 0, 50, 1, 0]] is too long sm8450-qrd.dtb: spi@a98000: interconnect-names: ['qup-core', 'qup-config', 'qup-memory'] is too long Fixes: 5bdcae1fe1c5 ("spi: dt-bindings: qcom,spi-geni-qcom: convert to dtschema") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220720163841.7283-1-krzysztof.kozlowski@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-20spi: npcm-fiu: Add NPCM8XX supportTomer Maimon1-0/+25
Adding FIU NPCM8XX support to NPCM FIU driver. NPCM8XX FIU supports four controllers. As part of adding NPCM8XX support: - Add NPCM8XX specific compatible string. - Using an internal burst configuration register instead of a GCR register. - Support FIU1 controller. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20220718081146.256070-4-tmaimon77@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-20dt-binding: spi: Add npcm845 compatible to npcm-fiu documentTomer Maimon1-1/+12
Add a compatible string and description for Nuvoton BMC NPCM845 FIU. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20220718081146.256070-3-tmaimon77@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-20spi: npcm-fiu: Modify direct read dummy configurationTomer Maimon1-2/+1
Modify NPCM BMC FIU direct read dummy configuration that according spi-mem direct read function. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20220718081146.256070-2-tmaimon77@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-18spi: atmel: remove #ifdef CONFIG_{PM, SLEEP}Claudiu Beznea1-11/+4
Remove #ifdef CONFIG_PM, #ifdef CONFIG_PM_SLEEP and use SYSTEM_SLEEP_PM_OPS() and RUNTIME_PM_OPS() macros instead which allows getting also rid of __maybe_unused in the code. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220718071052.1707858-1-claudiu.beznea@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-18spi: dt-bindings: Add compatible for MediaTek MT8188Johnson Wang1-0/+1
This commit adds dt-binding documentation of spi bus for MediaTek MT8188 SoC platform. Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Link: https://lore.kernel.org/r/20220715120114.4243-1-johnson.wang@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-18spi: dt-bindings: mediatek,spi-mtk-nor: Update bindings for nor flashAllen-KH Cheng1-6/+9
The spi-mtk-nor controller of mt8173, mt8186 and mt8192 have their DT data. They don't use mt8173 as fallback. Using the fallback of mt8186 to enables the controllers to support mt8188. Not all of spi-mtk-nor controller need interrupt property, so we don't mark interrupt as required. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Link: https://lore.kernel.org/r/20220715115443.4154-1-allen-kh.cheng@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-14spi: dt-bindings: atmel,at91rm9200-spi: convert to json-schemaSergiu Moga2-36/+75
Convert SPI DT binding for Atmel/Microchip SoCs to json-schema. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220713132908.175026-1-sergiu.moga@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-13Add support for Intel Thunder Bay SPI controllerMark Brown4-16/+12
Merge series from nandhini.srikandan@intel.com <nandhini.srikandan@intel.com>: This patch enables support for DW SPI on Intel Thunder Bay. This patch set also enables master mode for latest Designware SPI versions. The driver is tested on Keem Bay and Thunder Bay evaluation board.
2022-07-13spi: microchip-core: fix and cleanupsMark Brown1-36/+20
Merge series from Yang Yingliang <yangyingliang@huawei.com>: Patch #1 fix a UAF in mchp_corespi_remove(). Patch #2 and #3 some cleanups to simpify code.
2022-07-13spi: tegra20-slink: fix UAF in tegra_slink_remove()Yang Yingliang1-1/+2
After calling spi_unregister_master(), the refcount of master will be decrease to 0, and it will be freed in spi_controller_release(), the device data also will be freed, so it will lead a UAF when using 'tspi'. To fix this, get the master before unregister and put it when finish using it. Fixes: 26c863418221 ("spi: tegra20-slink: Don't use resource-managed spi_register helper") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220713094024.1508869-1-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-13spi: Fix simplification of devm_spi_register_controllerYang Yingliang1-5/+14
This reverts commit 59ebbe40fb51 ("spi: simplify devm_spi_register_controller"). If devm_add_action() fails in devm_add_action_or_reset(), devm_spi_unregister() will be called, it decreases the refcount of 'ctlr->dev' to 0, then it will cause uaf in the drivers that calling spi_put_controller() in error path. Fixes: 59ebbe40fb51 ("spi: simplify devm_spi_register_controller") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220712135504.1055688-1-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-13spi: microchip-core: switch to use dev_err_probe()Yang Yingliang1-25/+17
Switch to use dev_err_probe() to simpify error path. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220713025657.3524506-4-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-13spi: microchip-core: switch to use devm_spi_alloc_master()Yang Yingliang1-13/+7
Switch to use devm_spi_alloc_master() to simpify error path. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220713025657.3524506-3-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-13spi: microchip-core: fix UAF in mchp_corespi_remove()Yang Yingliang1-2/+0
When using devm_spi_register_master(), the unregister function will be called in devres_release_all() which is called after ->remove(), so remove spi_unregister_master() andspi_master_put(). Fixes: 9ac8d17694b6 ("spi: add support for microchip fpga spi controllers") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220713025657.3524506-2-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-13spi: dw: Add support for Intel Thunder Bay SPI controllerNandhini Srikandan2-6/+5
Add support for Intel Thunder Bay SPI controller, which uses DesignWare DWC_ssi core and also add common init function for both Keem Bay and Thunder Bay. Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com> Acked-by: Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20220713042223.1458-5-nandhini.srikandan@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-13spi: dw: Add support for master mode selection for DWC SSI controllerNandhini Srikandan2-9/+4
Add support to select the controller mode as master mode by setting Bit 31 of CTRLR0 register. This feature is supported for controller versions above v1.02. Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com> Acked-by: Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20220713042223.1458-4-nandhini.srikandan@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-13spi: Add bindings for Intel Thunder Bay SOCNandhini Srikandan1-0/+2
Add documentation for SPI controller in Intel Thunder Bay SoC. Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20220713042223.1458-3-nandhini.srikandan@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-13spi: dw: Fix IP-core versions macroNandhini Srikandan1-1/+1
Add the missing underscore in IP version macro to avoid compilation issue. The macro is used for IP version comparison in the current patchset. Fixes: 2cc8d9227bbb ("spi: dw: Introduce Synopsys IP-core versions interface") Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com> Acked-by: Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20220713042223.1458-2-nandhini.srikandan@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-11spi: remove duplicate parameters check in acpi_spi_add_resource()Andy Shevchenko1-3/+0
The acpi_spi_add_resource() is never called with ctrl == NULL and index == -1. The only caller already performs the check. Hence remove the duplication from the acpi_spi_add_resource(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220709000709.35622-2-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-11spi: propagate error code to the caller of acpi_spi_device_alloc()Andy Shevchenko1-1/+1
Since acpi_spi_device_alloc() has been designed to return an error pointer we may now properly propagate error codes to the caller of it. It helps debugging a lot. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220709000709.35622-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-11spi: Return deferred probe error when controller isn't yet availableAndy Shevchenko1-1/+1
If the controller is not available, it might be in the future and we would like to re-probe the peripheral again. For that purpose return deferred probe. BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=215993 Fixes: 87e59b36e5e2 ("spi: Support selection of the index of the ACPI Spi Resource before alloc") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220709212956.25530-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-06spi: AMD SPI controller driver bug fix and cleanupsMark Brown1-23/+30
Merge series from Cristian Ciocaltea <cristian.ciocaltea@collabora.com>: This patch series addresses an issue in the spi-amd driver and, while there, performs some additional cleanups, like simplifying the error handling in the probe function and removing an unused struct member. For improving code readability, it also adds some kernel-doc comments.
2022-07-06spi: amd: Add struct and enum kernel-doc commentsCristian Ciocaltea1-2/+12
Provide documentation comments in the kernel-doc format for enum amd_spi_versions and struct amd_spi. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220706100626.1234731-6-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-06spi: amd: Drop io_base_addr member from struct amd_spiCristian Ciocaltea1-1/+0
The io_base_addr member of struct amd_spi is not referenced anywhere in the driver implementation and there is no indication that it could be used in the future, hence drop it. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220706100626.1234731-5-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-06spi: amd: Make use of dev_err_probe()Cristian Ciocaltea1-11/+8
Simplify the error handling in probe function by switching from dev_err() to dev_err_probe(). Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220706100626.1234731-4-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-06spi: amd: Make use of devm_spi_alloc_master()Cristian Ciocaltea1-11/+4
Make use of the devm variant of spi_alloc_master() in order to cleanup and simplify the error handling in the probe function by getting rid of the goto statements. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220706100626.1234731-3-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-06spi: amd: Limit max transfer and message sizeCristian Ciocaltea1-0/+8
Enabling the SPI CS35L41 audio codec driver for Steam Deck [1] revealed a problem with the current AMD SPI controller driver implementation, consisting of an unrecoverable system hang. The issue can be prevented if we ensure the max transfer size and the max message size do not exceed the FIFO buffer size. According to the implementation of the downstream driver, the AMD SPI controller is not able to handle more than 70 bytes per transfer, which corresponds to the size of the FIFO buffer. Hence, let's fix this by setting the SPI limits mentioned above. [1] https://lore.kernel.org/r/20220621213819.262537-1-cristian.ciocaltea@collabora.com Reported-by: Anastasios Vacharakis <vacharakis@o2mail.de> Fixes: bbb336f39efc ("spi: spi-amd: Add AMD SPI controller driver support") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220706100626.1234731-2-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-04spi: dt-bindings: zynqmp-qspi: add missing 'required'Krzysztof Kozlowski1-0/+7
During the conversion the bindings lost list of required properties. Fixes: c58db2abb19f ("spi: convert Xilinx Zynq UltraScale+ MPSoC GQSPI bindings to YAML") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20220704130618.199231-2-krzysztof.kozlowski@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-04spi: dt-bindings: cadence: add missing 'required'Krzysztof Kozlowski1-0/+7
During the conversion the bindings lost list of required properties. Fixes: aa7968682a2b ("spi: convert Cadence SPI bindings to YAML") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20220704130618.199231-1-krzysztof.kozlowski@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-01spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-widthConor Dooley1-6/+0
Most users of dw-apb-ssi use spi-{r,t}x-bus-width of 1, however the Canaan k210 is wired up for a width of 4. Quoting Serge: The modern DW APB SSI controllers of v.4.* and newer also support the enhanced SPI Modes too (Dual, Quad and Octal). Since the IP-core version is auto-detected at run-time there is no way to create a DT-schema correctly constraining the Rx/Tx SPI bus widths. /endquote As such, drop the restriction on only supporting a bus width of 1. Link: https://lore.kernel.org/all/20220620205654.g7fyipwytbww5757@mobilestation/ Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Tested-by: Niklas Cassel <niklas.cassel@wdc.com> Link: https://lore.kernel.org/r/20220629184343.3438856-5-mail@conchuod.ie Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-30Fix some coding style issuesMark Brown2-94/+94
Merge series from David Jander <david@protonic.nl>: This series fixes some coding style issues. No functional change.
2022-06-30spi: spi.c: Remove redundant else blockDavid Jander1-5/+5
Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: David Jander <david@protonic.nl> Link: https://lore.kernel.org/r/20220629142519.3985486-4-david@protonic.nl Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-30spi: spi.c: Fix comment styleDavid Jander2-88/+88
Capitalize first word in comment where appropriate and add parentheses to function names. Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: David Jander <david@protonic.nl> Link: https://lore.kernel.org/r/20220629142519.3985486-3-david@protonic.nl Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-30spi: spi.c: White-space fix in __spi_pump_messages()David Jander1-1/+1
Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: David Jander <david@protonic.nl> Link: https://lore.kernel.org/r/20220629142519.3985486-2-david@protonic.nl Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-30spi: pxa2xx: Add support for Intel Meteor Lake-PJarkko Nikula1-0/+4
Add support for LPSS SPI on Intel Meteor Lake-P. It has three controllers each having two chip selects. This squashes a fix from Ap, Kamal <kamal.ap@intel.com> fixing incorrect PCI ID of 3rd controller. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20220630073305.632850-1-jarkko.nikula@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-29spi support for Exynos Auto v9 SoCMark Brown2-10/+49
Merge series from Chanho Park <chanho61.park@samsung.com>: Add to support Exynos Auto v9 SoC's spi. By supporting USI(Universal Serial Interface) mode, the SoC can support up to 12 spi ports. Thus, we need to increase MAX_SPI_PORTS from 6 to 12. The spi of the SoC can support loopback mode unlike previous exynos SoCs. To separate the feature, we need to add .has_loopback to the s3c64xx_spi_port_config. Furthermore, it uses 4 as the default internal clock divider. We also need to clk_div field of the structure and assign "2" as the default value to the existing SoC's port config. Device tree definitions of exynosautov9-spi will be added in separated patchset to include usi(i2c/uart/spi) nodes all together.
2022-06-29spi: intel: Add support for Intel Meteor Lake-P SPI serial flashMika Westerberg1-0/+1
Intel Meteor Lake-P has the same SPI serial flash controller as Alder Lake-P. Add Meteor Lake-P PCI ID to the driver list of supported devices. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20220629113403.79942-1-mika.westerberg@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-29spi: s3c64xx: define exynosautov9 compatibleChanho Park1-1/+4
Define "samsung,exynosautov9-spi" for Exynos Auto v9's spi. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Andi Shyti <andi@etezian.org> Signed-off-by: Chanho Park <chanho61.park@samsung.com> Link: https://lore.kernel.org/r/20220629102304.65712-4-chanho61.park@samsung.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-29spi: s3c64xx: add spi port configuration for Exynos Auto v9 SoCChanho Park1-1/+17
Add exynosautov9 spi port configuration. It supports up to 12 spis so MAX_SPI_PORTS should be increased from 6 to 12. It has DIV_4 as the default internal clock divider and an internal loopback mode to run a loopback test. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Andi Shyti <andi@etezian.org> Signed-off-by: Chanho Park <chanho61.park@samsung.com> Link: https://lore.kernel.org/r/20220629102304.65712-5-chanho61.park@samsung.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-29spi: s3c64xx: support custom value of internal clock dividerChanho Park1-8/+20
Modern exynos SoCs such as Exynos Auto v9 have different internal clock divider, for example "4". To support this internal value, this adds clk_div of the s3c64xx_spi_port_config and assign "2" as the default value to existing s3c64xx_spi_port_config. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Andi Shyti <andi@etezian.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220629102304.65712-3-chanho61.park@samsung.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-29spi: s3c64xx: support loopback modeChanho Park1-0/+8
Modern exynos SoCs can support self loopback mode via setting BIT(3) of MODE_CFG register. Previous SoCs don't have the bit so we need to add has_loopback field in the s3c64xx_spi_port_config. Exynos Auto v9 SoC has the bit and it will define the field to "true". When it is set, SPI_LOOP mode will be marked. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Andi Shyti <andi@etezian.org> Signed-off-by: Chanho Park <chanho61.park@samsung.com> Link: https://lore.kernel.org/r/20220629102304.65712-2-chanho61.park@samsung.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-28Optimize spi_sync pathMark Brown2-127/+202
Merge series from David Jander <david@protonic.nl>: These patches optimize the spi_sync call for the common case that the worker thread is idle and the queue is empty. It also opens the possibility to potentially further optimize the async path also, since it doesn't need to take into account the direct sync path anymore. As an example for the performance gain, on an i.MX8MM SoC with a SPI CAN controller attached (MCP2518FD), the time the interrupt line stays active (which corresponds roughly with the time it takes to send 3 relatively short consecutive spi_sync messages) is reduced from 98us to only 72us by this patch. A note about message ordering: This patch series should not change the behavior of message ordering when coming from the same context. This means that if a client driver issues one or more spi_async() messages immediately followed by a spi_sync() message in the same context, it can still rely on these messages being sent out in the order they were fired.
2022-06-28spi: s3c64xx: move dma_release_channel to unprepareChanho Park1-8/+19
This fixes the sequence of dma_release_channel. Since commit f52b03c70744 ("spi: s3c64xx: requests spi-dma channel only during data transfer"), dma_release_channel has been located in the s3c64xx_spi_transfer_one but this makes invalid return of can_dma callback. __spi_unmap_msg will check whether the request is requested by dma or not via can_dma callback. When it is calling to check it, the channels will be already released at the end of s3c64xx_spi_transfer_one so the callback function will return always "false". So, they can't be unmapped from __spi_unmap_msg call. To fix this, we need to add unprepare_transfer_hardware callback and move the dma_release_channel from s3c64xx_spi_transfer_one to there. Fixes: f52b03c70744 ("spi: s3c64xx: requests spi-dma channel only during data transfer") Signed-off-by: Chanho Park <chanho61.park@samsung.com> Link: https://lore.kernel.org/r/20220627013845.138350-1-chanho61.park@samsung.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-28spi: synquacer: Add missing clk_disable_unprepare()Guo Mengqi1-0/+1
Add missing clk_disable_unprepare() in synquacer_spi_resume(). Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Guo Mengqi <guomengqi3@huawei.com> Link: https://lore.kernel.org/r/20220624005614.49434-1-guomengqi3@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-27spi: opportunistically skip ctlr->cur_msg_completionDavid Jander2-2/+33
There are only a few drivers that do not call spi_finalize_current_message() in the context of transfer_one_message(), and even for those cases the completion ctlr->cur_msg_completion is not needed always. The calls to complete() and wait_for_completion() each take a spin-lock, which is costly. This patch makes it possible to avoid those calls in the big majority of cases, by introducing two flags that with the help of ordering via barriers can avoid using the completion safely. In case of a race with the context calling spi_finalize_current_message(), the scheme errs on the safe side and takes the completion. The impact of this patch is worth the effort: On a i.MX8MM SoC, the time the SPI bus is idle between two consecutive calls to spi_sync(), is reduced from 19.6us to 16.8us... roughly 15%. Signed-off-by: David Jander <david@protonic.nl> Link: https://lore.kernel.org/r/20220621061234.3626638-12-david@protonic.nl Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-27spi: Ensure the io_mutex is held until spi_finalize_current_message()David Jander2-22/+16
This patch introduces a completion that is completed in spi_finalize_current_message() and waited for in __spi_pump_transfer_message(). This way all manipulation of ctlr->cur_msg is done with the io_mutex held and strictly ordered: __spi_pump_transfer_message() will not return until spi_finalize_current_message() is done using ctlr->cur_msg, and its calling context is only touching ctlr->cur_msg after returning. Due to this, we can safely drop the spin-locks around ctlr->cur_msg. Signed-off-by: David Jander <david@protonic.nl> Link: https://lore.kernel.org/r/20220621061234.3626638-11-david@protonic.nl Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-27spi: Set ctlr->cur_msg also in the sync transfer caseDavid Jander1-0/+1
Some drivers rely on this to point to the currently processed message, so set this here also. Signed-off-by: David Jander <david@protonic.nl> Link: https://lore.kernel.org/r/20220621061234.3626638-10-david@protonic.nl Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-27spi: Remove unneeded READ_ONCE for ctlr->busy flagDavid Jander1-1/+1
Now this flag is written entirely in the mutex, so no need for READ_ONCE Signed-off-by: David Jander <david@protonic.nl> Link: https://lore.kernel.org/r/20220621061234.3626638-9-david@protonic.nl Signed-off-by: Mark Brown <broonie@kernel.org>
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