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2022-03-31drm/i915: Extract intel_edp_has_drrs()Ville Syrjälä2-25/+34
2022-04-01drm/i915/display: Add HAS_MBUS_JOININGJosé Roberto de Souza2-3/+5
2022-04-01drm/i915/dmc: split out dmc registers to a separate fileJani Nikula4-21/+32
2022-04-01drm/i915/dmc: hide DMC version macrosJani Nikula2-4/+4
2022-04-01drm/i915/dmc: abstract GPU error state dumpJani Nikula4-9/+25
2022-03-31drm/i915: Handle the DG2 max bw properlyVinod Govindapillai1-10/+15
2022-03-30drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTLJosé Roberto de Souza3-40/+54
2022-03-30drm/i915/display/adlp: Adjust MBUS DBOX BW and B creditsCaz Yokoyama1-1/+4
2022-03-30drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX...José Roberto de Souza2-13/+25
2022-03-30drm/i915/dp: make DSC usage logging actually usefulJani Nikula1-7/+12
2022-03-30drm/i915/audio: move has_audio checks to within codec enable/disableJani Nikula5-42/+26
2022-03-30drm/i915/audio: unify audio codec enable/disable debug loggingJani Nikula3-38/+11
2022-03-30drm/i915: Move intel_vtd_active and run_as_guest to i915_utilsTvrtko Ursulin18-48/+66
2022-03-30drm/i915/dmc: fix i915_reg_t usageJani Nikula1-2/+2
2022-03-30drm/i915/dmc: move dmc debugfs to intel_dmc.cJani Nikula3-74/+85
2022-03-30drm/i915/dmc: move assert_dmc_loaded() to intel_dmc.cJani Nikula3-12/+13
2022-03-30drm/i915/dmc: simplify intel_dmc_load_program() conditionsJani Nikula2-13/+4
2022-03-29drm/i915/ats-m: add ATS-M platform infoMatt Roper1-14/+24
2022-03-29drm/i915: Add RPL-S PCI IDsTejas Upadhyay1-1/+3
2022-03-29drm/i915: Change SDVO fixed mode handlingVille Syrjälä1-19/+10
2022-03-29drm/i915: Use intel_panel_edid_fixed_mode() for sdvoVille Syrjälä1-10/+3
2022-03-29drm/i915: Extract intel_panel_encoder_fixed_mode()Ville Syrjälä4-30/+31
2022-03-29drm/i915: Extract intel_panel_vbt_sdvo_fixed_mode()Ville Syrjälä3-10/+26
2022-03-29drm/i915: Rename intel_panel_vbt_fixed_mode()Ville Syrjälä6-6/+6
2022-03-29drm/i915: Use intel_panel_preferred_fixed_mode() moreVille Syrjälä4-14/+18
2022-03-29drm/i915: Extract intel_edp_add_properties()Ville Syrjälä1-5/+17
2022-03-29drm/i915: Use DRM_MODE_FMT+DRM_MODE_ARG()Ville Syrjälä7-37/+37
2022-03-29drm/i915: Pass intel_connector to intel_panel_{init,fini}()Ville Syrjälä9-15/+15
2022-03-29drm/i915: Split pipe+output CSC programming to noarm+arm pairVille Syrjälä1-13/+23
2022-03-29drm/i915: Split color_commit() into noarm+arm pairVille Syrjälä3-28/+56
2022-03-29drm/i915: Make ilk+ pfit regiser unlockedVille Syrjälä1-9/+9
2022-03-29drm/i915: Remove locks around skl+ scaler programmingVille Syrjälä1-10/+0
2022-03-29docs: gpu: i915.rst: Fix DRRS documentationJosé Roberto de Souza1-13/+1
2022-03-29drm/i915: Add a DP1.2 compatible way to read LTTPR capabilitiesImre Deak3-31/+60
2022-03-28drm/i915/display: Extend DP HDR support to hsw+Uma Shankar1-1/+20
2022-03-28drm/i915/intel_combo_phy: Print I/O voltage infoAnkit Nautiyal1-10/+25
2022-03-28drm/i915/display: Remove check for low voltage sku for max dp source rateAnkit Nautiyal1-29/+3
2022-03-22drm/i915: s/enable/active/ for DRRSVille Syrjälä4-20/+27
2022-03-21drm/i915: Add "maximum pipe read bandwidth" checksVille Syrjälä2-5/+32
2022-03-21drm/i915: Fix DBUF bandwidth vs. cdclk handlingVille Syrjälä4-89/+147
2022-03-21drm/i915: Properly write lock bw_state when it changesVille Syrjälä1-1/+23
2022-03-21drm/i915: Round up when calculating display bandwidth requirementsVille Syrjälä1-2/+2
2022-03-21drm/i915: Nuke intel_bw_calc_min_cdclk()Ville Syrjälä3-76/+5
2022-03-21drm/i915: Remove total[] and uv_total[] from ddb allocationVille Syrjälä1-60/+62
2022-03-21drm/i915: Pre-calculate plane relative data rateVille Syrjälä4-154/+108
2022-03-21drm/i915: Split plane data_rate into data_rate+data_rate_yVille Syrjälä5-38/+42
2022-03-21drm/i915: Tweak plane ddb allocation trackingVille Syrjälä6-91/+74
2022-03-21drm/i915/display/adlp: More voltage swing table updatesJosé Roberto de Souza1-4/+18
2022-03-21drm/i915/sdvo: prefer __packed over __attribute__((packed))Jani Nikula1-1/+1
2022-03-18drm/i915: Rename QGV request/response bitsVille Syrjälä2-10/+17
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