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2020-02-26drm/amdgpu: move get_xgmi_relative_phy_addr to amdgpu_xgmi.cHawking Zhang3-16/+21
centralize all the xgmi related function to amdgpu_xgmi.c Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-26drm/amdgpu: add dpm helper function for DF Cstate controlHawking Zhang2-0/+20
The helper function hides software smu and legacy powerplay implementation for DF Cstate control. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-26drm/amdgpu: update psp firmwares loading sequence V2Evan Quan2-6/+61
For those ASICs with DF Cstate management centralized to PMFW, TMR setup should be performed between pmfw loading and other non-psp firmwares loading. V2: skip possible SMU firmware reloading Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-26drm/amdgpu: Remove kfd eviction fence before release bo (v2)xinhui pan4-0/+49
No need to trigger eviction as the memory mapping will not be used anymore. All pt/pd bos share same resv, hence the same shared eviction fence. Everytime page table is freed, the fence will be signled and that cuases kfd unexcepted evictions. v2: squash in 32 bit fix CC: Christian König <christian.koenig@amd.com> CC: Felix Kuehling <felix.kuehling@amd.com> CC: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: xinhui pan <xinhui.pan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: limit display clock to 100MHz to avoid FIFO errorYu-ting Shen2-0/+4
[Why] when changing display clock, SMU need to use power up DFS and use DENTIST to ramp DFS DID to switch target frequency before switching back to bypass. [How] fixed the minimum display clock to 100MHz, it's W/A the same with PCO. Signed-off-by: Yu-ting Shen <Yu-ting.Shen@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: Access patches from stream for ignore MSA monitor patchJaehyun Chung1-2/+2
[Why] System will crash when trying to access local sink in core_link_enable_stream in MST case. [How] Access patches directly from stream. Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Reviewed-by: Ashley Thomas <Ashley.Thomas2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: Temporarily disable stutter on MPO transitionGeorge Shen5-1/+37
[Why] Underflow sometimes occurs during transition into MPO with stutter enabled. [How] When transitioning into MPO, disable stutter. Re-enable stutter within one frame. Signed-off-by: George Shen <george.shen@amd.com> Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: Make clock table struct more accessibleSung Lee1-1/+1
[WHY] Currently clock table struct is very far down in the bounding box struct making it hard to find while debugging, especially when using the dal3dbgext. [HOW] Move it up so it is the first struct defined, and therefore much easier to find and access. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: optimize prgoram wm and clksYongqiang Sun10-102/+237
[Why] In some display configuration like 1080P monitor playing a 1080P video, if user use ALT+F4 to exit Movie and TV, there is a chance clocks are same only water mark changed. Current clock optimization machanism will result in water mark keeps high after exit Movie and TV app. [How] Return if watermark need to be optimized when doing program watermark, perform the optimization after. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: correct dml surface size assignmentDmytro Laktyushkin1-4/+4
Need to assign surface size rather than viewport size for surface size dml variable. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: Update TTU properlyAlvin Lee1-0/+8
[Why] We need to update TTU properly if DRAMClockChangeWatermark changes. If TTU < DRAMClockChangeWatermark, we pstate won't be allowed and we will hang in some PSR cases. [How] Update TTU if DramClockChangeWatermark value increases (only if TTU was dependent on the watermark value on the DRAMClockChangeWatermark value in the first place). Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: Fix RV2 Variant DetectionMichael Strauss3-18/+21
[WHY] RV2 and variants are indistinguishable by hw internal rev alone, need to be distinguishable in order to correctly set max vlevel. Previous detection change incorrectly checked for hw internal rev. [HOW] Use pci revision to check if RV2 or low power variant Correct a few overlapping ASICREV range checks Signed-off-by: Michael Strauss <michael.strauss@amd.com> Reviewed-by: Michael Strauss <Michael.Strauss@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: Add driver support for enabling PSR on DMCUBWyatt Wood8-10/+24
[Why] We want to be able to enable PSR on DMCUB, and fallback to DMCU when necessary. [How] Add infrastructure to enable and disable PSR on DMCUB. Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: 3.2.74Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: remove unused dml variableDmytro Laktyushkin3-3/+0
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: update dml input population functionDmytro Laktyushkin4-14/+18
Update dcn20_populate_dml_pipes_from_context to correctly handle odm when no surface is provided. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: Add visual confirm support for FreeSync 2 ARGB2101010Peikang Zhang1-0/+4
[Why] DalMPVisualConfirm does not support FreeSync 2 ARGB2101010 which causes black visual confirm bar when playing HDR video on FreeSync 2 display in full screen mode [How] Added pink color for DalMPVisualConfirm on FreeSync 2 ARGB2101010 surface Signed-off-by: Peikang Zhang <peikang.zhang@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: Link training TPS1 workaroundMartin Leung3-10/+10
[Why] Previously implemented early_cr_pattern was link level but the whole asic should be affected. [How] - change old link flag to dc level - new bit in dc->work_arounds set by DM Signed-off-by: Martin Leung <martin.leung@amd.com> Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: Monitor patch to delay setting ignore MSA bitJaehyun Chung2-0/+4
[Why] Some displays clear ignore MSA bit on mode change, which cause blackscreen when programming variable vtotals. Ignore MSA bit needs programming needs to be delayed or re-set to be retained. [How] Create patch to delay programming ignore MSA bit after unblanking stream. Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: Workaround required for link training reliabilityDavid Galiffi2-1/+19
[Why] A software workaround is required for all vendor-built cards on platform. [How] When performing DP link training, we must send TPS1 before DPCD:100h is written with the proper bit rate value. This change must be applies in ALL cases when LT happens. Signed-off-by: David Galiffi <David.Galiffi@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: Revert "DCN2.x Do not program DPPCLK if same value"Sung Lee1-1/+1
[WHY] Not programming dto with same values causes test failures in DCN2 diags DPP tests. [HOW] This reverts commit 1b53e733238c0f7faa4744ec7c8c6f193649f168. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: Add DMUB firmware state debugfsNicholas Kazlauskas1-0/+27
[Why] Firmware state helps to debug sequence issues and hangs for DMCUB commands and we don't have an easy mechanism to dump it from the driver. [How] Add a debugfs entry to dump the current firmware state. Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: programming last delta in output transfer function LUT to a ↵Vladimir Stempen1-0/+13
correct value [Why] Currently DAL programs negative slope for the last point of output transfer function curve. [How] Applying a check for the last PWL point for RGB values not to be smaller than previous. If smaller, initialize the last point values to a sum of previous PWL value and previous PWL delta; Signed-off-by: Vladimir Stempen <vladimir.stempen@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: make some rn_clk_mgr structs and funcs staticAnthony Koo1-4/+4
[Why] There are some structures and functions meant only to be used in the scope of that single rn_clk_mgr c file. [How] Make structs and funcs static if only meant to be used within rn_clk_mgr Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: Add function pointers for panel related hw functionsAnthony Koo6-5/+22
[Why] Make panel backlight and power on/off functions into hardware specific function pointers [How] Add function pointers for panel related hw functions - is_panel_powered_on - is_panel_backlight_on Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: Fix HDMI repeater authenticationBhawanpreet Lakha1-2/+2
when the rxstatus split was done the index was incorrect. This lead to HDMI repeater authentication failure for HDCP2.X So fix it Fixes: 302169003733 ("drm/amd/display: split rxstatus for hdmi and dp") Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: 3.2.73Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: Only round InfoFrame refresh ratesAric Cyr1-6/+2
[Why] When calculating nominal refresh rates, don't round. Only the VSIF needs to be rounded. [How] Revert rounding change for nominal and just round when forming the FreeSync VSIF. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: System crashes when add_ptb_to_table() gets calledPeikang Zhang1-6/+10
[Why] Unused VMIDs were not evicted correctly [How] 1. evict_vmids() logic was fixed; 2. Added boundary check for add_ptb_to_table() and clear_entry_from_vmid_table() to avoid crash caused by array out of boundary; 3. For mod_vmid_get_for_ptb(), vimd is changed from unsigned to signed due to vimd is signed. Signed-off-by: Peikang Zhang <peikang.zhang@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: do not force UCLK DPM to stay at highest state during ↵Samson Tam3-2/+29
display off in DCN2 [Why] Add optimization to allow pstate change support when all displays are off in DCN2. [How] Add clk_mgr_helper_get_active_plane_cnt() to sum plane_count for all valid stream_status[]. If plane_count is 0, then there are no active or virtual streams present. Use plane_count == 0 as extra condition to enable p_state_change_support in dcn2_update_clocks(). Signed-off-by: Samson Tam <Samson.Tam@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: Add dmcu f/w loading for NV12Roman Li1-1/+6
[Why] We need DMCU for features like PSR and ABM. [How] Add path to dmcu firmware binary and load it for Navi12. Signed-off-by: Roman Li <roman.li@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: Don't ask PSP to load DMCUB for backdoor loadNicholas Kazlauskas1-8/+12
[Why] If we're doing backdoor load then do it entirely ourselves without invoking any of the frontdoor path to avoid potential issues with outdated tOS. [How] Check the load type and don't pass it to base if we don't want it loaded. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: Wait for DMCUB to finish loading before executing commandsNicholas Kazlauskas1-0/+5
[Why] When we execute the first command for ASIC_INIT for command table offloading we can hit a timing scenario such that the interrupts for the inbox wptr haven't been enabled yet and the first command is ignored until the second command is sent. [How] This happens when either the SCRATCH0 is already the correct status code or autoload check is unsupported. Clear SCRATCH0 during reset. Also ensure that we don't accidentally reset the ASIC again in case of a hang by clearing GPINT while we're at it. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: Disable PG on NV12Alvin Lee2-3/+13
[Why] According to HW team, PG is dropped for NV12, but programming the registers will still cause power to be consumed, so don't program for NV12. [How] Set function pointer to NULL if NV12 Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: DMUB Firmware Load by PSPHersen Wu1-2/+12
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: dmub back door loadHersen Wu1-5/+4
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: Update TX masks correctlyAlvin Lee1-0/+16
[Why] Bugs occur when TX interrupt comes in when no USB-C on board. [How] Check PHY for USB-C before enabling TX interrupt in DMCU FW. Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: update scaling filtersDmytro Laktyushkin2-939/+1290
Currently there is a minor error in scaling filter coefficients caused by truncation to fit the HW registers.This error accummulates with increased taps, but has gone unnoticed due to vast majority of scaling being done with only 4 taps. Scaling filters are now updated using HW team's filter generator which has quantization error minimization built in. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: dal_ddc_i2c_payloads_create can fail causing panicAric Cyr1-27/+25
[Why] Since the i2c payload allocation can fail need to check return codes [How] Clean up i2c payload allocations and check for errors Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: Add aconnector condition check for dpcd readZhan Liu1-7/+14
[Why] core_link_read_dpcd() will invoke dm_helpers_dp_read_dpcd(), which needs to read dpcd info with the help of aconnector. If aconnector (dc->links[i]->prev) is NULL, then dpcd status cannot be read. As a result, dpcd read fails and a line of error will be printed out in dmesg.log as: "*ERROR* Failed to found connector for link!" [How] Make sure that aconnector (dc->links[i]->prev) is not NULL, then read dpcd status. Signed-off-by: Zhan Liu <zhan.liu@amd.com> Reviewed-by: Joseph Gravenor <Joseph.Gravenor@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amdgpu: Improve Vega20 XGMI TLB flush workaroundFelix Kuehling2-21/+53
Using a heavy-weight TLB flush once is not sufficient. Concurrent memory accesses in the same TLB cache line can re-populate TLB entries from stale texture cache (TC) entries while the heavy-weight TLB flush is in progress. To fix this race condition, perform another TLB flush after the heavy-weight one, when TC is known to be clean. Move the workaround into the low-level TLB flushing functions. This way they apply to amdgpu as well, and KIQ-based TLB flush only needs to synchronize once. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: shaoyun liu <shaoyun.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amdgpu: fix psp ucode not loaded in bare-metalMonk Liu1-1/+1
for bare-metal we alawys need to load sys/sos/kdb Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25amdgpu/gmc_v9: save/restore sdpif regs during S3Shirish S3-1/+39
fixes S3 issue with IOMMU + S/G enabled @ 64M VRAM. Suggested-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amdgpu/discovery: make the discovery code less chattyAlex Deucher1-1/+1
Make the IP block base output debug only. Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amdgpu: fix colliding of preemptionMonk Liu2-5/+6
what: some os preemption path is messed up with world switch preemption fix: cleanup those logics so os preemption not mixed with world switch this patch is a general fix for issues comes from SRIOV MCBP, but there is still UMD side issues not resovlved yet, so this patch cannot fix all world switch bug. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amdgpu: fix memory leak during TDR test(v2)Monk Liu1-1/+5
fix system memory leak v2: fix coding style Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amdgpu: cleanup some incorrect reg access for SRIOVMonk Liu2-3/+4
1) we shouldn't load PSP kdb and sys/sos for VF, they are supposed to be handled by hypervisor 2) ih reroute doesn't work on VF thus we should avoid calling it, besides VF should not use those PSP register sets for PF 3) shouldn't load SMU ucode under SRIOV, otherwise PSP would report error Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-19drm/amdgpu: drop the non-sense firmware version check on arcturusEvan Quan1-2/+3
As the firmware versions of arcturus are different from other gfx9 ASICs. And the warning("CP firmware version too old, please update!") caused by this check can be eliminated. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-19drm/amdgpu: add is_raven_kicker judgement for raven1changzhu1-2/+9
The rlc version of raven_kicer_rlc is different from the legacy rlc version of raven_rlc. So it needs to add a judgement function for raven_kicer_rlc and avoid disable GFXOFF when loading raven_kicer_rlc. Signed-off-by: changzhu <Changfeng.Zhu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-19drm/amdgpu: record non-zero error counter info in NBIO before resetting GPUGuchun Chen1-1/+14
When NBIO's RAS error happens, before trigging GPU reset, it's needed to record error counter information, which can correct the error counter value missed issue when reading from debugfs. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-25 11:32:47 +0300