summaryrefslogtreecommitdiff
AgeCommit message (Expand)AuthorFilesLines
2015-11-23drm/i915: Update DRIVER_DATE to 20151120Daniel Vetter1-1/+1
2015-11-20drm/i915: take a power domain reference while checking the HDMI live statusImre Deak1-0/+4
2015-11-20drm/i915: take a power domain ref only when needed during HDMI detectImre Deak1-3/+4
2015-11-19drm/i915: Tear down fbdev if initialization failsLukas Wunner1-3/+7
2015-11-19async: export current_is_async()Lukas Wunner1-0/+1
2015-11-19Revert "drm/i915: Initialize HWS page address after GPU reset"Arun Siluvery1-6/+0
2015-11-19drm/i915: Fix oops caused by fbdev initialization failureLukas Wunner3-15/+25
2015-11-19drm/i915: Fix i915_ggtt_view_equal to handle rotation correctlyDaniel Vetter2-6/+6
2015-11-19drm/i915: Stuff rotation params into view unionDaniel Vetter3-8/+5
2015-11-19drm/i915: Drop return value from intel_fill_fb_ggtt_viewDaniel Vetter1-11/+5
2015-11-19drm/i915 : Fix to remove unnecsessary checks in postclose function.Namrta Salonie1-2/+0
2015-11-18drm/i915: add MISSING_CASE to a few port/aux power domain helpersImre Deak1-3/+3
2015-11-18drm/i915/ddi: fix intel_display_port_aux_power_domain() after HDMI detectImre Deak1-1/+8
2015-11-18drm/i915: Remove platform specific *_dp_detect() functionsAnder Conselvan de Oliveira1-28/+5
2015-11-18drm/i915: Don't do edp panel detection in g4x_dp_detect()Ander Conselvan de Oliveira1-10/+0
2015-11-18drm/i915: Send TP1 TP2/3 even when panel claims no NO_TRAIN_ON_EXIT.Rodrigo Vivi1-4/+0
2015-11-18drm/i915: PSR: Don't Skip aux handshake on DP_PSR_NO_TRAIN_ON_EXIT.Rodrigo Vivi1-1/+0
2015-11-18drm/i915: Reduce PSR re-activation time for VLV/CHV.Rodrigo Vivi1-2/+1
2015-11-18drm/i915: Delay first PSR activation.Rodrigo Vivi1-2/+16
2015-11-18drm/i915: Type safe register read/writeVille Syrjälä35-1573/+1540
2015-11-18drm/i915: Add missing ')' to SKL_PS_ECC_STAT defineVille Syrjälä1-1/+1
2015-11-18drm/i915: Add 'offset' to uncore funcsVille Syrjälä1-23/+25
2015-11-18drm/i915: Pull the vgpu uncore funcs apart from the rest of gen6+Ville Syrjälä1-26/+54
2015-11-18drm/i915: Turn vgpu pdps into an arrayVille Syrjälä2-15/+8
2015-11-18drm/i915: Wrap context LRI init in a macroVille Syrjälä1-51/+40
2015-11-18drm/i915: Give names to more ring registersVille Syrjälä2-11/+19
2015-11-18drm/i915: Wrap ASSIGN_CTX_{PDP,PM4L} in do {} while(0)Ville Syrjälä1-4/+4
2015-11-18drm/i915: Add wa_ctx_emit_reg()Ville Syrjälä1-4/+6
2015-11-18drm/i915: Add functions to emit register offsets to the ringVille Syrjälä10-23/+33
2015-11-18drm/i915: Make the cmd parser 64bit regs explicitVille Syrjälä2-14/+35
2015-11-18drm/i915: Make the high dword offset more explicit in i915_reg_read_ioctlVille Syrjälä3-12/+22
2015-11-18drm/i915: s/0x50/RING_PSMI_CTL/Ville Syrjälä1-1/+1
2015-11-18drm/i915: Parametrize MOCS registersVille Syrjälä2-31/+40
2015-11-18drm/i915: Parametrize L3 error registersVille Syrjälä3-9/+6
2015-11-18drm/i915: Prefix raw register defines with underscoreVille Syrjälä1-131/+131
2015-11-18drm/i915: Streamline gpio_mmio_base deductionVille Syrjälä1-8/+7
2015-11-18drm/i915: Store DVO SRCDIM register offset under intel_dvo_deviceVille Syrjälä2-14/+10
2015-11-18drm/i915: s/is_sdvob/enum port/Ville Syrjälä3-23/+32
2015-11-18drm/i915: s/PCH_DP_/PORT_/ in intel_trans_dp_port_sel() and move it next to i...Ville Syrjälä3-23/+19
2015-11-18pci: Decouple quirks.c from i915_reg.hVille Syrjälä1-1/+3
2015-11-18drm/i915: Rely on TEST_SINK_START instead of tracking Sink CRC state on dev_p...Rodrigo Vivi2-13/+6
2015-11-18drm/i915: Stop tracking last calculated Sink CRC.Rodrigo Vivi2-32/+9
2015-11-18drm/i915: Make Sink crc calculation waiting for counter to reset.Rodrigo Vivi1-1/+18
2015-11-18drm/i915: Allow 1 vblank to let Sink CRC calculation to start or stop.Rodrigo Vivi1-0/+4
2015-11-17drm/i915/skl: Remove unused suspend and resume callbacksPatrik Jakobsson1-17/+0
2015-11-17drm/i915/gen9: Add boot parameter for disabling DC6Patrik Jakobsson3-3/+18
2015-11-17drm/i915/gen9: Turn DC handling into a power wellPatrik Jakobsson4-35/+90
2015-11-17drm/i915: Explain usage of power well IDs vs bit groupsPatrik Jakobsson1-0/+4
2015-11-17drm/i915: Do not warn on PG2 enabled in gen9_disable_dc5()Patrik Jakobsson1-3/+0
2015-11-17drm/i915: Add a modeset power domainPatrik Jakobsson2-0/+3
generated by cgit v1.2.3 (git 2.39.0) at 2026-01-06 01:31:37 +0300