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2024-07-05Merge tag 'renesas-pinctrl-for-v6.11-tag3' of ↵Linus Walleij1-49/+95
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.11 (take three) - Support output enable on RZ/G2L. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-07-04pinctrl: renesas: rzg2l: Support output enable on RZ/G2LPaul Barker1-4/+63
On the RZ/G2L SoC family, the direction of the Ethernet TXC/TX_CLK signal is selectable to support an Ethernet PHY operating in either MII or RGMII mode. By default, the signal is configured as an input and MII mode is supported. The ETH_MODE register can be modified to configure this signal as an output to support RGMII mode. As this signal is by default an input, and can optionally be switched to an output, it maps neatly onto an `output-enable` property in the device tree. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240625200316.4282-4-paul.barker.ct@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-07-04pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write functionsPaul Barker1-49/+36
The variable naming in the various OEN functions has been confusing. We were passing the _pin & bit variables from rzg2l_pinctrl_pinconf_get() and rzg2l_pinctrl_pinconf_set() as the offset & pin argument to the oen_read() and oen_write() functions. This doesn't make sense, the first of these isn't actually an offset and the second is not needed for RZ/V2H but leads to confusion with the bit variable used within these functions. To tidy this up, instead pass the _pin variable directly to the oen_read() and oen_write() functions with consistent naming. Then rzg3s_read_oen() and rzg3s_write_oen() can use macros to get the port and pin numbers it needs. Instead of passing the pin capabilities into oen_read() and oen_write(), check that the pin supports OEN before calling these functions. Also, merge rzg3s_oen_is_supported() into rzg3s_pin_to_oen_bit() to give a single translation function which returns an error if the pin doesn't support OEN. While we're here, remove an unnecessary branch and clarify the variable naming. Lastly, check that we are not dealing with a dedicated pin before calling RZG2L_PIN_ID_TO_{PORT,PIN}(). Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240625200316.4282-3-paul.barker.ct@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-07-04pinctrl: renesas: rzg2l: Clarify OEN read/write supportPaul Barker1-14/+14
We currently support OEN read/write for the RZ/G3S SoC but not the RZ/G2L SoC family (consisting of RZ/G2L, RZ/G2LC, RZ/G2UL, RZ/V2L & RZ/Five). The appropriate functions are renamed to clarify this and to match the callback names. We should also only set the oen_read and oen_write function pointers for the devices which support these operations. This requires us to check that these function pointers are valid before calling them. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240625200316.4282-2-paul.barker.ct@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-07-03dt-bindings: pinctrl: pinctrl-single: Fix pinctrl-single,gpio-range descriptionNishanth Menon1-5/+5
The binding is supposed to describe the properties of each element of the pinctrl-single,gpio-range array entry, however when we use "- items:" instead of "items:", it explicitly describes that there is just a single entry in the array. The pinctrl-single,gpio-range property should describe more than one entry in the array. Fix the typo and adjust the alignment of the description of the entries appropriately. Fixes: 677a62482bd6 ("dt-bindings: pinctrl: Update pinctrl-single to use yaml") Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/20240627150610.469645-1-nm@ti.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-07-03dt-bindings: pinctrl: npcm8xx: add missing pin group and mux functionTomer Maimon1-10/+12
Add the following missing pin group and mux function: smb6b, smb6c, smb6d, smb7b, smb7c, smb7d, bu4, bu4b, bu5, bu5b, bu6, gpo187. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/20240630090104.565779-1-tmaimon77@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-07-03dt-bindings: pinctrl: pinctrl-single: fix schmitt related propertiesInochi Amaoto1-0/+7
The "pinctrl-single,input-schmitt" have four arguments in the bindings but the driver needs two. According to the meaning of other properties and driver, it should have "enable" suffix. Fortunately, there is no dts using this property, so it is safe to correct this property with the right name. Rename existed property "pinctrl-single,input-schmitt" to "pinctrl-single,input-schmitt-enable" and add the right description for property "pinctrl-single,input-schmitt" used by the driver. Fixes: 677a62482bd6 ("dt-bindings: pinctrl: Update pinctrl-single to use yaml") Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/IA1PR20MB4953D5E7D7D68DDCE31C0031BBCF2@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-07-03pinctrl: freescale: Use scope based of_node_put() cleanupsPeng Fan3-39/+16
Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/20240627131721.678727-4-peng.fan@oss.nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-07-03pinctrl: equilibrium: Use scope based of_node_put() cleanupsPeng Fan1-16/+5
Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/20240627131721.678727-3-peng.fan@oss.nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-07-03pinctrl: ti: iodelay: Use scope based of_node_put() cleanupsPeng Fan1-28/+15
Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/20240627131721.678727-2-peng.fan@oss.nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-07-03pinctrl: qcom: lpass-lpi: increase MAX_NR_GPIO to 32Alexey Klimov1-1/+1
Account for more than only 23 GPIOs in LPASS Low Power Island pinctrl generic driver. The previous value 23 was chosen to satisfy existing SoC-specific drivers. However SM4250 LPI pinctrl uses more than 23 GPIOs and its probe routine fails on: if (WARN_ON(data->npins > MAX_NR_GPIO)) return -EINVAL; with the following message: [ 10.709014] ------------[ cut here ]------------ [ 10.719085] WARNING: CPU: 1 PID: 56 at drivers/pinctrl/qcom/pinctrl-lpass-lpi.c:446 lpi_pinctrl_probe+0x308/0x388 [pinctrl_lpass_lpi] [ 10.719108] Modules linked in: [...] [ 10.719238] CPU: 1 PID: 56 Comm: kworker/u33:0 Not tainted 6.10.0-rc2-00012-ge45ddb1f8d34-dirty #7 [ 10.719245] Hardware name: Qualcomm Technologies, Inc. QRB4210 RB2 (DT) [ 10.719250] Workqueue: events_unbound deferred_probe_work_func [ 10.719265] pstate: 20000005 (nzCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 10.719271] pc : lpi_pinctrl_probe+0x308/0x388 [pinctrl_lpass_lpi] [ 10.719278] lr : lpi_pinctrl_probe+0x44/0x388 [pinctrl_lpass_lpi] ... [ 10.719357] Call trace: [ 10.719361] lpi_pinctrl_probe+0x308/0x388 [pinctrl_lpass_lpi] [ 10.719369] platform_probe+0x68/0xc4 [ 10.719378] really_probe+0xbc/0x29c [ 10.719384] __driver_probe_device+0x78/0x12c [ 10.719390] driver_probe_device+0xd8/0x15c [ 10.719395] __device_attach_driver+0xb8/0x134 [ 10.719401] bus_for_each_drv+0x88/0xe8 [ 10.719407] __device_attach+0xa0/0x190 [ 10.719412] device_initial_probe+0x14/0x20 [ 10.719418] bus_probe_device+0xac/0xb0 [ 10.719423] deferred_probe_work_func+0x88/0xc0 [ 10.719429] process_one_work+0x150/0x294 [ 10.719439] worker_thread+0x2f8/0x408 [ 10.719445] kthread+0x110/0x114 [ 10.719452] ret_from_fork+0x10/0x20 [ 10.719459] ---[ end trace 0000000000000000 ]--- [ 10.719589] qcom-sm4250-lpass-lpi-pinctrl a7c0000.pinctrl: probe with driver qcom-sm4250-lpass-lpi-pinctrl failed with error -22 Fixes: c2e5a25e8d88 ("pinctrl: qcom: Introduce SM4250 LPI pinctrl driver") Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/20240627003654.242870-1-alexey.klimov@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-07-03pinctrl: cy8c95x0: Update cache modificationPatrick Rudolph1-13/+9
In the previous review cycle the regmap cache update code was questioned since it seems and odd way of using regmap_update_bits(). Thus update the regmap cache modification code to better explain what it does and why it's done. This is no functional change, but it's improving code maintainability. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/20240626084525.787298-2-patrick.rudolph@9elements.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-07-03pinctrl: cy8c95x0: Use cleanup.hPatrick Rudolph1-9/+4
Use the guard mutex from cleanup.h to make the code more readable. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/20240626084525.787298-1-patrick.rudolph@9elements.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-07-02Merge tag 'renesas-pinctrl-for-v6.11-tag2-v2' of ↵Linus Walleij4-418/+557
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-07-01pinctrl: renesas: r8a779h0: Remove unneeded separatorsGeert Uytterhoeven1-21/+9
Usually there are no separators between alternate functions. Remove them to increase uniformity. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/1fcd4f8734d063c9a691d9ab8ca0543892eb8388.1718378979.git.geert+renesas@glider.be
2024-07-01pinctrl: renesas: r8a779g0: Add INTC-EX pins, groups, and functionGeert Uytterhoeven1-0/+112
Add pins, groups, and function for the Interrupt Controller for External Devices (INTC-EX) on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/9c33c36d13a5e38d79fa53085339b14631888b50.1718378943.git.geert+renesas@glider.be
2024-07-01pinctrl: renesas: r8a779g0: Remove unneeded separatorsGeert Uytterhoeven1-4/+2
Usually there are no separators between alternate functions. Remove them to increase uniformity. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/2375711d5edd03a209b4ed996f136e1f3c649773.1718378859.git.geert+renesas@glider.be
2024-07-01pinctrl: renesas: r8a779h0: Add AVB MII pins and groupsGeert Uytterhoeven1-0/+52
EtherAVB instances 0 and 1 support both RGMII and MII interfaces. Add the missing pins and groups for MII. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/4a0a12227f2145ef53b18bc08f45b19dcd745fc6.1718378739.git.geert+renesas@glider.be
2024-07-01pinctrl: renesas: r8a779g0: Fix TPU suffixesGeert Uytterhoeven1-65/+63
The Timer Pulse Unit channels have two alternate pin groups: "tpu_to[0-3]" and "tpu_to[0-3]_a". Increase uniformity by adopting R-Car V4M naming: - Rename "tpu_to[0-3]_a" to "tpu_to[0-3]_b", - Rename "tpu_to[0-3]" to "tpu_to[0-3]_a", Fixes: ad9bb2fec66262b0 ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support") Fixes: 050442ae4c74f830 ("pinctrl: renesas: r8a779g0: Add pins, groups and functions") Fixes: 85a9cbe4c57bb958 ("pinctrl: renesas: r8a779g0: Add missing TPU0TOx_A") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/0dd9428bc24e97e1001ed3976b1cb98966f5e7e3.1717754960.git.geert+renesas@glider.be
2024-07-01pinctrl: renesas: r8a779g0: Fix TCLK suffixesGeert Uytterhoeven1-22/+22
The Pin Multiplex attachment in Rev.1.10 of the R-Car V4H Series Hardware User's Manual still has two alternate pins named both TCLK3 and TCLK4. To differentiate, the pin control driver uses "TCLK[34]" and "TCLK[34]_X". In addition, there are alternate pins without suffix, and with an "_A" or "_B" suffix. Increase uniformity by adopting R-Car V4M naming: - Rename "TCLK2_B" to "TCLK2_C", - Rename "TCLK[12]_A" to "TCLK[12]_B", - Rename "TCLK[12]" to "TCLK[12]_A", - Rename "TCLK[34]_A" to "TCLK[34]_C", - Rename "TCLK[34]_X" to "TCLK[34]_A", - Rename "TCLK[34]" to "TCLK[34]_B". Fixes: ad9bb2fec66262b0 ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support") Fixes: 0df46188a58895e1 ("pinctrl: renesas: r8a779g0: Add missing TCLKx_A/TCLKx_B/TCLKx_X") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/2845ff1f8fe1fd8d23d2f307ad5e8eb8243da608.1717754960.git.geert+renesas@glider.be
2024-07-01pinctrl: renesas: r8a779g0: FIX PWM suffixesGeert Uytterhoeven1-40/+36
PWM channels 0, 2, 8, and 9 do not have alternate pins. Remove their "_a" or "_b" suffixes to increase uniformity. Fixes: c606c2fde2330547 ("pinctrl: renesas: r8a779g0: Add missing PWM") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/abb748e6e1e4e7d78beac7d96e7a0a3481b32e75.1717754960.git.geert+renesas@glider.be
2024-07-01pinctrl: renesas: r8a779g0: Fix IRQ suffixesGeert Uytterhoeven1-18/+18
The suffixes of the IRQ identifiers for external interrupts 0-3 are inconsistent: - "IRQ0" and "IRQ0_A", - "IRQ1" and "IRQ1_A", - "IRQ2" and "IRQ2_A", - "IRQ3" and "IRQ3_B". The suffixes for external interrupts 4 and 5 do follow conventional naming: - "IRQ4A" and IRQ4_B", - "IRQ5". Fix this by adopting R-Car V4M naming: - Rename "IRQ[0-2]_A" to "IRQ[0-2]_B", - Rename "IRQ[0-3]" to "IRQ[0-3]_A". Fixes: ad9bb2fec66262b0 ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support") Fixes: 1b23d8a478bea9d1 ("pinctrl: renesas: r8a779g0: Add missing IRQx_A/IRQx_B") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/8ce9baf0a0f9346544a3ac801fd962c7c12fd247.1717754960.git.geert+renesas@glider.be
2024-07-01pinctrl: renesas: r8a779g0: Fix (H)SCIF3 suffixesGeert Uytterhoeven1-98/+94
(H)SCIF instance 3 has two alternate pin groups: "hscif3" and "hscif3_a", resp. "scif3" and "scif3_a", but the actual meanings of the pins within the groups do not match. Increase uniformity by adopting R-Car V4M naming: - Rename "hscif3_a" to "hscif3_b", - Rename "hscif3" to "hscif3_a", - Rename "scif3" to "scif3_b". While at it, remove unneeded separators. Fixes: ad9bb2fec66262b0 ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support") Fixes: 050442ae4c74f830 ("pinctrl: renesas: r8a779g0: Add pins, groups and functions") Fixes: 213b713255defaa6 ("pinctrl: renesas: r8a779g0: Add missing HSCIF3_A") Fixes: 49e4697656bdd1cd ("pinctrl: renesas: r8a779g0: Add missing SCIF3") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/61fdde58e369e8070ffd3c5811c089e6219c7ecc.1717754960.git.geert+renesas@glider.be
2024-07-01pinctrl: renesas: r8a779g0: Fix (H)SCIF1 suffixesGeert Uytterhoeven1-106/+102
The Pin Multiplex attachment in Rev.1.10 of the R-Car V4H Series Hardware User's Manual still has two alternate pin groups (GP0_14-18 and GP1_6-10) each named both HSCIF1 and SCIF1. To differentiate, the pin control driver uses "(h)scif1" and "(h)scif1_x", which were considered temporary names until the conflict was sorted out. Fix this by adopting R-Car V4M naming: - Rename "(h)scif1" to "(h)scif1_a", - Rename "(h)scif1_x" to "(h)scif1_b". Adopt the R-Car V4M naming "(h)scif1_a" and "(h)scif1_b" to increase uniformity. While at it, remove unneeded separators. Fixes: ad9bb2fec66262b0 ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support") Fixes: 050442ae4c74f830 ("pinctrl: renesas: r8a779g0: Add pins, groups and functions") Fixes: cf4f7891847bc558 ("pinctrl: renesas: r8a779g0: Add missing HSCIF1_X") Fixes: 9c151c2be92becf2 ("pinctrl: renesas: r8a779g0: Add missing SCIF1_X") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/5009130d1867e12abf9b231c8838fd05e2b28bee.1717754960.git.geert+renesas@glider.be
2024-07-01pinctrl: renesas: r8a779g0: Fix FXR_TXEN[AB] suffixesGeert Uytterhoeven1-10/+10
The Pin Multiplex attachment in Rev.1.10 of the R-Car V4H Series Hardware User's Manual still has two alternate pins named both "FXR_TXEN[AB]". To differentiate, the pin control driver uses "FXR_TXEN[AB]" and "FXR_TXEN[AB]_X", which were considered temporary names until the conflict was sorted out. Fix this by adopting R-Car V4M naming: - Rename "FXR_TXEN[AB]" to "FXR_TXEN[AB]_A", - Rename "FXR_TXEN[AB]_X" to "FXR_TXEN[AB]_B". Fixes: ad9bb2fec66262b0 ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support") Fixes: 1c2646b5cebfff07 ("pinctrl: renesas: r8a779g0: Add missing FlexRay") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/5e1e9abb46c311d4c54450d991072d6d0e66f14c.1717754960.git.geert+renesas@glider.be
2024-07-01pinctrl: renesas: r8a779g0: Fix CANFD5 suffixGeert Uytterhoeven1-13/+11
CAN-FD instance 5 has two alternate pin groups: "canfd5" and "canfd5_b". Rename the former to "canfd5_a" to increase uniformity. While at it, remove the unneeded separator. Fixes: ad9bb2fec66262b0 ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support") Fixes: 050442ae4c74f830 ("pinctrl: renesas: r8a779g0: Add pins, groups and functions") Fixes: c2b4b2cd632d17e7 ("pinctrl: renesas: r8a779g0: Add missing CANFD5_B") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/10b22d54086ed11cdfeb0004583029ccf249bdb9.1717754960.git.geert+renesas@glider.be
2024-07-01pinctrl: renesas: sh73a0: Use rdev_get_drvdata()Michał Mirosław1-2/+2
Replace `reg_data` access with the official wrapper. The field is going away soon. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/bb6b85722d80d665779e3043d1499c4fc38f0ff3.1714562004.git.mirq-linux@rere.qmqm.pl Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-06-26pinctrl: mlxbf3: Fix return value check for devm_platform_ioremap_resourceChen Ni1-6/+6
Fix return value check for devm_platform_ioremap_resource() in mlxbf3_pinctrl_probe(). Signed-off-by: Chen Ni <nichen@iscas.ac.cn> Acked-by: Asmaa Mnebhi <asmaa@nvidia.com> Link: https://lore.kernel.org/20240621091637.2299310-1-nichen@iscas.ac.cn Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-26pinctrl: aspeed-g6: Add NCSI pin group configPotin Lai1-2/+8
Based on the NCSI pin table (Table 181) in NCSI spec[1], the reference clock output pin (RMIIXRCLKO) is not needed on the management controller side. To optimize pin usage, add new NCSI pin group that excludes RMIIXRCLKO, reducing the number of required pins. LINK: [1] https://www.dmtf.org/sites/default/files/standards/documents/DSP0222_1.2.0a.pdf Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Link: https://lore.kernel.org/20240621093142.698529-3-potin.lai.pt@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-26dt-bindings: pinctrl: aspeed,ast2600-pinctrl: add NCSI groupsPotin Lai1-0/+7
In the NCSI pin table, the reference clock output pin (RMIIXRCLKO) is not needed on the management controller side. Add "NCSI" pin groups that are equivalent to the RMII pin groups, but without the RMIIXRCLKO pin. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Link: https://lore.kernel.org/20240621093142.698529-2-potin.lai.pt@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-26pinctrl: qcom: Introduce SM4250 LPI pinctrl driverSrinivas Kandagatla3-0/+246
Add support for the pin controller block on SM4250 Low Power Island. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/20240612-sm4250-lpi-v4-2-a0342e47e21b@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-26dt-bindings: pinctrl: qcom: Add SM4250 pinctrlSrinivas Kandagatla1-0/+118
Add device tree binding Documentation details for Qualcomm SM4250 LPASS LPI(Low power Island) pinctrl device. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/20240612-sm4250-lpi-v4-1-a0342e47e21b@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-26pinctrl: k210: Use scope based of_node_put() cleanupsPeng Fan1-5/+2
Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/20240504-pinctrl-cleanup-v2-19-26c5f2dc1181@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-26pinctrl: freescale: mxs: Fix refcount of childPeng Fan1-2/+2
of_get_next_child() will increase refcount of the returned node, need use of_node_put() on it when done. Per current implementation, 'child' will be override by for_each_child_of_node(np, child), so use of_get_child_count to avoid refcount leakage. Fixes: 17723111e64f ("pinctrl: add pinctrl-mxs support") Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/20240504-pinctrl-cleanup-v2-18-26c5f2dc1181@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-26pinctrl: pinconf-generic: Use scope based of_node_put() cleanupsPeng Fan1-5/+2
Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/20240504-pinctrl-cleanup-v2-17-26c5f2dc1181@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-26pinctrl: bcm: bcm63xx: Use scope based of_node_put() cleanupsPeng Fan1-3/+1
Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/20240504-pinctrl-cleanup-v2-16-26c5f2dc1181@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-26pinctrl: mediatek: Use scope based of_node_put() cleanupsPeng Fan2-6/+2
Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/20240504-pinctrl-cleanup-v2-14-26c5f2dc1181@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-26pinctrl: nomadik: Use scope based of_node_put() cleanupsPeng Fan2-6/+2
Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/20240504-pinctrl-cleanup-v2-13-26c5f2dc1181@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-26pinctrl: s32cc: Use scope based of_node_put() cleanupsPeng Fan1-21/+10
Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/20240504-pinctrl-cleanup-v2-12-26c5f2dc1181@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-26pinctrl: at91: Use scope based of_node_put() cleanupsPeng Fan2-15/+6
Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/20240504-pinctrl-cleanup-v2-11-26c5f2dc1181@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-26pinctrl: rockchip: Use scope based of_node_put() cleanupsPeng Fan1-8/+3
Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/20240504-pinctrl-cleanup-v2-9-26c5f2dc1181@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-26pinctrl: spear: Use scope based of_node_put() cleanupsPeng Fan1-9/+4
Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/20240504-pinctrl-cleanup-v2-6-26c5f2dc1181@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-26pinctrl: sprd: Use scope based of_node_put() cleanupsPeng Fan1-10/+4
Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/20240504-pinctrl-cleanup-v2-5-26c5f2dc1181@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-26pinctrl: starfive: Use scope based of_node_put() cleanupsPeng Fan2-26/+19
Use scope based of_node_put() cleanup to simplify code. Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/20240504-pinctrl-cleanup-v2-4-26c5f2dc1181@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-26pinctrl: tegra: Use scope based of_node_put() cleanupsPeng Fan2-8/+3
Use scope based of_node_put() cleanup to simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/20240504-pinctrl-cleanup-v2-2-26c5f2dc1181@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-24pinctrl: renesas: rzg2l: Reorganize variable configuration macroLad Prabhakar1-12/+17
The `PIN_CFG_VARIABLE` macro did not indicate the capabilities of a pin but served as a flag indicating that the pins of a port have different capabilities. To better reflect its purpose, move the `PIN_CFG_VARIABLE` macro beside `RZG2L_SINGLE_PIN` and rename it to `RZG2L_VARIABLE_CFG`. Additionally, introduce new macros for packing variable port configurations: - `RZG2L_GPIO_PORT_PACK_VARIABLE(n, a)`: Combines `RZG2L_VARIABLE_CFG` with `RZG2L_GPIO_PORT_PACK` to handle variable pin configurations for a packed port. - `RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(m, a)`: Combines `RZG2L_VARIABLE_CFG` with `RZG2L_GPIO_PORT_SPARSE_PACK` to handle variable pin configurations for a sparse port. Due to the above change the configuration macros have been reorganized as follows: - Shift the bit positions of `PIN_CFG_NOGPIO_INT`, `PIN_CFG_NOD`, `PIN_CFG_SMT`, `PIN_CFG_ELC`, and `PIN_CFG_IOLH_RZV2H` down by one to accommodate the removal of `PIN_CFG_VARIABLE`. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/r/20240618174831.415583-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-06-24pinctrl: renesas: rzg2l: Move RZG2L_SINGLE_PIN definition to top of the fileLad Prabhakar1-7/+7
Define `RZG2L_SINGLE_PIN` at the top of the file to clarify its use for dedicated pins for improved readability. While at it update the comment for `RZG2L_SINGLE_PIN_PACK` macro and place it just above the macro for clarity. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/r/20240618174831.415583-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-06-24pinctrl: renesas: rzg2l: Adjust bit masks for PIN_CFG_VARIABLE to use BIT(62)Lad Prabhakar1-2/+2
Shift the bit masks for `PIN_CFG_PIN_MAP_MASK` and `PIN_CFG_PIN_REG_MASK`, to accommodate `PIN_CFG_VARIABLE` using `BIT(62)`. Previously, these bit masks were placed higher up in the bit range, which did not leave room for `PIN_CFG_VARIABLE` at `BIT(62)`. By adjusting these masks, we ensure that `PIN_CFG_VARIABLE` can occupy `BIT(62)` without any conflicts. The updated masks are now: - `PIN_CFG_PIN_MAP_MASK`: `GENMASK_ULL(61, 54)` (was `GENMASK_ULL(62, 55)`) - `PIN_CFG_PIN_REG_MASK`: `GENMASK_ULL(53, 46)` (was `GENMASK_ULL(54, 47)`) Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/r/20240618174831.415583-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-06-24pinctrl: renesas: rzg2l: Update PIN_CFG_MASK() macro to be 32-bit wideLad Prabhakar1-6/+6
Modify the `PIN_CFG_MASK()` macro to be 32-bit wide. The current maximum value for `PIN_CFG_*` is `BIT(21)`, which fits within a 32-bit mask. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/r/20240618174831.415583-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-06-18pinctrl: freescale: Select missing featuresLinus Walleij1-0/+2
Fix the compile problem for pinctrl-imx-scmi by selecting the right core features so the symbols resolve. Fixes: 1e37f761d016 ("pinctrl: imx: support SCMI pinctrl protocol for i.MX95") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202406172317.Sds860AS-lkp@intel.com/ Link: https://lore.kernel.org/20240618-imx-scmi-generic-v1-1-67808a48beac@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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