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2016-11-03clk: qcom: Add freq tables for a few rcgsRajendra Nayak1-0/+25
Add frequency tables for a few RCG clocks in msm8996 Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-03clk: qcom: Add .is_enabled ops for clk-alpha-pllRajendra Nayak1-0/+26
This would be useful in subsequent patches when the .set_rate operation would need to identify if the PLL is actually enabled Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> [sboyd@codeaurora.org: Simplify return statement of is_enabled op] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: qcom: Enable FSM mode for votable alpha PLLsRajendra Nayak5-28/+38
The votable alpha PLLs need to have the fsm mode enabled as part of the initialization. The sequence seems to be the same as used by clk-pll, so move the function which does this into a common place and reuse it for the clk-alpha-pll Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: qcom: handle alpha PLLs with 16bit alpha val registersRajendra Nayak2-7/+18
Some alpha PLLs have support for only a 16bit programable Alpha Value (as against the default 40bits). Add a flag to handle the 16bit alpha registers Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: qcom: Add support to initialize alpha pllsRajendra Nayak2-0/+51
Add a function to do initial configuration of the alpha plls Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: qcom: Add support for alpha pll hwfsm opsRajendra Nayak2-12/+93
Some PLLs can support an HW FSM mode (different from the Votable FSMs, though its the same bit used to enable Votable FSMs as well as HW FSMs) which enables the HW to do the bypass/reset/enable-output-ctrl sequence on its own. So all thats needed from SW is to set the FSM_ENA bit. PLL_ACTIVE_FLAG is whats used to check if the PLL is active/enabled. Some of the PLLs which support HW FSM can also need an OFFLINE request that needs to be toggled across the enable/disable. We use a flag to identify such cases and handle them. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02Merge branch 'clk-fixes' into clk-nextStephen Boyd4-9/+12
* clk-fixes: clk: mmp: pxa910: fix return value check in pxa910_clk_init() clk: mmp: pxa168: fix return value check in pxa168_clk_init() clk: mmp: mmp2: fix return value check in mmp2_clk_init() clk: qoriq: Don't allow CPU clocks higher than starting value
2016-11-02clk: qcom: ipq4019: changed i2c freq tableAbhishek Sahu1-2/+1
The current I2C freq table uses MND values which is not applicable for I2C since its RCG does not have MND counter. This patch updates the freq table for 19.05 MHz clk frequency with FEPLL_200 parent. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: pxa: export core clocksRobert Jarzmik2-8/+14
pxaxxx_get_clk_frequency_khz() needs several clocks to be available through clk_get(), ie. the cpu clocks, system bus clock and memory clocks. Add the missing clkdev so that their rate can be acquired. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: pxa: b bit of clkcfg means fast busRobert Jarzmik1-2/+2
The meaning of this bit was inverted : - when set to 0, system bus clock is half of the CPU run clock - when set to 1, system bus clock is the CPU run clock Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: pxa: core pll is not affected by t bitRobert Jarzmik2-4/+2
The t bit of clkfcfg doesn't affect the core pll clock, but it makes core clock select between core pll clock and core run clock. As such remove it from the core pll rate reporting function, while it remains in clk_pxa27x_core_get_parent(). Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: pxa: remove unused variablesRobert Jarzmik1-5/+2
This is a cleanup patch to remove unused values not used in their respective functions. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: qoriq: add ls1046a supportMingkai Hu1-0/+41
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: qcom: lcc-ipq806x: Fixup overriding val in regmap_read callAxel Lin1-1/+1
Drop the assignment of regmap_read return code to val, so the code checks the value read. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: mmp: pxa910: fix return value check in pxa910_clk_init()Wei Yongjun1-2/+2
Fix the retrn value check which testing the wrong variable in pxa910_clk_init(). Fixes: 2bc61da9f7ff ("clk: mmp: add pxa910 DT support for clock driver") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: mmp: pxa168: fix return value check in pxa168_clk_init()Wei Yongjun1-1/+1
Fix the retrn value check which testing the wrong variable in pxa168_clk_init(). Fixes: ab08aefcd12d ("clk: mmp: add pxa168 DT support for clock driver") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: mmp: mmp2: fix return value check in mmp2_clk_init()Wei Yongjun1-1/+1
Fix the retrn value check which testing the wrong variable in mmp2_clk_init(). Fixes: 1ec770d92a62 ("clk: mmp: add mmp2 DT support for clock driver") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: tegra: dfll: improve function-level documentationJulia Lawall1-5/+5
Adjust variables to correspond to the names used in the parameter list of the function. Move the struct device * variable up to the place where it appears in the parameter list. Issue detected using Coccinelle (http://coccinelle.lip6.fr/) Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: keystone: improve function-level documentationJulia Lawall1-2/+2
Adjust the documentation to use the actual function names. Issue detected using Coccinelle (http://coccinelle.lip6.fr/) Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: mvebu: migrate CP110 system controller to clk_hw API and registrationMarcin Wojtas1-78/+72
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: Enable compile testing for s2mps11 and max77686Krzysztof Kozlowski1-2/+2
s2mps11 and max77686 clock drivers can be compile tested to increase build coverage. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: renesas: cpg-mssr: Fix inverted debug checkGeert Uytterhoeven1-2/+2
The intention was to enable the checks if debugging is enabled, not disabled. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: nxp: clk-lpc18xx-ccu: Unmap region obtained by of_iomapArvind Yadav1-1/+4
Free memory mapping, if lpc18xx_ccu_init() is not successful. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Acked-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: lpc32xx: add a quirk for PWM and MS clock dividersVladimir Zapolskiy1-4/+28
In common clock framework CLK_DIVIDER_ONE_BASED or'ed with CLK_DIVIDER_ALLOW_ZERO flags indicates that 1) a divider clock may be set to zero value, 2) divider's zero value is interpreted as a non-divided clock. On the LPC32xx platform clock dividers of PWM and memory card clocks comply with the first condition, but zero value means a gated clock, thus it may happen that the divider value is not updated when the clock is enabled and the clock remains gated. The change adds one-shot quirks, which check for zero value of divider on initialization and set it to a non-zero value, therefore in runtime a gate clock will work as expected. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: qoriq: Don't allow CPU clocks higher than starting valueScott Wood1-5/+8
The boot-time frequency of a CPU is considered its rated maximum, as we have no other source of such information. However, this was previously only used for chips with 80% restrictions on secondary PLLs. This usually wasn't a problem because most chips/configs boot with a divider of /1, with other dividers being used only for dynamic frequency reduction. However, at least one config (LS1021A at less than 1 GHz) uses a different divider for top speed. This was causing cpufreq to set a frequency beyond the chip's rated speed. This is fixed by applying a 100%-of-initial-speed limit to all CPU PLLs, similar to the existing 80% limit that only applied to some. Signed-off-by: Scott Wood <oss@buserror.net> Cc: stable@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: qcom: mmcc-8996: Add gpu gdscsRajendra Nayak1-0/+24
Add gpu gdsc data for msm8996 Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: qcom: Handle the clamp_io assert/deassert sequenceRajendra Nayak2-1/+27
Add a flag to mark gdscs which need to support the clamp deassert/assert before and after the gdsc enable/disable Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: imx: improve precision of AV PLL to 1 HzEmil Lundmark1-0/+8
The audio and video PLLs are designed to have a precision of 1 Hz if some conditions are met. The current implementation only allows a precision that depends on the rate of the parent clock. E.g., if the parent clock is 24 MHz, the precision will be 24 Hz; or more generally the precision will be p / 10^6 Hz where p is the parent clock rate. This comes down to how the register values for the PLL's fractional loop divider are chosen. The clock rate calculation for the PLL is PLL output frequency = Fref * (DIV_SELECT + NUM / DENOM) or with a shorter notation r = p * (d + a / b) In addition to all variables being integers, we also have the following conditions: 27 <= d <= 54 -2^29 <= a <= 2^29-1 0 < b <= 2^30-1 |a| < b Here, d, a and b are register values for the fractional loop divider. We want to chose d, a and b such that f(p, r) = p, i.e. f is our round_rate function. Currently, d and b are chosen as d = r / p b = 10^6 hence we get the poor precision. And a is defined in terms of r, d, p and b: a = (r - d * p) * b / p I propose that if p <= 2^30-1 (i.e., the max value for b), we chose b as b = p We can do this since |a| < b |(r - d * p) * b / p| < b |r - d * p| < p Which have two solutions, one of them is when p < 0, so we can skip that one. The other is when p > 0 and p * (d - 1) < r < p * (d + 1) Substitute d = r / p: (r - p) < r < (r + p) <=> p > 0 So, as long as p > 0, we can chose b = p. This is a good choise for b since a = (r - d * p) * b / p = (r - d * p) * p / p = r - d * p r = p * (d + a / b) = p * d + p * a / b = p * d + p * a / p = p * d + a and if d = r / p: a = r - d * p = r - r / p * p = 0 r = p * d + a = p * d + 0 = p * r / p = r I reckon this is the intention by the design of the clock rate formula. Signed-off-by: Emil Lundmark <emil@limesaudio.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02Merge branch 'clk-fixes' into clk-nextStephen Boyd3-12/+11
* clk-fixes: clk: imx: fix integer overflow in AV PLL round rate clk: xgene: Don't call __pa on ioremaped address clk: rockchip: don't return NULL when failing to register ddrclk branch
2016-11-02Merge tag 'v4.9-rockchip-clkfixes1' of ↵Stephen Boyd1-4/+1
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes Fix return value in error case of new ddrclk type. * tag 'v4.9-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: don't return NULL when failing to register ddrclk branch
2016-11-02clk: imx: fix integer overflow in AV PLL round rateEmil Lundmark1-2/+6
Since 'parent_rate * mfn' may overflow 32 bits, the result should be stored using 64 bits. The problem was discovered when trying to set the rate of the audio PLL (pll4_post_div) on an i.MX6Q. The desired rate was 196.608 MHz, but the actual rate returned was 192.000570 MHz. The round rate function should have been able to return 196.608 MHz, i.e., the desired rate. Fixes: ba7f4f557eb6 ("clk: imx: correct AV PLL rate formula") Cc: Anson Huang <b20788@freescale.com> Signed-off-by: Emil Lundmark <emil@limesaudio.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-28clk: xgene: Don't call __pa on ioremaped addressLaura Abbott1-6/+4
ioremaped addresses are not linearly mapped so the physical address can not be figured out via __pa. More generally, there is no guarantee that backing value of an ioremapped address is a physical address at all. The value here is only used for debugging so just drop the call to __pa on the ioremapped address. Fixes: 6ae5fd381251 ("clk: xgene: Silence sparse warnings") Signed-off-by: Laura Abbott <labbott@redhat.com> Acked-by: Loc Ho <lho@apm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-28clk: stm32f469: Add QSPI clockGabriel Fernandez2-19/+158
This patch adds the QSPI clock for stm32f469 discovery board. The gate mapping is a little bit different from stm32f429 soc. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-28clk: stm32f4: Add RTC clockGabriel Fernandez1-1/+136
This patch introduces the support of the RTC clock. RTC clock can have 3 sources: lsi, lse and hse_rtc. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-28clk: stm32f4: Add LSI & LSE clocksGabriel Fernandez1-5/+126
This patch introduces the support of the LSI & LSE clocks. The clock drivers needs to disable the power domain write protection using syscon/regmap to enable these clocks. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-28Merge branch 'clk-fixes' into clk-nextStephen Boyd1-8/+14
* clk-fixes: clk/samsung: Use CLK_OF_DECLARE_DRIVER initialization method for CLKOUT
2016-10-28clk/samsung: Use CLK_OF_DECLARE_DRIVER initialization method for CLKOUTMarek Szyprowski1-8/+14
The Exynos PMU node is an interrupt, clock and PMU (Power Management Unit) controller, and these functionalities are supported by different drivers that matches the same compatible strings. Since commit 989eafd0b609 ("clk: core: Avoid double initialization of clocks") the OF core flags clock controllers registered with the CLK_OF_DECLARE() macro as OF_POPULATED, so platform devices with the same compatible string will not be registered. This prevents the PMU platform device to be created, so the Exynos PMU driver is never probed. This breaks (among other things) Suspend-to-RAM. Fix this by changing CLKOUT driver initialization method to CLK_OF_DECLARE_DRIVER(), which doesn't clear the OF_POPULATED flag, so later a platform device is created and the Exynos PMU platform driver can be be probed properly. Fixes: 989eafd0b609 ("clk: core: Avoid double initialization of clocks") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-23Merge branch 'clk-next-oxnas' into clk-nextMichael Turquette4-90/+231
2016-10-23dt-bindings: clk: oxnas,stdclk: Add OX820 bindingsNeil Armstrong1-13/+6
Add OX820 bindings and remove clock indices from bindings since they are present in the dt-bindings headers files. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20161005150752.22618-7-narmstrong@baylibre.com
2016-10-23clk: oxnas: Add OX820 Gate clocksNeil Armstrong1-0/+58
Add support for the Oxford Semiconductor OX820 SoC gate clocks along the OX810SE SoC support. This rework on concerns the gate clocks since they are different. Future PLL handling code will be added for OX820. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20161005150752.22618-6-narmstrong@baylibre.com
2016-10-23clk: oxnas: Refactor to make use of devm_clk_hw_register()Neil Armstrong1-64/+84
Make usage of static tables identified by the OF match table to feed devm_clk_hw_register() and use of_clk_add_hw_provider(). This structure is cleaner and simplifies adding new SoC support while having common probe and gate ops code. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20161005150752.22618-5-narmstrong@baylibre.com
2016-10-23clk: oxnas: Rename to clk_oxnas_gateNeil Armstrong1-16/+16
Rename clock ops to clk_oxnas_gate in ops and structures. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20161005150752.22618-4-narmstrong@baylibre.com
2016-10-23clk: oxnas: Add dt-bindings include file for OX820Neil Armstrong1-0/+40
In order to support the Oxford Semiconductor Gate clocks, add a dedicated dt-binding include file for gate indexes. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20161005150752.22618-3-narmstrong@baylibre.com
2016-10-23clk: oxnas: Add dt-bindings include file for OX810SENeil Armstrong1-0/+30
In order to prepare support for the Oxford Semiconductor OX820, add a dt-bindings include file used by the ox810se dtsi. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20161005150752.22618-2-narmstrong@baylibre.com
2016-10-21clk: at91: Fix a return value in case of errorChristophe JAILLET1-1/+1
If 'clk_hw_register()' fails, it is likely that we expect to return an error instead of a valid pointer (which would mean success). Fix commit f5644f10dcfb ("clk: at91: Migrate to clk_hw based registration and OF APIs") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-19clk: uniphier: rename MIO clock to SD clock for Pro5, PXs2, LD20 SoCsMasahiro Yamada4-17/+17
I made a mistake as for naming for this block. The MIO block is not implemented for these 3 SoCs in the first place. The current naming will be a trouble if an SoC with both MIO and SD-ctrl blocks appear in the future. This driver has just been merged in the previous merge window. Rename it before the release. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-19clk: uniphier: fix memory overrun bugMasahiro Yamada1-1/+1
The first loop of this "for" statement writes memory beyond the allocated clk_hw_onecell_data. It should be: for (clk_num--; clk_num >= 0; clk_num--) ... Or more simply: while (--clk_num >= 0) ... Fixes: 734d82f4a678 ("clk: uniphier: add core support code for UniPhier clock driver") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-18clk: hi6220: use CLK_OF_DECLARE_DRIVER for sysctrl and mediactrl clock initShawn Guo1-2/+2
The hi6220-sysctrl and hi6220-mediactrl are not only clock provider but also reset controller. It worked fine that single sysctrl/mediactrl device node in DT can be used to initialize clock driver and populate platform device for reset controller. But it stops working after commit 989eafd0b609 ("clk: core: Avoid double initialization of clocks") gets merged. The commit sets flag OF_POPULATED during clock initialization to skip the platform device populating for the same device node. On hi6220, it effectively makes hi6220-sysctrl reset driver not probe any more. The patch changes hi6220 sysctrl and mediactrl clock init macro from CLK_OF_DECLARE to CLK_OF_DECLARE_DRIVER, so that the reset driver using the same hardware block can continue working. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-18clk: mvebu: armada-37xx-periph: Fix the clock gate flagGregory CLEMENT1-0/+1
For the gate part of the peripheral clock setting the bit disables the clock and clearing it enables the clock. This is not the default behavior of clk_gate component, so we need to use the CLK_GATE_SET_TO_DISABLE flag. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Fixes: 8ca4746a78ab ("clk: mvebu: Add the peripheral clock driver for Armada 3700") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-18clk: bcm2835: Clamp the PLL's requested rate to the hardware limits.Eric Anholt1-7/+4
Fixes setting low-resolution video modes on HDMI. Now the PLLH_PIX divider adjusts itself until the PLLH is within bounds. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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