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2016-03-10drm/i915: Fix watermarks for VLV/CHVVille Syrjälä3-12/+22
2016-03-10drm/i915: Pass the correct crtc state to .update_plane()Ville Syrjälä1-3/+1
2016-03-10Revert "drm/i915: Enable PSR by default on Valleyview and Cherryview."Ville Syrjälä1-2/+1
2016-03-09drm/i915: Actually retry with bit-banging after GMBUS timeoutVille Syrjälä1-0/+6
2016-03-09drm/i915: Make SKL/KBL DPLL0 managed by the shared dpll codeAnder Conselvan de Oliveira5-111/+105
2016-03-09drm/i915: Manage HSW/BDW LCPLLs with the shared dpll interfaceAnder Conselvan de Oliveira7-65/+108
2016-03-09drm/i915: Move BXT pll configuration logic to intel_dpll_mgr.cAnder Conselvan de Oliveira2-146/+134
2016-03-09drm/i915: Move SKL/KLB pll selection logic to intel_dpll_mgr.cAnder Conselvan de Oliveira2-302/+306
2016-03-09drm/i915: Move HSW/BDW pll selection logic to intel_dpll_mgr.cAnder Conselvan de Oliveira5-282/+307
2016-03-09drm/i915: Refactor platform specifics out of intel_get_shared_dpll()Ander Conselvan de Oliveira3-84/+145
2016-03-09drm/i915: Use a table to initilize shared dpllsAnder Conselvan de Oliveira3-119/+108
2016-03-09drm/i915: Move shared dpll function prototypes to intel_dpll_mgr.hAnder Conselvan de Oliveira2-28/+30
2016-03-09drm/i915: Move shared dpll struct definitions to separate header fileAnder Conselvan de Oliveira2-75/+107
2016-03-09drm/i915: Store a direct pointer to shared dpll in intel_crtc_stateAnder Conselvan de Oliveira5-52/+132
2016-03-09drm/i915: Split intel_get_shared_dpll() into smaller functionsAnder Conselvan de Oliveira1-35/+74
2016-03-09drm/i915: Move ddi shared dpll code to intel_dpll_mgr.cAnder Conselvan de Oliveira3-473/+472
2016-03-09drm/i915: Move shared dpll code to a new fileAnder Conselvan de Oliveira4-346/+379
2016-03-09drm/i915: Only use sanitized values for ILK watermarksMaarten Lankhorst2-8/+12
2016-03-09drm/i915/bxt: add missing DSI power domain to power well 1Jani Nikula1-0/+1
2016-03-07drm/i915: Fix bogus dig_port_map[] assignment for pre-HSWTakashi Iwai4-4/+3
2016-03-07drm/i915/gen9: Fix DMC firmware initializationImre Deak3-35/+29
2016-03-04drm/i915/hangcheck: Prevent long walks across full-ppgttMika Kuoppala4-16/+7
2016-03-04drm/i915: Generalise common GPU engine reset request/unrequest codeTomas Elf1-20/+36
2016-03-04drm/i915: Use DIV_ROUND_CLOSEST for PWM calculationsVille Syrjälä1-7/+7
2016-03-04drm/i915: Clean up .get_aux_clock_divider() functionsVille Syrjälä1-13/+15
2016-03-04drm/i915: Read out hrawclk from CCK on vlv/chvVille Syrjälä2-1/+3
2016-03-04drm/i915: Use g4x_get_aux_clock_divider() for VLV/CHVVille Syrjälä1-7/+0
2016-03-04drm/i915: Rename s/i9xx/g4x/ in DP codeVille Syrjälä1-7/+7
2016-03-04drm/i915: Store rawclk_freq in dev_privVille Syrjälä5-54/+62
2016-03-03drm/i915: Do not wait atomically for display clocksTvrtko Ursulin1-4/+4
2016-03-03drm/i915: Do not lie about atomic timeout granularityTvrtko Ursulin1-2/+35
2016-03-03drm/i915: Kconfig for extra driver debuggingTvrtko Ursulin2-0/+18
2016-03-03drm/i915/lrc: Do not wait atomically when stopping enginesTvrtko Ursulin1-1/+1
2016-03-03drm/i915: Add wait_for_usTvrtko Ursulin3-10/+12
2016-03-03drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwardsDeepak M2-63/+89
2016-03-03drm/i915: Only recalculate wm's for planes part of the state, v2.Maarten Lankhorst4-29/+47
2016-03-03drm/i915: Allow preservation of watermarks, v2.Maarten Lankhorst1-10/+13
2016-03-03drm/i915: Handle invalid ilk pipe watermarks correctly.Maarten Lankhorst1-1/+1
2016-03-02drm/i915: Hold RPM reference while setting freq limits through sysfsSagar Arun Kamble1-0/+10
2016-03-02drm/i915: Avoid snooping with userptr where not supportedTvrtko Ursulin4-1/+14
2016-03-02drm/i915: Do not return unknown status when load detection is tested.Maarten Lankhorst1-0/+2
2016-03-01drm/i915/gen9: Remove state asserts when disabling DC statesImre Deak1-40/+1
2016-03-01drm/i915/gen9: Disable DC states if power well support is disabledImre Deak1-0/+3
2016-03-01drm/i915/gen9: Sanitize handling of allowed DC statesImre Deak2-21/+58
2016-03-01drm/i915/skl: Fix power domain suspend sequenceImre Deak1-3/+3
2016-03-01drm/i915/error: Capture WA ctx batch in error statearun.siluvery@linux.intel.com2-0/+31
2016-03-01drm/i915: Try to fix CRT port clock limitsVille Syrjälä1-4/+12
2016-03-01drm/i915: Read out VGA dotclock properly on LPTVille Syrjälä4-2/+48
2016-03-01drm/i915: Make the LPT iclkip 20MHz case more genericVille Syrjälä1-21/+19
2016-03-01drm/i915: Remove the SPLL==270Mhz assumption from intel_fdi_link_freq()Ville Syrjälä1-7/+10
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