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2019-12-18mmc: sdhci-msm: convert to devm_platform_ioremap_resourceYangtao Li1-5/+1
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20191215175120.3290-10-tiny.windzz@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-18mmc: sdhci-milbeaut: convert to devm_platform_ioremap_resourceYangtao Li1-3/+1
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Link: https://lore.kernel.org/r/20191215175120.3290-9-tiny.windzz@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-18mmc: sdhci_am654: convert to devm_platform_ioremap_resourceYangtao Li1-3/+1
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Link: https://lore.kernel.org/r/20191215175120.3290-8-tiny.windzz@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-18mmc: sdhci_f_sdh30: convert to devm_platform_ioremap_resourceYangtao Li1-3/+1
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Link: https://lore.kernel.org/r/20191215175120.3290-7-tiny.windzz@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-18mmc: sh_mmcif: convert to devm_platform_ioremap_resourceYangtao Li1-3/+1
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20191215175120.3290-6-tiny.windzz@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-18mmc: sdhci-spear: convert to devm_platform_ioremap_resourceYangtao Li1-3/+1
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Link: https://lore.kernel.org/r/20191215175120.3290-5-tiny.windzz@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-18mmc: sdhci-s3c: convert to devm_platform_ioremap_resourceYangtao Li1-3/+1
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Link: https://lore.kernel.org/r/20191215175120.3290-4-tiny.windzz@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-18mmc: meson-mx-sdio: convert to devm_platform_ioremap_resourceYangtao Li1-3/+1
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Link: https://lore.kernel.org/r/20191215175120.3290-3-tiny.windzz@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-18mmc: tmio: convert to devm_platform_ioremap_resourceYangtao Li1-3/+1
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20191215175120.3290-2-tiny.windzz@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-18mmc: sunxi-mmc: convert to devm_platform_ioremap_resourceYangtao Li1-2/+1
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Link: https://lore.kernel.org/r/20191215175120.3290-1-tiny.windzz@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-18Merge branch 'fixes' into nextUlf Hansson4-3/+16
2019-12-18mmc: sdhci: Add a quirk for broken command queuingAdrian Hunter2-0/+5
Command queuing has been reported broken on some systems based on Intel GLK. A separate patch disables command queuing in some cases. This patch adds a quirk for broken command queuing, which enables users with problems to disable command queuing using sdhci module parameters for quirks. Fixes: 8ee82bda230f ("mmc: sdhci-pci: Add CQHCI support for Intel GLK") Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20191217095349.14592-2-adrian.hunter@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-18mmc: sdhci: Workaround broken command queuing on Intel GLKAdrian Hunter1-1/+9
Command queuing has been reported broken on some Lenovo systems based on Intel GLK. This is likely a BIOS issue, so disable command queuing for Intel GLK if the BIOS vendor string is "LENOVO". Fixes: 8ee82bda230f ("mmc: sdhci-pci: Add CQHCI support for Intel GLK") Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20191217095349.14592-1-adrian.hunter@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-18mmc: sdhci-of-esdhc: use 1/2 periperhal clock for ls1088aYangbo Lu1-1/+2
The eSDHC on LS1088A platform uses 1/2 peripheral clock as base clock. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Link: https://lore.kernel.org/r/20191216091911.14840-1-yangbo.lu@nxp.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-18mmc: sdhci-of-esdhc: fix P2020 errata handlingYangbo Lu1-2/+2
Two previous patches introduced below quirks for P2020 platforms. - SDHCI_QUIRK_RESET_AFTER_REQUEST - SDHCI_QUIRK_BROKEN_TIMEOUT_VAL The patches made a mistake to add them in quirks2 of sdhci_host structure, while they were defined for quirks. host->quirks2 |= SDHCI_QUIRK_RESET_AFTER_REQUEST; host->quirks2 |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; This patch is to fix them. host->quirks |= SDHCI_QUIRK_RESET_AFTER_REQUEST; host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; Fixes: 05cb6b2a66fa ("mmc: sdhci-of-esdhc: add erratum eSDHC-A001 and A-008358 support") Fixes: a46e42712596 ("mmc: sdhci-of-esdhc: add erratum eSDHC5 support") Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20191216031842.40068-1-yangbo.lu@nxp.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-18mmc: mmci: add threaded irq to abort DPSM of non-functional stateLudovic Barre2-6/+41
The stm32_sdmmc variant has build-in support for datatimeout for R1B requests. If a corresponding IRQ is raised, this triggers the DPSM to stay busy and remains in a non-functional state. Only a reset can bring it back to a functional state. Because a reset must be issued from non-atomic context, let's defer this to be managed from a threaded IRQ handler. Besides the reset, the threaded handler also calls mmc_request_done(), to finally complete the request. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Link: https://lore.kernel.org/r/20191211133934.16932-1-ludovic.Barre@st.com [Ulf: A few minor updates to the changelog/comments] Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-18mmc: core: Remove mmc_gpiod_request_*(invert_gpio)Michał Mirosław14-37/+24
Now that invert_gpio arguments are unused, let's remove them. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Link: https://lore.kernel.org/r/64d766d1f8af2e22bce32f4ffa453f7234207ad6.1576031637.git.mirq-linux@rere.qmqm.pl Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-18mmc: core: Rework cd-gpio handlingMichał Mirosław3-43/+12
There are a few places around the code that invert inverted and possibly inverted CD line. That's really confusing. Squash them all into one place in mmc_gpiod_request_cd(). MMC_CAP2_CD_ACTIVE_HIGH is used analogously to WP line: in GPIO mode it is used only at probe time to switch polarity, for native mode it is left as is. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Link: https://lore.kernel.org/r/db189b715596d63caf8c6a088bddc71dd69a879b.1576031637.git.mirq-linux@rere.qmqm.pl Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-18mmc: core: Rework wp-gpio handlingMichał Mirosław5-16/+13
Use MMC_CAP2_RO_ACTIVE_HIGH flag as indicator if GPIO line is to be inverted compared to DT/platform-specified polarity. The flag is not used after init in GPIO mode anyway. No functional changes intended. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Link: https://lore.kernel.org/r/a60f563f11bbff821da2fa2949ca82922b144860.1576031637.git.mirq-linux@rere.qmqm.pl Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-18gpio: add gpiod_toggle_active_low()Michał Mirosław2-0/+18
Add possibility to toggle active-low flag of a gpio descriptor. This is useful for compatibility code, where defaults are inverted vs DT gpio flags or the active-low flag is taken from elsewhere. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Link: https://lore.kernel.org/r/7ce0338e01ad17fa5a227176813941b41a7c35c1.1576031637.git.mirq-linux@rere.qmqm.pl Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-18mmc: sdhci-s3c: remove unused ext_cd_gpio fieldMichał Mirosław1-2/+0
Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/3f12c2deaae9e77a5e7ab8415db7751a27bc3b98.1575916477.git.mirq-linux@rere.qmqm.pl Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-18mmc: cavium: Add missed pci_release_regionsChuhong Yuan1-5/+11
The driver forgets to call pci_release_regions() in probe failure and remove. Add the missed calls to fix it. Signed-off-by: Chuhong Yuan <hslester96@gmail.com> Link: https://lore.kernel.org/r/20191206075408.18355-1-hslester96@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-16Merge branch 'mmc_pinctrl' into nextUlf Hansson11-76/+40
Merge an immutable pinctrl branch from Linus Walleij's tree, which enables pinctrl code consolidations for mmc. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-16mmc: uniphier-sd: Convert to pinctrl_select_default_state()Ulf Hansson1-9/+5
Let's drop the boilerplate code for managing the default pinctrl state and convert into using the new pinctrl_select_default_state(). Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191206170821.29711-10-ulf.hansson@linaro.org
2019-12-16mmc: jz4740: Convert to pinctrl_select_default_state()Ulf Hansson1-1/+1
Let's move away from using pinctrl_pm_select_default_state() as it's scheduled for removal and use pinctrl_select_default_state() instead. Cc: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191206170821.29711-9-ulf.hansson@linaro.org
2019-12-16mmc: atmel-mci: Convert to pinctrl_select_default_state()Ulf Hansson1-1/+1
Let's move away from using pinctrl_pm_select_default_state() as it's scheduled for removal and use pinctrl_select_default_state() instead. Cc: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191206170821.29711-8-ulf.hansson@linaro.org
2019-12-16mmc: sdhci-esdhc-imx: Convert to pinctrl_select_default_state()Ulf Hansson1-9/+2
Let's drop the boilerplate code for managing the default pinctrl state and convert into using the new pinctrl_select_default_state(). Cc: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191206170821.29711-7-ulf.hansson@linaro.org
2019-12-16mmc: omap_hsmmc: Convert to pinctrl_select_default_state()Ulf Hansson1-8/+2
Let's drop the boilerplate code for managing the default pinctrl state and convert into using the new pinctrl_select_default_state(). Additionally, move away from using pinctrl_pm_select_default_state() as it's scheduled for removal and use pinctrl_select_default_state() instead. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191206170821.29711-6-ulf.hansson@linaro.org
2019-12-16mmc: usdhi6rol0: Convert to pinctrl_select_default_state()Ulf Hansson1-14/+1
Let's drop the boilerplate code for managing the default pinctrl state and convert into using the new pinctrl_select_default_state(). Cc: Jesper Nilsson <jesper.nilsson@axis.com> Cc: Lars Persson <lars.persson@axis.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191206170821.29711-5-ulf.hansson@linaro.org
2019-12-16mmc: mmci: Convert to pinctrl_select_default_state()Ulf Hansson2-11/+2
Let's drop the boilerplate code for managing the default pinctrl state and convert into using the new pinctrl_select_default_state(). Additionally, move away from using pinctrl_pm_select_default_state() as it's scheduled for removal and use pinctrl_select_default_state() instead. Cc: Russell King <linux@armlinux.org.uk> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191206170821.29711-4-ulf.hansson@linaro.org
2019-12-16mmc: meson-gx: Convert to pinctrl_select_default_state()Ulf Hansson1-9/+1
Let's drop the boilerplate code for managing the default pinctrl state and convert into using the new pinctrl_select_default_state(). Cc: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191206170821.29711-3-ulf.hansson@linaro.org
2019-12-16Merge branch 'fixes' into nextUlf Hansson4-15/+22
2019-12-16mmc: sdhci: Update the tuning failed messages to pr_debug levelFaiz Abbas1-2/+2
Tuning support in DDR50 speed mode was added in SD Specifications Part1 Physical Layer Specification v3.01. Its not possible to distinguish between v3.00 and v3.01 from the SCR and that is why since commit 4324f6de6d2e ("mmc: core: enable CMD19 tuning for DDR50 mode") tuning failures are ignored in DDR50 speed mode. Cards compatible with v3.00 don't respond to CMD19 in DDR50 and this error gets printed during enumeration and also if retune is triggered at any time during operation. Update the printk level to pr_debug so that these errors don't lead to false error reports. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Cc: stable@vger.kernel.org # v4.4+ Link: https://lore.kernel.org/r/20191206114326.15856-1-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-16dt-bindings: mmc: renesas_sdhi: Document r8a77961 supportGeert Uytterhoeven1-1/+2
Document support for the SDHI controller in the Renesas R-Car M3-W+ (R8A77961) SoC. Update all references to R-Car M3-W from "r8a7796" to "r8a77960", to avoid confusion between R-Car M3-W (R8A77960) and M3-W+. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20191205134349.6410-2-geert+renesas@glider.be Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-16mmc: renesas_sdhi: use recent tap values for HS400Wolfram Sang3-4/+7
New datasheets require different and new values for HS400 with 4taps or 8taps. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191203200513.1758-6-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-16mmc: renesas_sdhi: remove 4taps as a TMIO flagWolfram Sang2-8/+2
Now that the quirks structure is accessible, we can remove the TMIO flag for HS400 using only 4 taps. This is Renesas specific anyhow. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191203200513.1758-5-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-16mmc: renesas_sdhi: make quirks info accessible outside probe()Wolfram Sang2-5/+7
We will need that for a later patch. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191203200513.1758-4-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-16mmc: renesas_sdhi: make warning more preciseWolfram Sang1-1/+1
The warning is not solely used for SDR104 anymore, but for all which require tuning. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191203200513.1758-3-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-16mmc: renesas_sdhi: keep sorting for quirk entriesWolfram Sang1-1/+1
The two devices next to each other are super similar, but still, let's keep the alphanumeric sorting for easier additions later. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191203200513.1758-2-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-16mmc: renesas_sdhi: remove whitelist for internal DMACWolfram Sang1-19/+4
We know now that there won't be Gen3 SoCs with both, SYS-DMAC and internal DMAC. We removed the blacklisting for SYS-DMAC already, so we can remove the whitelisting for internal DMAC, too. This makes adding new SoCs easier. We keep the quirk handling, of course. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191203194859.917-1-wsa@the-dreams.de Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-16mmc: sdhci: fix up CMD12 sendingYangbo Lu1-14/+3
The STOP command is disabled for multiple blocks r/w commands with auto CMD12, when start to send. However, if there is data error, software still needs to send CMD12 according to SD spec. This patch is to allow software CMD12 sending for this case. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20191114111814.35199-1-yangbo.lu@nxp.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-16mmc: spi: Toggle SPI polarity, do not hardcode itLinus Walleij1-3/+8
The code in mmc_spi_initsequence() tries to send a burst with high chipselect and for this reason hardcodes the device into SPI_CS_HIGH. This is not good because the SPI_CS_HIGH flag indicates logical "asserted" CS not always the physical level. In some cases the signal is inverted in the GPIO library and in that case SPI_CS_HIGH is already set, and enforcing SPI_CS_HIGH again will actually drive it low. Instead of hard-coding this, toggle the polarity so if the default is LOW it goes high to assert chipselect but if it is already high then toggle it low instead. Cc: Phil Elwell <phil@raspberrypi.org> Reported-by: Mark Brown <broonie@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20191204152749.12652-1-linus.walleij@linaro.org Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-16mmc: sdhci-of-at91: rework clocks management to support SAM9x60 deviceLudovic Desroches1-47/+58
In the SAM9x60 SoC, there are only two clocks instead of three for the SDHCI device. The base clk is no longer provided, it is generated internally from the mult clk. The values of the base clk and mul in the capabilities registers may not reflect the reality as the mult clk is a programmable clock which can take several rates. As we can't trust those values, take them from the clock tree and update the capabilities according to. As we can have the same pitfall, in some cases, with the SAMA5D2 Soc, stop relying on capabilities too. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20191128074522.69706-2-ludovic.desroches@microchip.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-16dt-bindings: sdhci-of-at91: new compatible string and update propertiesLudovic Desroches1-3/+10
There is a new compatible string for the SAM9X60 sdhci device. It involves an update of the properties about the clocks stuff. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20191128074522.69706-1-ludovic.desroches@microchip.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-16dt-bindings: mmc: sdhci-msm: Add compatible string for sc7180Veerabhadrarao Badiganti1-0/+1
Add sc7180 SoC specific compatible strings for qcom-sdhci controller. Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/0101016eacb255af-3985262d-9b7e-4813-88c2-61838406e12c-000000@us-west-2.amazonses.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-16mmc: sdhci: Update the tuning failed messages to pr_debug levelFaiz Abbas1-2/+2
Tuning support in DDR50 speed mode was added in SD Specifications Part1 Physical Layer Specification v3.01. Its not possible to distinguish between v3.00 and v3.01 from the SCR and that is why since commit 4324f6de6d2e ("mmc: core: enable CMD19 tuning for DDR50 mode") tuning failures are ignored in DDR50 speed mode. Cards compatible with v3.00 don't respond to CMD19 in DDR50 and this error gets printed during enumeration and also if retune is triggered at any time during operation. Update the printk level to pr_debug so that these errors don't lead to false error reports. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Cc: stable@vger.kernel.org # v4.4+ Link: https://lore.kernel.org/r/20191206114326.15856-1-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-16mmc: sdhci-of-esdhc: Revert "mmc: sdhci-of-esdhc: add erratum A-009204 support"Rasmus Villemoes1-3/+0
This reverts commit 5dd195522562542bc6ebe6e7bd47890d8b7ca93c. First, the fix seems to be plain wrong, since the erratum suggests waiting 5ms before setting setting SYSCTL[RSTD], but this msleep() happens after the call of sdhci_reset() which is where that bit gets set (if SDHCI_RESET_DATA is in mask). Second, walking the whole device tree to figure out if some node has a "fsl,p2020-esdhc" compatible string is hugely expensive - about 70 to 100 us on our mpc8309 board. Walking the device tree is done under a raw_spin_lock, so this is obviously really bad on an -rt system, and a waste of time on all. In fact, since esdhc_reset() seems to get called around 100 times per second, that mpc8309 now spends 0.8% of its time determining that it is not a p2020. Whether those 100 calls/s are normal or due to some other bug or misconfiguration, regularly hitting a 100 us non-preemptible window is unacceptable. Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20191204085447.27491-1-linux@rasmusvillemoes.dk Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-16mmc: mediatek: fix CMD_TA to 2 for MT8173 HS200/HS400 modeChaotian Jing1-0/+2
there is a chance that always get response CRC error after HS200 tuning, the reason is that need set CMD_TA to 2. this modification is only for MT8173. Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Tested-by: Hsin-Yi Wang <hsinyi@chromium.org> Cc: stable@vger.kernel.org Fixes: 1ede5cb88a29 ("mmc: mediatek: Use data tune for CMD line tune") Link: https://lore.kernel.org/r/20191204071958.18553-1-chaotian.jing@mediatek.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-16mmc: sdhci-msm: Correct the offset and value for DDR_CONFIG registerVeerabhadrarao Badiganti1-9/+19
The DDR_CONFIG register offset got updated after a specific minor version of sdcc V4. This offset change has not been properly taken care of while updating register changes for sdcc V5. Correcting proper offset for this register. Also updating this register value to reflect the recommended RCLK delay. Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Link: https://lore.kernel.org/r/0101016ea738ec72-fa0f852d-20f8-474a-80b2-4b0ef63b132c-000000@us-west-2.amazonses.com Fixes: f15358885dda ("mmc: sdhci-msm: Define new Register address map") Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-12-16Revert "mmc: sdhci: Fix incorrect switch to HS mode"Faiz Abbas1-3/+1
This reverts commit c894e33ddc1910e14d6f2a2016f60ab613fd8b37. This commit aims to treat SD High speed and SDR25 as the same while setting UHS Timings in HOST_CONTROL2 which leads to failures with some SD cards in AM65x. Revert this commit. The issue this commit was trying to fix can be implemented in a platform specific callback instead of common sdhci code. Cc: <stable@vger.kernel.org> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20191128110422.25917-1-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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