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2022-12-06soc: qcom: socinfo: Add SM6115 / SM4250 SoC IDs to the soc_id tableBhupesh Sharma1-0/+4
Add SoC ID table entries for the SM6115 / SM4250 and variants. Cc: Bjorn Andersson <andersson@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221201141619.2462705-5-bhupesh.sharma@linaro.org
2022-12-06dt-bindings: arm: qcom,ids: Add SoC IDs for SM6115 / SM4250 and variantsBhupesh Sharma1-0/+4
Add SoC IDs for Qualcomm SM6115 / SM4250 and variants. Cc: Bjorn Andersson <andersson@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221201141619.2462705-4-bhupesh.sharma@linaro.org
2022-12-06soc: qcom: socinfo: Add SM8150 and SA8155 SoC IDs to the soc_id tableBhupesh Sharma1-0/+2
Add SoC ID table entries for the SM8150 and SA8155 SoCs. Cc: Bjorn Andersson <andersson@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221201141619.2462705-3-bhupesh.sharma@linaro.org
2022-12-06dt-bindings: arm: qcom,ids: Add SoC IDs for SM8150 and SA8155Bhupesh Sharma1-0/+2
Add SoC IDs for Qualcomm SM8150 and SA8155 SoCs. Cc: Bjorn Andersson <andersson@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221201141619.2462705-2-bhupesh.sharma@linaro.org
2022-12-06dt-bindings: soc: qcom: apr: document generic qcom,apr compatibleKrzysztof Kozlowski1-0/+1
Document the qcom,apr compatible, used by Qualcomm Asynchronous Packet Router driver. There are no upstream DTSes using this compatible - instead we have ones with APRv2 (qcom,apr-v2). The driver does not make distinction between both compatibles, which raises the question whether the compatible is really needed. Document it (as compatible with v2) for completeness. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221201133637.46146-1-krzysztof.kozlowski@linaro.org
2022-12-06soc: qcom: Select REMAP_MMIO for ICC_BWMON driverManivannan Sadhasivam1-0/+1
ICC_BWMON driver uses REGMAP_MMIO for accessing the hardware registers. So select the dependency in Kconfig. Without this, there will be errors while building the driver with COMPILE_TEST only: ERROR: modpost: "__devm_regmap_init_mmio_clk" [drivers/soc/qcom/icc-bwmon.ko] undefined! make[1]: *** [scripts/Makefile.modpost:126: Module.symvers] Error 1 make: *** [Makefile:1944: modpost] Error 2 Cc: <stable@vger.kernel.org> # 6.0 Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Fixes: b9c2ae6cac40 ("soc: qcom: icc-bwmon: Add bandwidth monitoring driver") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221129072022.41962-1-manivannan.sadhasivam@linaro.org
2022-12-06soc: qcom: Select REMAP_MMIO for LLCC driverManivannan Sadhasivam1-0/+1
LLCC driver uses REGMAP_MMIO for accessing the hardware registers. So select the dependency in Kconfig. Without this, there will be errors while building the driver with COMPILE_TEST only: ERROR: modpost: "__devm_regmap_init_mmio_clk" [drivers/soc/qcom/llcc-qcom.ko] undefined! make[1]: *** [scripts/Makefile.modpost:126: Module.symvers] Error 1 make: *** [Makefile:1944: modpost] Error 2 Cc: <stable@vger.kernel.org> # 4.19 Fixes: a3134fb09e0b ("drivers: soc: Add LLCC driver") Reported-by: Borislav Petkov <bp@alien8.de> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221129071201.30024-2-manivannan.sadhasivam@linaro.org
2022-12-06soc: qcom: rpmpd: Add SM4250 supportBhupesh Sharma1-0/+18
SM4250 has the same RPM power domains as SM6115. Add SM4250 support by reusing SM6115 power domains. Cc: Bjorn Andersson <andersson@kernel.org> Cc: Rajendra Nayak <rnayak@codeaurora.org> Cc: Konrad Dybcio <konrad.dybcio@somainline.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221127112204.1486337-3-bhupesh.sharma@linaro.org
2022-12-06dt-bindings: power: rpmpd: Add SM4250 supportBhupesh Sharma2-0/+11
Add compatible and constants for the power domains exposed by the SM4250 RPM. Cc: Bjorn Andersson <andersson@kernel.org> Cc: Rajendra Nayak <rnayak@codeaurora.org> Cc: Konrad Dybcio <konrad.dybcio@somainline.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221127112204.1486337-2-bhupesh.sharma@linaro.org
2022-12-06dt-bindings: soc: qcom: aoss: Add compatible for SM8550Abel Vesa1-0/+1
Document the compatible for SM8550. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116113128.2655441-1-abel.vesa@linaro.org
2022-12-06soc: qcom: llcc: Add configuration data for SM8550Abel Vesa2-0/+53
Add LLCC configuration data for SM8550 SoC. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116113005.2653284-4-abel.vesa@linaro.org
2022-12-06dt-bindings: arm: msm: Add LLCC compatible for SM8550Abel Vesa1-0/+1
Add LLCC compatible for SM8550 SoC. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116113005.2653284-3-abel.vesa@linaro.org
2022-12-06soc: qcom: llcc: Add v4.1 HW version supportAbel Vesa1-7/+118
The LLCC found in SM8550 supports more slice configuration knobs and HW block version has been bumped up to 4.1. Add support for the new version and make sure the new config values are programed on probe. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116113005.2653284-2-abel.vesa@linaro.org
2022-12-06soc: qcom: socinfo: Add SM8550 IDAbel Vesa2-0/+2
Add the ID for the Qualcomm SM8550 SoC. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116112438.2643607-1-abel.vesa@linaro.org
2022-12-06soc: qcom: rpmh-rsc: Avoid unnecessary checks on irq-done responseAbel Vesa4-37/+10
The RSC interrupt is issued only after the request is complete. For fire-n-forget requests, the irq-done interrupt is sent after issuing the RPMH request and for response-required request, the interrupt is triggered only after all the requests are complete. These unnecessary checks in the interrupt handler issues AHB reads from a critical path. Lets remove them and clean up error handling in rpmh_request data structures. Co-developed-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116112246.2640648-2-abel.vesa@linaro.org
2022-12-06soc: qcom: rpmh-rsc: Add support for RSC v3 register offsetsAbel Vesa2-58/+110
The SM8550 RSC has a new set of register offsets due to its version bump. So read the version from HW and use the proper register offsets based on that. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116112246.2640648-1-abel.vesa@linaro.org
2022-12-06soc: qcom: rpmhpd: Add SM8550 power domainsAbel Vesa1-0/+24
Add the power domains exposed by RPMH in the Qualcomm SM8550 platform. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116111745.2633074-3-abel.vesa@linaro.org
2022-12-06dt-bindings: power: rpmpd: Add SM8550 to rpmpd bindingAbel Vesa2-0/+17
Add compatible and constants for the power domains exposed by the RPMH in the Qualcomm SM8550 platform. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116111745.2633074-2-abel.vesa@linaro.org
2022-12-05soc: qcom: socinfo: Add MSM8956/76 SoC IDs to the soc_id tableAngeloGioacchino Del Regno1-0/+2
Add SoC ID table entries for MSM8956 and MSM8976 chips. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221111120156.48040-8-angelogioacchino.delregno@collabora.com
2022-12-05dt-bindings: arm: qcom,ids: Add SoC IDs for MSM8956 and MSM8976AngeloGioacchino Del Regno1-0/+2
Document the identifier of MSM8956/76. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221111120156.48040-7-angelogioacchino.delregno@collabora.com
2022-11-12dt-bindings: firmware: scm: add sdm670 compatibleRichard Acayan1-0/+1
The Snapdragon 670 uses SCM as for PSCI power management. Document the appropriate compatible string for it. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Guru Das Srinagesh <quic_gurus@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221111001818.124901-4-mailingradian@gmail.com
2022-11-10soc: qcom: rpmh-rsc: Write CONTROL_TCS with next timer wakeupMaulik Shah3-1/+67
The next wakeup timer value needs to be set in always on domain timer as the arch timer interrupt can not wakeup the SoC if after the deepest CPUidle states the SoC also enters deepest low power state. To wakeup the SoC in such scenarios the earliest wakeup time is set in CONTROL_TCS and the firmware takes care of setting up its own timer in always on domain with next wakeup time. The timer wakes up the RSC and sets resources back to wake state. Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450 Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221018152837.619426-7-ulf.hansson@linaro.org
2022-11-10soc: qcom: rpmh-rsc: Save base address of drvMaulik Shah2-10/+10
Add changes to save drv's base address for rsc. This is used to read drv's configuration such as solver mode is supported or to write into CONTROL_TCS registers. Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450 Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221018152837.619426-6-ulf.hansson@linaro.org
2022-11-10PM: domains: Store the next hrtimer wakeup in genpdMaulik Shah3-0/+36
The arch timer cannot wake up the Qualcomm Technologies, Inc. (QTI) SoCs from the deeper CPUidle states. To be able to wakeup from these deeper states, another always-on timer needs to be programmed through the so called CONTROL_TCS. As the RSC is part of CPU subsystem and the corresponding APSS RSC device is attached to the cluster PM domain (through genpd), it holds the responsibility to program the always-on timer, before entering any of these deeper CPUidle states. However, programming the timer requires information about the next hrtimer wakeup for the cluster PM domain, which is currently only known by genpd. Therefore, let's share this data through a new genpd helper function, dev_pm_genpd_get_next_hrtimer(). Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com> Cc: "Rafael J. Wysocki" <rafael@kernel.org> [Ulf: Reworked the code and updated the commit message] Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450 Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221018152837.619426-5-ulf.hansson@linaro.org
2022-11-10soc: qcom: rpmh-rsc: Attach RSC to cluster PM domainLina Iyer2-5/+66
RSC is part the CPU subsystem and powers off the CPU domains when all the CPUs and no RPMH transactions are pending from any of the drivers. The RSC needs to flush the 'sleep' and 'wake' votes that are critical for saving power when all the CPUs are in idle. Let's make RSC part of the CPU PM domains, by attaching it to the cluster power domain. Registering for PM domain notifications, RSC driver can be notified that the last CPU is powering down. When the last CPU is powering down the domain, let's flush the 'sleep' and 'wake' votes that are stored in the data buffers into the hardware and also write next wakeup in CONTROL_TCS. Signed-off-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450 Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221018152837.619426-3-ulf.hansson@linaro.org
2022-11-10dt-bindings: soc: qcom: Update devicetree binding document for rpmh-rscMaulik Shah1-0/+5
The change documents power-domains property for RSC device. This optional property points to corresponding PM domain node. Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450 Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221018152837.619426-2-ulf.hansson@linaro.org
2022-11-08dt-bindings: soc: qcom: qcom,smd-rpm: Use qcom,smd-channels on MSM8976AngeloGioacchino Del Regno1-0/+1
Like MSM8916 and some others, MSM8976 uses qcom,smd-channels and not qcom,glink-channels. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221104172122.252761-5-angelogioacchino.delregno@collabora.com
2022-11-08soc: qcom: apr: Add check for idr_alloc and of_property_read_string_indexJiasheng Jiang1-3/+12
As idr_alloc() and of_property_read_string_index() can return negative numbers, it should be better to check the return value and deal with the exception. Therefore, it should be better to use goto statement to stop and return error. Fixes: 6adba21eb434 ("soc: qcom: Add APR bus driver") Signed-off-by: Jiasheng Jiang <jiasheng@iscas.ac.cn> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221107014403.3606-1-jiasheng@iscas.ac.cn
2022-11-07soc: qcom: socinfo: Add QDU1000/QRU1000 SoC IDs to the soc_id tableMelody Olvera1-0/+6
Add SoC ID table entries for the QDU1000 and QRU1000 platforms and their variants. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221026190549.4005703-6-quic_molvera@quicinc.com
2022-11-07dt-bindings: arm: qcom,ids: Add SoC IDs for QDU1000/QRU1000Melody Olvera1-0/+6
Add SoC IDs for Qualcomm QDU1000 and QRU1000 platforms and their variants. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221026190549.4005703-5-quic_molvera@quicinc.com
2022-11-07soc: qcom: rpmhpd: Add QDU1000/QRU1000 power domainsMelody Olvera1-0/+14
Add the power domains exposed by RPMH in the Qualcomm QDU1000 and QRU1000 platforms. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221026190549.4005703-4-quic_molvera@quicinc.com
2022-11-07dt-bindings: power: rpmpd: Add QDU1000/QRU1000 to rpmpd bindingMelody Olvera2-0/+7
Add compatible and constants for the power domains exposed by the RPMH in the Qualcomm QDU1000 and QRU1000 platforms. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221026190549.4005703-3-quic_molvera@quicinc.com
2022-11-07dt-bindings: qcom: smp2p: Add WPSS node names to pattern propertyManikanta Pubbisetty1-1/+1
WLAN firmware uses SMP2P protocol in order to talk to the application processor (AP) in certain cases like WoW (Wake on Wireless). WLAN firmware runs on the WPSS Q6 processor (Wireless Processor SubSystem). Therefore it is required to have sub nodes pertaining to the WPSS Q6 processor and the application processor in the SMP2P node. Add WPSS Q6 (Wireless Processor SubSystem) node names to the pattern property required for WPSS Q6 processor to communicate to the application processor and vice versa over SMP2P protocol. Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221017125346.3691-2-quic_mpubbise@quicinc.com
2022-11-06soc: qcom: spm: Implement support for SAWv2.3, MSM8976 L2 PMAngeloGioacchino Del Regno1-0/+33
Implement the support for SAW v2.3, used in at least MSM8976, MSM8956 and APQ variants and while at it also add the configuration for the MSM8976's little (a53) and big (a72) clusters cache power management. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> [Marijn: reorder struct definitions to follow high-to-low order] Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221104133452.131227-3-angelogioacchino.delregno@collabora.com
2022-11-06dt-bindings: soc: qcom: spm: Add compatibles for MSM8976 L2AngeloGioacchino Del Regno1-0/+2
Add SPM AVS Wrapper 2 compatibles for MSM8976's L2 cache. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221104133452.131227-2-angelogioacchino.delregno@collabora.com
2022-11-06soc: qcom: llcc: make irq truly optionalLuca Weiss1-1/+1
The function platform_get_irq prints an error message into the kernel log when the irq isn't found. Since the interrupt is actually optional and not provided by some SoCs, use platform_get_irq_optional which does not print an error message. Fixes: c081f3060fab ("soc: qcom: Add support to register LLCC EDAC driver") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221104153041.412020-1-luca.weiss@fairphone.com
2022-11-06soc: qcom: spm: Add MSM8939 SPM register dataVincent Knecht1-0/+13
Add SPM register information and initialization values for QCOM MSM8939 SoC. Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221019171004.1080911-2-vincent.knecht@mailoo.org
2022-11-06dt-bindings: soc: qcom: spm: Add MSM8939 CPU compatibleVincent Knecht1-0/+1
Document the "qcom,msm8939-saw2-v3.0-cpu" compatible for the CPU Subsystem Power Manager (SPM) on the MSM8939 SoC. Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221019171004.1080911-1-vincent.knecht@mailoo.org
2022-10-18dt-bindings: soc: qcom: aoss: Add sc8280xp compatibleLuca Weiss1-0/+1
Document the aoss-qmp compatible for sc8280xp. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221016090035.565350-4-luca@z3ntu.xyz
2022-10-18dt-bindings: firmware: document Qualcomm SM6375 SCMKonrad Dybcio1-0/+2
Document the compatible for Qualcomm SM6375 SCM. SCM consumes a single clock (core / RPM_SMD_CE1_CLK), though it does not matter whether Linux enables it, as one of the billion levels of firmware ensures it's on anyway. Still, mark it as used for the sake of correctness. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221015115535.150037-1-konrad.dybcio@somainline.org
2022-10-18soc: qcom: stats: Mark device as having no PM supportStephen Boyd1-0/+2
This driver purely exposes information from memory to the kernel. Let's mark it as not having any device PM functionality, so that during suspend we skip even trying to call a suspend function on this device. This clears up suspend logs more than anything else, but it also shaves a few cycles off suspend. Cc: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221015004934.3930651-2-swboyd@chromium.org
2022-10-18soc: qcom: cmd-db: Mark device as having no PM supportStephen Boyd1-0/+2
This driver purely exposes information from memory to the kernel. Let's mark it as not having any device PM functionality, so that during suspend we skip even trying to call a suspend function on this device. This clears up suspend logs more than anything else, but it also shaves a few cycles off suspend. Cc: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221015004934.3930651-1-swboyd@chromium.org
2022-10-17soc: qcom: spmi-pmic: add more PMIC SUBTYPE IDsLuca Weiss1-0/+11
Add more IDs that are found in the downstream msm-4.19 kernel under the path include/linux/qpnp/qpnp-revid.h. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220922082925.17975-2-luca.weiss@fairphone.com
2022-10-17soc: qcom: spmi-pmic: convert hex numbers to lowercaseLuca Weiss1-3/+3
There are some IDs that are written in uppercase. For consistency convert them to lowercase. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220922082925.17975-1-luca.weiss@fairphone.com
2022-10-17soc: qcom: pdr: Make QMI message rules constJeff Johnson1-10/+10
Commit ff6d365898d4 ("soc: qcom: qmi: use const for struct qmi_elem_info") allows QMI message encoding/decoding rules to be const, so do that for QCOM PDR. Signed-off-by: Jeff Johnson <quic_jjohnson@quicinc.com> Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220914234705.28405-5-quic_jjohnson@quicinc.com
2022-10-17soc: qcom: rpmhpd: Use highest corner until sync_stateBjorn Andersson1-1/+38
In some cases the hardware that the bootloader has left configured depends on RPMH power domains for their operation up until the point where the related Linux device driver probes and can inherit that configuration, or power down the hardware gracefully. Unfortunately as Linux probes the releavant drivers in sequence there are periods during the Linux boot flow where either the genpd refcount will reach 0, or worse where the active performance_state votes does not meet the requirements of the state that the hardware was left in. One specific example of this is during boot of e.g. SM8150/SC8180X, where the display clock controller probes, without any particular performance state needs (to access its registers). This will drop the MMCX rail to MIN_SVS, which isn't sufficient to sustain the clock rates that the later probing MDP is configured to. This results in an unrecoverable system state. Handle both these cases by keeping the RPMH power-domais that are referenced voted for highest state, until sync_state indicates that all devices referencing the RPMH power-domain driver has been probed. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Caleb Connolly <caleb@connolly.tech> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> [bjorn: Added print for sync_state errors] Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220915205559.14574-1-quic_bjorande@quicinc.com
2022-10-17soc: qcom: smd-rpm: Add SM6375 compatibleKonrad Dybcio1-0/+1
Add a compatible for the SM6375 SoC. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220921004534.151990-2-konrad.dybcio@somainline.org
2022-10-17dt-bindings: soc: qcom: qcom,smd-rpm: Add a compatible for SM6375Konrad Dybcio1-0/+1
Document the compatible for SM6375. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220921004534.151990-1-konrad.dybcio@somainline.org
2022-10-17dt-bindings: soc: qcom: smd-rpm: add qcom,glink-channelsKrzysztof Kozlowski1-4/+17
The Qualcomm Resource Power Manager (RPM) over SMD bindings contain compatibles and description for RPM devices on two different communication channels: SMD and GLINK. Except the difference in the parent node, they use different properties for describing name of channel qcom,smd-channels or qcom,glink-channels. The first one is already present but second is missing: qcom/sm6125-sony-xperia-seine-pdx201.dtb: rpm-requests: 'qcom,glink-channels' does not match any of the regexes: '^regulators(-[01])?$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220926092104.111449-2-krzysztof.kozlowski@linaro.org
2022-10-17dt-bindings: soc: qcom: smd-rpm: add PMIC regulators nodesKrzysztof Kozlowski1-0/+5
The Qualcomm RPM over SMD contains devices for one or two PMIC regulators - already used in several DTS files. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220926092104.111449-1-krzysztof.kozlowski@linaro.org
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