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2021-12-27phy: cadence: Sierra: Fix to get correct parent for mux clocksSwapnil Jakhade1-5/+26
Fix get_parent() callback to return the correct index of the parent for PLL_CMNLC1 clock. Add a separate table of register values corresponding to the parent index for PLL_CMNLC1. Update set_parent() callback accordingly. Fixes: 28081b72859f ("phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)") Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-12-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-27phy: cadence: Sierra: Update single link PCIe register configurationSwapnil Jakhade1-1/+213
Add single link PCIe register configurations for no SSC and internal SSC. Also, add missing PMA lane registers for external SSC. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-11-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-27phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operationSwapnil Jakhade1-1/+72
PIPE phy status is used to communicate the completion of several PHY functions. Check if PHY is ready for operation while configured for PIPE mode during startup. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-10-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-27phy: cadence: Sierra: Check cmn_ready assertion during PHY power onSwapnil Jakhade1-0/+45
Check if PMA cmn_ready is set indicating the startup process is complete. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-9-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-27phy: cadence: Sierra: Add PHY PCS common register configurationsSwapnil Jakhade1-0/+38
Add PHY PCS common register configuration sequences for single link. Update single link PCIe register sequence accordingly. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-8-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-27phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra ↵Swapnil Jakhade1-10/+11
documentation No functional change. Rename some regmap variables as mentioned in Sierra register description documentation. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-7-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-27phy: cadence: Sierra: Add support to get SSC type from device treeSwapnil Jakhade1-1/+5
Add support to get SSC type from DT. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-6-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-27dt-bindings: phy: cadence-sierra: Add binding to specify SSC modeSwapnil Jakhade1-0/+9
Add binding to specify Spread Spectrum Clocking mode used. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211223060137.9252-5-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-27dt-bindings: phy: cadence-torrent: Rename SSC macros to use generic namesSwapnil Jakhade2-6/+6
Rename SSC macros to use generic names instead of PHY specific names, so that they can be used to specify SSC modes for both Torrent and Sierra. Renaming the macros should not affect the things as these are not being used in any DTS file yet. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211223060137.9252-4-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-27phy: cadence: Sierra: Prepare driver to add support for multilink configurationsSwapnil Jakhade1-56/+139
Sierra driver currently supports single link configurations only. Prepare driver to support multilink multiprotocol configurations along with different SSC modes. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-3-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-27phy: cadence: Sierra: Use of_device_get_match_data() to get driver dataSwapnil Jakhade1-9/+4
Use of_device_get_match_data() to get driver data instead of boilerplate code. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-2-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-27phy: mediatek: Fix missing check in mtk_mipi_tx_probeMiaoqian Lin1-0/+2
The of_device_get_match_data() function may return NULL. Add check to prevent potential null dereference. Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20211224082103.7658-1-linmq006@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-24phy: uniphier-usb3ss: fix unintended writing zeros to PHY registerRyuta NAKANISHI1-4/+6
Similar to commit 4a90bbb478db ("phy: uniphier-pcie: Fix updating phy parameters"), in function uniphier_u3ssphy_set_param(), unintentionally write zeros to other fields when writing PHY registers. Fixes: 5ab43d0f8697 ("phy: socionext: add USB3 PHY driver for UniPhier SoC") Signed-off-by: Ryuta NAKANISHI <nakanishi.ryuta@socionext.com> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1640150369-4134-1-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-24phy: phy-mtk-tphy: use new io helpers to access registerChunfeng Yun1-325/+179
Use new helpers mtk_phy_clear/set/update_bits() to access registers Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20211218082802.5256-5-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-24phy: phy-mtk-xsphy: use new io helpers to access registerChunfeng Yun1-94/+46
Use new helpers mtk_phy_clear/set/update_bits() to access registers Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20211218082802.5256-4-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-24phy: mediatek: add helpers to update bits of registersChunfeng Yun1-0/+38
Add three helpers mtk_phy_clear/set/update_bits() for registers operation Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20211218082802.5256-3-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-24phy: phy-mtk-tphy: add support efuse settingChunfeng Yun1-0/+162
Due to some SoCs have a bit shift issue that will drop a bit for usb3 phy or pcie phy, fix it by adding software efuse reading and setting, but only support it optionally for version 2/3. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20211218082802.5256-2-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-24dt-bindings: phy: mediatek: tphy: support software efuse loadChunfeng Yun1-0/+18
Add optional property nvmem-cells and nvmem-cell-names to support software efuse load, this helps to fix the efuse bit shift issue on mt8195 etc. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20211218082802.5256-1-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-24phy: qcom-qmp: Add SM8450 PCIe1 PHY supportDmitry Baryshkov2-0/+223
There are two different PCIe PHYs on SM8450, one having one lane (v5) and another with two lanes (v5.20). This commit adds support for the second PCIe phy. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211218141754.503661-3-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-24dt-bindings: phy: qcom,qmp: Add SM8450 PCIe PHY bindingsDmitry Baryshkov1-0/+2
There are two different PCIe PHYs on SM8450, one having one lane and another with two lanes. Add support for second (gen4, two lanes) PHY. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211218141754.503661-2-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-23phy: phy-rockchip-inno-usb2: add rk3568 supportPeter Geis1-0/+65
The rk3568 usb2phy is a standalone device with a single muxed interrupt. Add support for the registers to the usb2phy driver. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20211215210252.120923-7-pgwipeout@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-23phy: phy-rockchip-inno-usb2: support muxed interruptsPeter Geis1-49/+119
The rk3568 usb2phy has a single muxed interrupt that handles all interrupts. Allow the driver to plug in only a single interrupt as necessary. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20211215210252.120923-6-pgwipeout@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-23phy: phy-rockchip-inno-usb2: support standalone phy nodesPeter Geis1-5/+12
New Rockchip devices have the usb2 phy devices as standalone nodes instead of children of the grf node. Allow the driver to find the grf node from a phandle. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20211215210252.120923-5-pgwipeout@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-23phy: phy-rockchip-inno-usb2: support #address_cells = 2Peter Geis1-1/+10
New Rockchip devices have the usb phy nodes as standalone devices. These nodes have register nodes with #address_cells = 2, but only use 32 bit addresses. Adjust the driver to check if the returned address is "0", and adjust the index in that case. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20211215210252.120923-4-pgwipeout@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-23dt-bindings: phy: phy-rockchip-inno-usb2: add rk3568 documentationPeter Geis1-4/+40
The rk3568 usb2phy node is a standalone node with a single muxed interrupt. Add documentation for it to phy-rockchip-inno-usb2. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211215210252.120923-3-pgwipeout@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-18phy: qcom-qmp: Add SM8450 PCIe0 PHY supportDmitry Baryshkov2-0/+158
There are two different PCIe PHYs on SM8450, one having one lane (v5) and another with two lanes (v5.20). This commit adds support for the first PCIe phy only, support for the second PCIe PHY is coming in next commits. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211214225846.2043361-4-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-18dt-bindings: phy: qcom,qmp: Add SM8450 PCIe PHY bindingsDmitry Baryshkov1-0/+2
There are two different PCIe PHYs on SM8450, one having one lane and another with two lanes. Add DT bindings for the first one. Support for second PCIe host and PHY will be submitted separately. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211214225846.2043361-3-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-16phy: qcom-qmp: Add SM8450 USB QMP PHYsVinod Koul1-0/+3
Add support for the USB DP & UNI PHYs found on SM8450. This is same as the phy version used on SM8350 and sequences turned out to be same, so use the same table from SM8350 for this as well. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211213131450.535775-3-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-16dt-bindings: phy: qcom,qmp: Add SM8450 USB3 PHYVinod Koul1-0/+1
Add compatible string for USB QMP phy in Qualcomm SM8450 SoC Signed-off-by: Vinod Koul <vkoul@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211213131450.535775-2-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-16dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for SM8450Vinod Koul1-0/+1
Document the compatible string for USB phy found in Qualcomm SM8450 SoC Signed-off-by: Vinod Koul <vkoul@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211213131450.535775-1-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-15phy: freescale: pcie: explicitly add bitfield.hVinod Koul1-0/+1
kernel test robot complains about missing FIELD_PREP, so include bitfield.h for that drivers/phy/freescale/phy-fsl-imx8m-pcie.c:41:37: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration] drivers/phy/freescale/phy-fsl-imx8m-pcie.c:41:41: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration] Reported-by: kernel test robot <lkp@intel.com> Fixes: 1aa97b002258 ("phy: freescale: pcie: Initialize the imx8 pcie standalone phy driver") Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com> Link: https://lore.kernel.org/r/20211215060834.921617-1-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-14phy: freescale: pcie: Initialize the imx8 pcie standalone phy driverRichard Zhu3-0/+245
Add the standalone i.MX8 PCIe PHY driver. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Tim Harvey <tharvey@gateworks.com> Tested-by: Tim Harvey <tharvey@gateworks.com> Link: https://lore.kernel.org/r/1638432158-4119-6-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-14dt-bindings: phy: Add imx8 pcie phy driver supportRichard Zhu1-0/+92
Add dt-binding for the standalone i.MX8 PCIe PHY driver. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Tim Harvey <tharvey@gateworks.com> Tested-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1638432158-4119-3-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-14dt-bindings: phy: phy-imx8-pcie: Add binding for the pad modes of imx8 pcie phyRichard Zhu1-0/+14
Add binding for reference clock PAD modes of the i.MX8 PCIe PHY. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Tim Harvey <tharvey@gateworks.com> Tested-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1638432158-4119-2-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-14phy: rockchip-inno-usb2: remove redundant assignment to variable delayColin Ian King1-1/+0
Variable delay is being assigned to zero and the code falls through to the next case in a switch statement that returns out of the function. The variable is never read in this scenario and so the assignment is redundant and can be removed. Cleans up scan-build static analysis warning: drivers/phy/rockchip/phy-rockchip-inno-usb2.c:753:3: warning: Value stored to 'delay' is never read [deadcode.DeadStores] Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Link: https://lore.kernel.org/r/20211211180054.525368-1-colin.i.king@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-14phy: lan966x: Remove set_speed functionHoratiu Vultur1-12/+5
Remove the set_speed function and allow the driver to figure out the speed at which needs to configure the serdes based on the interface type. Fixes: 305524902a0045 ("phy: Add lan966x ethernet serdes PHY driver") Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Link: https://lore.kernel.org/r/20211211214717.1284306-1-horatiu.vultur@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-14phy: ti: Use IS_ERR_OR_NULL() to clean codeMiaoqian Lin1-3/+3
Use IS_ERR_OR_NULL() to make the code cleaner. Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Link: https://lore.kernel.org/r/20211212142226.23674-1-linmq006@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-14dt-bindings: phy: qcom,qusb2: Add SM6350 compatibleLuca Weiss1-0/+1
Add devicetree compatible for the usb phy on SM6350 SoC. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Acked-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20211213082614.22651-5-luca.weiss@fairphone.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-14phy: tegra: xusb: Fix return value of tegra_xusb_find_port_node functionMiaoqian Lin1-1/+1
callers of tegra_xusb_find_port_node() function only do NULL checking for the return value. return NULL instead of ERR_PTR(-ENOMEM) to keep consistent. Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20211213020507.1458-1-linmq006@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-09phy: qcom: use struct_size instead of sizeofGuo Zhengkui1-1/+1
Use struct_size() to get the accurate size of `clk_hw_onecell_data` with a variable size array, instead of sizeof(data) to get the size of a pointer. Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Guo Zhengkui <guozhengkui@vivo.com> Fixes: f199223cb490 ("phy: qcom: Introduce new eDP PHY driver") Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211209032114.9416-1-guozhengkui@vivo.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-07phy: qcom-qmp: Add SM8450 UFS QMP PhyVinod Koul1-0/+32
SM8450 UFS seems to use same sequence as SM8350, so reuse the sequence from SM8450. Add the new clock list for this phy and the new compatible Signed-off-by: Vinod Koul <vkoul@kernel.org> Co-developed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Martin K. Petersen <martin.petersen@oracle.com> Link: https://lore.kernel.org/r/20211201074456.3969849-4-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-07dt-bindings: phy: qcom,qmp: Add SM8450 UFS phy compatibleVinod Koul1-0/+1
Document the UFS phy compatible for QMP UFS phy found in SM8450 SoC. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Martin K. Petersen <martin.petersen@oracle.com> Link: https://lore.kernel.org/r/20211201074456.3969849-3-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-07scsi: ufs: dt-bindings: Add SM8450 compatible stringsVinod Koul1-0/+1
Document "qcom,sm8450-ufshc" compatible string. "qcom,sm8450-ufshc" is for UFS HC found in SM8450 SoC. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Martin K. Petersen <martin.petersen@oracle.com> Link: https://lore.kernel.org/r/20211201074456.3969849-2-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-02phy: lan966x: Extend lan966x to support multiple phy interfaces.Horatiu Vultur1-0/+4
Currently the driver is supporting only the interfaces QSGMII, SGMII, RGMII and GMII. This patch extend the supported interfaces with 1000BASE-X and 2500BASE-X. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Acked-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://lore.kernel.org/r/20211130101015.164916-1-horatiu.vultur@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-02phy: intel: Remove redundant dev_err call in thunderbay_emmc_phy_probe()Zou Wei1-3/+1
There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zou Wei <zou_wei@huawei.com> Link: https://lore.kernel.org/r/1637822289-24534-1-git-send-email-zou_wei@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-11-26phy: stm32: adopt dev_err_probe for regulatorsFabrice Gasnier1-6/+4
Change stm32-usbphyc driver to use dev_err_probe(), to benefit of devices_deferred debugfs in case of probe deferral. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Reviewed-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/1635172265-26219-1-git-send-email-fabrice.gasnier@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-11-25phy: bcm-ns-usb2: improve printing ref clk errorsRafał Miłecki1-1/+1
Improve message & use dev_err_probe() helper which prints actual error (helpful for debugging) and deals with -EPROBE_DEFER. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20211123221521.25323-1-zajec5@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-11-23phy: intel: Add Thunder Bay eMMC PHY supportRashmi A3-0/+522
Add support of eMMC PHY for Intel Thunder Bay SoC, uses the Arasan eMMC phy Signed-off-by: Rashmi A <rashmi.a@intel.com> Reviewed-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20211027115516.4475-5-rashmi.a@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-11-23dt-bindings: phy: intel: Add Thunder Bay eMMC PHY bindingsRashmi A2-0/+53
Binding description for Intel Thunder Bay eMMC PHY. Added the newly introduced files into MAINTAINERS file-list Signed-off-by: Rashmi A <rashmi.a@intel.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211027115516.4475-4-rashmi.a@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-11-23phy: Add lan966x ethernet serdes PHY driverHoratiu Vultur4-0/+766
Add the Microchip lan966x ethernet serdes PHY driver for interfaces available in the lan966x SoC. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Link: https://lore.kernel.org/r/20211116100818.1615762-4-horatiu.vultur@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-04-30 02:22:27 +0300