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AgeCommit message (Expand)AuthorFilesLines
2013-01-31drm/i915: remove intel_gtt structureBen Widawsky5-54/+33
2013-01-31drm/i915: Add probe and remove to the gtt opsBen Widawsky3-79/+114
2013-01-31drm/i915: extract hw ppgtt setup/cleanup codeDaniel Vetter2-24/+45
2013-01-31drm/i915: pte_encode is gen6+Daniel Vetter1-10/+14
2013-01-31drm/i915: vfuncs for ppgttDaniel Vetter2-56/+65
2013-01-31drm/i915: vfuncs for gtt_clear_range/insert_entriesDaniel Vetter2-59/+83
2013-01-31drm/i915: Error state should print /sys/kernel/debugBen Widawsky1-1/+2
2013-01-31drm/i915: move DP save/restore into i915_ums.cDaniel Vetter2-28/+25
2013-01-31drm/i915: dont save/restore VGA state for kmsDaniel Vetter3-23/+28
2013-01-31drm/i915: extract ums suspend/resume into i915_ums.cDaniel Vetter4-452/+485
2013-01-29drm/i915: move modeset checks out of save/restore_modeset_regDaniel Vetter1-23/+15
2013-01-28drm/i915: Implement WaVSRefCountFullforceMissDisableBen Widawsky2-0/+5
2013-01-28drm/i915: turn on the power well before suspendingPaulo Zanoni3-1/+4
2013-01-28drm/i915: set TRANSCODER_EDP even earlierPaulo Zanoni1-5/+5
2013-01-26drm/i915: only disable enabled planes on intel_fb_restore_modePaulo Zanoni1-1/+2
2013-01-26drm/i915: fix intel_init_power_wellsPaulo Zanoni4-26/+46
2013-01-26drm/i915: SWF screatch registers need an offset on VLVVille Syrjälä1-13/+13
2013-01-26drm/i915: Include display_mmio_offset in sequencer index/data registersVille Syrjälä1-2/+8
2013-01-26drm/i915: Pass VLV_DISPLAY_BASE + reg to intel_{hdmi, dp}_init on VLVVille Syrjälä1-8/+8
2013-01-26drm/i915: VLV doesn't have SDVOVille Syrjälä1-7/+2
2013-01-26drm/i915: Always use adpa_regVille Syrjälä1-14/+15
2013-01-26drm/i915: PLL registers need an offset on VLVVille Syrjälä1-4/+4
2013-01-25drm/i915: Set display_mmio_offset for VLVVille Syrjälä1-0/+2
2013-01-25drm/i915: GPIO/GMBUS registers need an offset on VLVVille Syrjälä1-0/+2
2013-01-25drm/i915: DPIO registers are VLV only and need an offsetVille Syrjälä1-4/+6
2013-01-25drm/i915: Spell out VLV_DISPLAY_BASE for interrupt registersVille Syrjälä1-5/+5
2013-01-25drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readableVille Syrjälä1-1/+1
2013-01-25drm/i915: FB_BLC_SELF_VLV is VLV only and needs an offsetVille Syrjälä1-1/+1
2013-01-25drm/i915: Pipe palette registers need an offset on VLVVille Syrjälä1-2/+2
2013-01-25drm/i915: Pipe timing registers need an offset on VLVVille Syrjälä1-18/+18
2013-01-25drm/i915: PORT_HOTPLUG registers need an offset on VLVVille Syrjälä1-2/+2
2013-01-25drm/i915: Panel fitter registers need an offset on VLVVille Syrjälä1-3/+3
2013-01-25drm/i915: DPFLIPSTAT and DPINVGTT registers are VLV only and need an offsetVille Syrjälä1-2/+2
2013-01-25drm/i915: DSPFW registers need an offset on VLVVille Syrjälä1-3/+3
2013-01-25drm/i915: VLV_DDL is VLV only and needs an offsetVille Syrjälä1-2/+2
2013-01-25drm/i915: Cursor registers need an offset on VLVVille Syrjälä1-6/+6
2013-01-25drm/i915: Pipe registers need an offset on VLVVille Syrjälä1-10/+10
2013-01-25drm/i915: Primary plane registers need an offset on VLVVille Syrjälä1-18/+18
2013-01-25drm/i915: PIPE M/N registers need an offset on VLVVille Syrjälä1-16/+16
2013-01-25drm/i915: VLV_VIDEO_DIP_CTL is for VLV onlyVille Syrjälä1-6/+6
2013-01-25drm/i915: Per-pipe PP registers are for VLV onlyVille Syrjälä1-11/+11
2013-01-25drm/i915: AUD_VID_DID needs an offset on VLVVille Syrjälä1-1/+1
2013-01-25drm/i915: Add display_display_mmio_offset to intel_device_infoVille Syrjälä1-0/+1
2013-01-25drm/i915: Convert intel_dp to enum portVille Syrjälä1-4/+5
2013-01-25drm/i915: Convert intel_hdmi to enum portVille Syrjälä1-12/+15
2013-01-24drm/i915: don't save/restore DSPARB on gen5+Paulo Zanoni1-2/+4
2013-01-23drm/i915: fixup sbi_read/write lockingDaniel Vetter1-0/+4
2013-01-22drm/i915: HDMI/DP - ELD info refresh support for HaswellWang Xingchao3-0/+26
2013-01-22drm/i915: use gem_set_seqno() on hardware initMika Kuoppala2-4/+4
2013-01-22drm/i915: add quirk to invert brightness on Packard Bell NCL20Jani Nikula1-0/+3