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2016-07-18mtd: update description of MTD_BCM47XXSFLASH symbolRafał Miłecki1-2/+2
For years now we support writing to BCMA SoC serial flash, so don't describe this driver as providing read-only support anymore. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-07-18mtd: spi-nor: Add driver for Cadence Quad SPI Flash ControllerGraham Moore3-0/+1311
Add support for the Cadence QSPI controller. This controller is present in the Altera SoCFPGA SoCs and this driver has been tested on the Cyclone V SoC. Signed-off-by: Graham Moore <grmoore@opensource.altera.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alan Tull <atull@opensource.altera.com> Cc: Brian Norris <computersforpeace@gmail.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Graham Moore <grmoore@opensource.altera.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Yves Vandervennet <yvanderv@opensource.altera.com> Cc: devicetree@vger.kernel.org Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-07-18mtd: spi-nor: Bindings for Cadence Quad SPI Flash Controller driverGraham Moore1-0/+56
Add binding document for the Cadence QSPI controller. Signed-off-by: Graham Moore <grmoore@opensource.altera.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alan Tull <atull@opensource.altera.com> Cc: Brian Norris <computersforpeace@gmail.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Graham Moore <grmoore@opensource.altera.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Yves Vandervennet <yvanderv@opensource.altera.com> Cc: devicetree@vger.kernel.org Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-07-17mtd: nand: brcmnand: Change BUG_ON in brcmnand_send_cmdFlorian Fainelli1-1/+1
Change the BUG_ON() condition in brcmnand_send_cmd() which checks for the interrupt status "controller ready" bit to a WARN_ON. There is no good reason to kill the system when this condition occur because we could have systems which listed the NAND controller as available (e.g: from Device Tree), but the NAND chip could be malfunctioning and not responding. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-07-16mtd: pmcmsp-flash: Allocating too much in init_msp_flash()Dan Carpenter1-3/+3
There is a cut and paste issue here. The bug is that we are allocating more memory than necessary for msp_maps. We should be allocating enough space for a map_info struct (144 bytes) but we instead allocate enough for an mtd_info struct (1840 bytes). It's a small waste. The other part of this is not harmful but when we allocated msp_flash then we allocated enough space fro a map_info pointer instead of an mtd_info pointer. But since pointers are the same size it works out fine. Anyway, I decided to clean up all three allocations a bit to make them a bit more consistent and clear. Fixes: 68aa0fa87f6d ('[MTD] PMC MSP71xx flash/rootfs mappings') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-07-16mtd: maps: sa1100-flash: potential NULL dereferenceDan Carpenter1-1/+3
We check for NULL but then dereference "info->mtd" on the next line. Fixes: 72169755cf36 ('mtd: maps: sa1100-flash: show parent device in sysfs') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-07-16mtd: atmel-quadspi: add driver for Atmel QSPI controllerCyrille Pitchen3-0/+742
This driver add support to the new Atmel QSPI controller embedded into sama5d2x SoCs. It expects a NOR memory to be connected to the QSPI controller. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-07-16mtd: nand: omap2: fix return value check in omap_nand_probe()Wei Yongjun1-2/+2
In case of error, the function dma_request_chan() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Fixes: aa7abd312c11 ('mtd: nand: omap2: Support parsing dma channel information from DT') Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-07-16Merge tag 'nand/for-4.8' of github.com:linux-nand/linux into mtdBrian Norris19-124/+2981
Pull NAND changes from Boris Brezillon: """ This pull request contains only one notable change: * Addition of the MTK NAND controller driver And a bunch of specific NAND driver improvements/fixes. Here are the changes that are worth mentioning: * A few fixes/improvements for the xway NAND controller driver * A few fixes for the sunxi NAND controller driver * Support for DMA in the sunxi NAND driver * Support for the sunxi NAND controller IP embedded in A23/A33 SoCs * Addition for bitflips detection in erased pages to the brcmnand driver * Support for new brcmnand IPs * Update of the OMAP-GPMC binding to support DMA channel description """
2016-07-14Documentation: atmel-quadspi: add binding file for Atmel QSPI driverCyrille Pitchen1-0/+32
This patch documents the DT bindings for the driver of the Atmel QSPI controller embedded inside sama5d2x SoCs. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-07-14mtd: spi-nor: add hisilicon spi-nor flash controller driverJiancheng Xue4-0/+521
Add hisilicon spi-nor flash controller driver Signed-off-by: Binquan Peng <pengbinquan@hisilicon.com> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-07-14mtd: spi-nor: support dual, quad, and WP for GigadeviceBrian Norris1-4/+20
Gigadevice flash support BP{0,1,2,3,4} bits, where BP3 means the same as the existing supported TB (Top/Bottom), and BP4 means the same as the not-yet-supported 4K bit used on other flash (e.g., Winbond). Let's support lock/unlock with the same feature flags as w25q32dw/w25q64dw. Tested on gd25lq64c, but I checked datasheets for the other 3, to make sure. While I was at it, I noticed that these all support dual and quad as well. I noted them, but can't test them at the moment, since my test system only supports standard 1x SPI. Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-07-14mtd: spi-nor: Added support for n25q00a.P L Sai Krishna1-0/+1
Add Micron (n25q00a) 1Gbit NOR Flash in the list of supported devices. This part is different from n25q00 in Memory Type. Memory Type for n25q00 - BAh Memory Type for n25q00a - BBh Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-07-14memory: Update dependency of IFC for LayerscapeRaghav Dogra3-3/+5
This patch enables IFC NAND support on ARM layerscape platform. It fixes the dependency to enable NAND. The include files are being modified to ensure complilation for both PowerPC and ARM architectures. Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Acked-by: Scott Wood <oss@buserror.net> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-07-11mtd: nand: jz4780: Update MODULE_AUTHOR email addressHarvey Hunt2-2/+2
Emails will bounce from my imgtec address, so update it to a new one. Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com> Cc: Harvey Hunt <harveyhuntnexus@gmail.com> Cc: linux-mtd@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-07-11mtd: nand: sunxi: prevent a small memory leakDan Carpenter1-3/+3
I moved the sanity check on ecc->size before the allocation so that we don't leak memory on error. Fixes: 05af074a4b73 ('mtd: nand: sunxi: check ecc->size values') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-07-11mtd: nand: sunxi: add reset line supportIcenowy Zheng1-2/+23
The NAND controller on some sun8i chips needs its reset line to be deasserted before they can enter working state. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-07-11mtd: nand: sunxi: update DT bindingsIcenowy Zheng1-0/+2
Document the reset lines Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-07-11mtd: nand: xway: add nandaddr to own structHauke Mehrtens1-16/+14
Instead of using IO_ADDR_W and IO_ADDR_R use an own pointer to the NAND controller memory area. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-07-11mtd: nand: xway: add missing write_buf and read_buf to nand driverHauke Mehrtens1-0/+18
This driver needs a special write_buf and read_buf function, because we have to read from a specific address to tell the controller this is a read from the nand controller. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-07-11mtd: nand: xway: extract read and write functionHauke Mehrtens1-9/+19
Extract the functions to read and write to the register of the NAND flash controller. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-07-11mtd: nand: xway: fix nand lockingJohn Crispin1-12/+8
The external Bus Unit (EBU) can control different flash devices, but these NAND flash commands have to be atomic and should not be interrupted in between. Lock the EBU from the beginning of the command till the end by moving the lock to the chip select. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-07-11mtd: nand: xway: remove manual resetHauke Mehrtens1-20/+0
nand_scan() already resets the NAND flash chip, this driver does not have to call it manually. The xway_reset_chip() functions does the same as the normal NAND reset function. The waiting for the NAND_WAIT_WR_C is done in xway_cmd_ctrl(). Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-07-11mtd: nand: xway: Avoid messing up with IO_ADDR_W in ->cmd_ctrl()John Crispin1-15/+11
The ->cmd_ctrl() function is adjusting the ->IO_ADDR_W value depending on the command type each time NAND_CTRL_CHANGE is passed. This is not only useless but can lead to an ->IO_ADDR_W corruption. Get rid of this logic and rely on the NAND_CLE and NAND_ALE flags to deduce the iomem address to write the cmd argument to. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-07-11mtd: nand: xway: convert to normal platform driverHauke Mehrtens2-37/+80
Instead of hacking this into the plat_nand driver just make this a normal nand driver. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-07-11mtd: nand: xway: add some more documentationHauke Mehrtens1-6/+15
This adds some register documentation which should make it easier to understand how this controller works. In addition it makes now use of BIT() macro and adds some more defines. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-07-11mtd: nandbiterrs: Support for NAND biterrors test on platforms without raw writeIwo Mergler1-1/+1
Support for NAND biterrors test on platforms without raw write While the default test mode relies on raw write (mtd_write_oob) to introduce bit errors into a page, the rewrite test mode doesn't need it. Changed the overwrite test to use normal writes. The default test mode is unaffected and still requires raw write as before. Signed-off-by: Iwo Mergler <Iwo.Mergler@netcommwireless.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-07-11mtd: nand: sunxi: fix subpage writeBoris Brezillon1-1/+32
Implement ecc->write_subpage() to prevent core code from assigning this hook to nand_write_subpage_hwecc(). This default implementation tries to call ecc->hwctl() which in our case is NULL, thus leading to a NULL pointer dereference. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-07-11mtd: nand: sunxi: check ecc->size valuesBoris Brezillon1-0/+3
Verify that the ecc->size value is either 512 or 1024 bytes. This should always be the case if this field was assigned to the nand->ecc_step_size_ds value, but can be wrong when the user overloaded this value with the nand-ecc-step-size DT property. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-07-11mtd: nand: sunxi: prefer 1k ECC blocks when applicableBoris Brezillon1-0/+6
Switching to 1k ECC blocks when possible provides better resistance against concentrated bitflips. Say you have those two configurations: 1/ 16bits/512bytes 2/ 32bits/1024bytes Both of them require the same amount of ECC bytes (only true for this specific engine), but the second config allows you to correct the case where most of your bitflips are concentrated in a single 512bytes portion. This fact makes the 1k ECC block size more advantageous than the 512bytes one. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-07-11mtd: nand: sunxi: Fix OOB bytes retrieval in read_chunks_dma()Boris Brezillon1-2/+4
The column address passed to the RNDOUT operation was missing the page size offset. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Fixes: 614049a8d904 ("mtd: nand: sunxi: add support for DMA assisted operations")
2016-07-11mtd: mediatek: driver for MTK Smart DeviceJorge Ramirez-Ortiz5-0/+2114
Add support for mediatek's SDG1 NFC nand controller embedded in SoC 2701 Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Tested-by: Xiaolei Li <xiaolei.li@mediatek.com>
2016-07-11mtd: mediatek: device tree bindings for MTKJorge Ramirez-Ortiz1-0/+160
Documentation support for Smart Device Gen1 type of NAND controllers Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-07-11mtd: nand: sunxi: fix return value check in sunxi_nfc_dma_op_prepare()Wei Yongjun1-2/+2
In case of error, the function dmaengine_prep_slave_sg() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Fixes: 614049a8d904 ("mtd: nand: sunxi: add support for DMA assisted operations") Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-07-11mtd: brcmnand: Detect sticky ucorr ecc error on dma readsKamal Dasu1-0/+18
This change provides a fix for controller bug where nand controller could have a possible sticky error after a PIO followed by a DMA read. The fix retries a read if we see a uncorr_ecc after read to detect such sticky errors. The fix applies to only controller version 7.0 and 7.1. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-07-10mtd: spi-nor: fix wrong "fully unlocked" testBrian Norris1-1/+1
In stm_unlock(), the test to determine whether we've fully unlocked the flash checks for the lock length to be equal to the flash size. That is a typo/think-o -- the condition actually means the flash is completely *locked.* We should be using the inverse condition -- that the lock length is 0 (i.e., no protection). The result of this bug is that we never actually turn off the Status Register Write Disable bit, even if the flash is completely unlocked. Now we can. Fixes: 47b8edbf0d43 ("mtd: spi-nor: disallow further writes to SR if WP# is low") Reported-by: Giorgio <giorgio.nicole@arcor.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
2016-07-10mtd: cfi_cmdset_0020: Deinline do_write_buffer, save 5316 bytesDenys Vlasenko1-1/+1
This function compiles to 2554 bytes of machine code. In C, the function is almost 200 lines long. It has only one callsite, but forced inlining that much code makes gcc generate significantly worse code. Let gcc itself decide what to do. Signed-off-by: Denys Vlasenko <dvlasenk@redhat.com> CC: David Woodhouse <David.Woodhouse@intel.com> CC: Dan Carpenter <dan.carpenter@oracle.com> CC: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> CC: linux-mtd@lists.infradead.org CC: linux-kernel@vger.kernel.org Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-07-10mtd: Replace if and BUG with BUG_ONAmitoj Kaur Chawla1-2/+1
Replace if condition and BUG() with a BUG_ON having the conditional expression of the if statement as argument. The Coccinelle semantic patch used to make this change is as follows: @@ expression E,f; @@ ( if (<+... f(...) ...+>) { BUG(); } | - if (E) { BUG(); } + BUG_ON(E); ) Signed-off-by: Amitoj Kaur Chawla <amitoj1606@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-07-10mtd: physmap_of: fix set but unused warningBrian Norris1-1/+1
drivers/mtd/maps/physmap_of.c: In function ‘of_flash_probe’: drivers/mtd/maps/physmap_of.c:165:16: warning: variable ‘p’ set but not used [-Wunused-but-set-variable] This could be a problem if the 'reg' property is not set, since that means 'count' will be uninitialized. Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-07-10mtd: silence some uninitialized variable warningsDan Carpenter1-2/+2
The "tmp_retlen" variable can be uninitialized if action() fails. It's harmless except for the static checker warning. I have moved the error handling earlier to fix it. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-07-10mtd: Remove unused symbol CONFIG_MTDRAM_ABS_POSBen Hutchings3-14/+2
This has been unused, except as the condition for a fatal error, since commit c13cbf3b5086 ("[MTD] mtdram: Quick cleanup of the driver:") in 2.6.13 (!). Signed-off-by: Ben Hutchings <ben@decadent.org.uk> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-06-13mtd: brcmnand: Add check for erased page bitflipsKamal Dasu1-0/+62
Check for erased page bitflips in a page. And if well within threshold return data as all 0xff. Apply sw check for controller version < 7.2. Controller vesion >= 7.2 has hw support. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-06-09mtd: nand: add ESMT manufacturerRafał Miłecki2-0/+2
I got device with ESMT (Elite Semiconductor Memory Technology Inc) F59L1G81MA flash that was detected as: [ 0.852034] nand: device found, Manufacturer ID: 0xc8, Chip ID: 0xd1 [ 0.858402] nand: Unknown NAND 128MiB 3,3V 8-bit [ 0.863031] nand: 128MiB, SLC, page size: 2048, OOB size: 64 According to the F59L1G81MA datasheet (and Read Id documentation) C8h is a "Maker Code" which should mean ESMT. Add it to fix above "Unknown". Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-06-06mtd: nand: sunxi: update DT bindingsBoris Brezillon1-0/+4
Document dmas and dma-names properties. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-06-06mtd: nand: sunxi: add support for DMA assisted operationsBoris Brezillon1-7/+323
The sunxi NAND controller is able to pipeline ECC operations only when operated in DMA mode, which improves a lot NAND throughput while keeping CPU usage low. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-06-03mtd: brcmnand: Add v7.2 controller supportFlorian Fainelli2-14/+78
The 7.2 controller differs in a few area compared to its predecssor (7.1): - NAND scrambler, which we are not using just yet - higher ECC levels (up to 120 bits) per 1KB data blocks, also not supported yet - up to 128B OOB This patch adds the necessary code to support such a controller generation and updates the Device Tree binding. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Kamal Dasu <kdasu.kdev@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-06-02mtd: m25p80: read in spi_max_transfer_size chunksMichal Suchanek1-1/+1
Take into account transfer size limitation of SPI master. Signed-off-by: Michal Suchanek <hramrach@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Michal Suchanek <hramrach@gmail.com> Tested-by: Michal Suchanek <hramrach@gmail.com>
2016-06-02mtd: spi-nor: add read loopMichal Suchanek1-6/+19
mtdblock and ubi do not handle the situation when read returns less data than requested. Loop in spi-nor until buffer is filled or an error is returned. Signed-off-by: Michal Suchanek <hramrach@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Tested-by Cyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by: Michal Suchanek <hramrach@gmail.com> Tested-by: Michal Suchanek <hramrach@gmail.com>
2016-06-02mtd: spi-nor: simplify write loopMichal Suchanek1-33/+25
The spi-nor write loop assumes that what is passed to the hardware driver write() is what gets written. When write() writes less than page size at once data is dropped on the floor. Check the amount of data writen and exit if it does not match requested amount. Signed-off-by: Michal Suchanek <hramrach@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Tested-by Cyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by: Michal Suchanek <hramrach@gmail.com> Tested-by: Michal Suchanek <hramrach@gmail.com>
2016-06-02mtd: spi-nor: stop passing around retlenMichal Suchanek6-35/+28
Do not pass retlen to hardware driver read/write functions. Update it in spi-nor generic driver instead. Signed-off-by: Michal Suchanek <hramrach@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Tested-by Cyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by: Michal Suchanek <hramrach@gmail.com> Tested-by: Michal Suchanek <hramrach@gmail.com>
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