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2016-01-20Merge branch 'pci/trivial' into nextBjorn Helgaas42-1431/+1421
* pci/trivial: PCI: shpchp: Constify hpc_ops structure PCI: Use kobj_to_dev() instead of open-coding it PCI: Use to_pci_dev() instead of open-coding it PCI: Fix all whitespace issues PCI/MSI: Fix typos in <linux/msi.h>
2016-01-20Merge branches 'pci/iommu' and 'pci/misc' into nextBjorn Helgaas2-0/+6
* pci/iommu: PCI: Add function 1 DMA alias quirk for Lite-On/Plextor M6e/Marvell 88SS9183 * pci/misc: PCI: Limit config space size for Netronome NFP4000 PCI: Add Netronome NFP4000 PF device ID
2016-01-20PCI: Add function 1 DMA alias quirk for Lite-On/Plextor M6e/Marvell 88SS9183Tim Sander1-0/+4
Add function 1 DMA alias quirk for Lite-On/Plextor M6e/Marvell 88SS9183. Signed-off-by: Tim Sander <tim@krieglstein.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Alex Williamson <alex.williamson@redhat.com>
2016-01-16PCI: Limit config space size for Netronome NFP4000Simon Horman1-0/+1
Like the NFP6000, the NFP4000 as an erratum where reading/writing to PCI config space addresses above 0x600 can cause the NFP to generate PCIe completion timeouts. Limit the NFP4000's PF's config space size to 0x600 bytes as is already done for the NFP6000. The NFP4000's VF is 0x6004 (PCI_DEVICE_ID_NETRONOME_NFP6000_VF), the same device ID as the NFP6000's VF. Thus, its config space is already limited by the existing use of quirk_nfp6000(). Signed-off-by: Simon Horman <simon.horman@netronome.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-01-16PCI: Add Netronome NFP4000 PF device IDSimon Horman1-0/+1
Add the device ID for the PF of the NFP4000. The device ID for the VF, 0x6003, is already present as PCI_DEVICE_ID_NETRONOME_NFP6000_VF. Signed-off-by: Simon Horman <simon.horman@netronome.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-01-16Merge branch 'pci/host-vmd' into nextBjorn Helgaas10-11/+811
* pci/host-vmd: x86/PCI: Add driver for Intel Volume Management Device (VMD) PCI/AER: Use 32 bit PCI domain numbers x86/PCI: Allow DMA ops specific to a PCI domain irqdomain: Export irq_domain_set_info() for module use genirq/MSI: Relax msi_domain_alloc() to support parentless MSI irqdomains
2016-01-15x86/PCI: Add driver for Intel Volume Management Device (VMD)Keith Busch5-0/+749
The Intel Volume Management Device (VMD) is a Root Complex Integrated Endpoint that acts as a host bridge to a secondary PCIe domain. BIOS can reassign one or more Root Ports to appear within a VMD domain instead of the primary domain. The immediate benefit is that additional PCIe domains allow more than 256 buses in a system by letting bus numbers be reused across different domains. VMD domains do not define ACPI _SEG, so to avoid domain clashing with host bridges defining this segment, VMD domains start at 0x10000, which is greater than the highest possible 16-bit ACPI defined _SEG. This driver enumerates and enables the domain using the root bus configuration interface provided by the PCI subsystem. The driver provides configuration space accessor functions (pci_ops), bus and memory resources, an MSI IRQ domain with irq_chip implementation, and DMA operations necessary to use devices through the VMD endpoint's interface. VMD routes I/O as follows: 1) Configuration Space: BAR 0 ("CFGBAR") of VMD provides the base address and size for configuration space register access to VMD-owned root ports. It works similarly to MMCONFIG for extended configuration space. Bus numbering is independent and does not conflict with the primary domain. 2) MMIO Space: BARs 2 and 4 ("MEMBAR1" and "MEMBAR2") of VMD provide the base address, size, and type for MMIO register access. These addresses are not translated by VMD hardware; they are simply reservations to be distributed to root ports' memory base/limit registers and subdivided among devices downstream. 3) DMA: To interact appropriately with an IOMMU, the source ID DMA read and write requests are translated to the bus-device-function of the VMD endpoint. Otherwise, DMA operates normally without VMD-specific address translation. 4) Interrupts: Part of VMD's BAR 4 is reserved for VMD's MSI-X Table and PBA. MSIs from VMD domain devices and ports are remapped to appear as if they were issued using one of VMD's MSI-X table entries. Each MSI and MSI-X address of VMD-owned devices and ports has a special format where the address refers to specific entries in the VMD's MSI-X table. As with DMA, the interrupt source ID is translated to VMD's bus-device-function. The driver provides its own MSI and MSI-X configuration functions specific to how MSI messages are used within the VMD domain, and provides an irq_chip for independent IRQ allocation to relay interrupts from VMD's interrupt handler to the appropriate device driver's handler. 5) Errors: PCIe error message are intercepted by the root ports normally (e.g., AER), except with VMD, system errors (i.e., firmware first) are disabled by default. AER and hotplug interrupts are translated in the same way as endpoint interrupts. 6) VMD does not support INTx interrupts or IO ports. Devices or drivers requiring these features should either not be placed below VMD-owned root ports, or VMD should be disabled by BIOS for such endpoints. [bhelgaas: add VMD BAR #defines, factor out vmd_cfg_addr(), rework VMD resource setup, whitespace, changelog] Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> (IRQ-related parts)
2016-01-15PCI/AER: Use 32 bit PCI domain numbersKeith Busch1-8/+8
The Intel Volume Management Device (VMD) supports 32-bit domain numbers. To accommodate this, use u32 instead of u16 to store domain numbers. [bhelgaas: changelog] Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-01-15x86/PCI: Allow DMA ops specific to a PCI domainKeith Busch2-0/+48
The Intel Volume Management Device (VMD) is a PCIe endpoint that acts as a host bridge to another PCI domain. When devices below the VMD perform DMA, the VMD replaces their DMA source IDs with its own source ID. Therefore, those devices require special DMA ops. Add interfaces to allow the VMD driver to set up dma_ops for the devices below it. [bhelgaas: remove "extern", add "static", changelog] Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-01-15irqdomain: Export irq_domain_set_info() for module useKeith Busch1-0/+1
Export irq_domain_set_info() for module use. It will be used by the Volume Management Device driver. [bhelgaas: changelog] Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Thomas Gleixner <tglx@linutronix.de>
2016-01-15Merge branches 'pci/hotplug' and 'pci/resource' into nextBjorn Helgaas13-96/+67
* pci/hotplug: PCI: ibmphp: Remove unneeded NULL test PCI: hotplug: Use list_for_each_entry() to simplify code PCI: acpiphp_ibm: Fix null dereferences on null ibm_slot * pci/resource: PCI: Avoid iterating through memory outside the resource window PCI: Fix minimum allocation address overwrite
2016-01-15Merge branches 'pci/host', 'pci/host-designware', 'pci/host-hisi', ↵Bjorn Helgaas18-85/+1110
'pci/host-qcom' and 'pci/host-rcar' into next * pci/host: PCI: host: Add of_pci_get_host_bridge_resources() stub PCI: host: Mark PCIe/PCI (MSI) IRQ cascade handlers as IRQF_NO_THREAD * pci/host-designware: PCI: designware: Make config accessor override checking symmetric PCI: designware: Simplify control flow * pci/host-hisi: PCI: hisi: Add support for HiSilicon Hip06 PCIe host controllers * pci/host-qcom: ARM: dts: ifc6410: enable PCIe DT node for this board ARM: dts: apq8064: add PCIe devicetree node PCI: qcom: Add Qualcomm PCIe controller driver PCI: qcom: Document PCIe devicetree bindings PCI: designware: Ensure ATU is enabled before IO/conf space accesses * pci/host-rcar: PCI: rcar: Add Gen2 PHY setup to pcie-rcar PCI: rcar: Add runtime PM support to pcie-rcar PCI: rcar: Remove unused pci_sys_data struct from pcie-rcar
2016-01-15PCI: host: Add of_pci_get_host_bridge_resources() stubArnd Bergmann1-0/+7
The pcie-rcar driver can be built for any ARM platform (for COMPILE_TEST) including those without CONFIG_OF enabled, and that results in a compile-time error: drivers/pci/host/pcie-rcar.c: In function 'rcar_pcie_parse_request_of_pci_ranges': drivers/pci/host/pcie-rcar.c:939:8: error: implicit declaration of function 'of_pci_get_host_bridge_resources' [-Werror=implicit-function-declaration] err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pci->resources, &iobase); Add a of_pci_get_host_bridge_resources() stub function defined when CONFIG_OF_ADDRESS is disabled to allow compile-testing on all platforms. This mirrors what we do for other OF-specific functions. Fixes: 5d2917d469fa ("PCI: rcar: Convert to DT resource parsing API") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Simon Horman <horms+renesas@verge.net.au>
2016-01-14genirq/MSI: Relax msi_domain_alloc() to support parentless MSI irqdomainsLiu Jiang1-3/+5
Previously msi_domain_alloc() assumed MSI irqdomains always had parent irqdomains, but that's not true for the new Intel VMD devices. Relax msi_domain_alloc() to support parentless MSI irqdomains. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Thomas Gleixner <tglx@linutronix.de>
2016-01-11PCI: rcar: Add Gen2 PHY setup to pcie-rcarPhil Edworthy1-3/+28
For PCIe compliance, the PHY registers need setting as per the manual. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
2016-01-11PCI: rcar: Add runtime PM support to pcie-rcarPhil Edworthy1-12/+32
If runtime PM is enabled in the kernel config, simply enable the clocks once during probe. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
2016-01-11PCI: designware: Make config accessor override checking symmetricBjorn Helgaas1-6/+6
Drivers based on the DesignWare core can override the config read accessors by supplying rd_own_conf() and rd_other_conf() function pointers. dw_pcie_rd_conf() calls dw_pcie_rd_own_conf() (for accesses to the root bus) or dw_pcie_rd_other_conf(): dw_pcie_rd_conf dw_pcie_rd_own_conf # if on root bus dw_pcie_rd_other_conf # if not on root bus Previously we checked for rd_other_conf() directly in dw_pcie_rd_conf(), but we checked for rd_own_conf() in dw_pcie_rd_own_conf(). Check for rd_other_conf() in dw_pcie_rd_other_conf() to make this symmetric with the rd_own_conf() checking, and similarly for the write path. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
2016-01-11PCI: ibmphp: Remove unneeded NULL testJulia Lawall1-3/+0
Remove unneeded NULL test. The index variable of list_for_each_entry is never NULL, as it is the structure that contains the list pointer. Generated by: scripts/coccinelle/iterators/itnull.cocci Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Julia Lawall <julia.lawall@lip6.fr> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Geliang Tang <geliangtang@163.com>
2016-01-11ARM: dts: ifc6410: enable PCIe DT node for this boardStanimir Varbanov1-0/+26
Enable PCIe DT node and fill PCIe DT node with regulator, pinctrl and reset GPIO, to use the PCIe on the ifc6410 board. Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-01-11ARM: dts: apq8064: add PCIe devicetree nodeStanimir Varbanov1-0/+36
Add the PCIe DT node so that it can probe and be used. Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-01-11PCI: hotplug: Use list_for_each_entry() to simplify codeGeliang Tang10-88/+46
Use list_for_each_entry() instead of list_for_each() to simplify the code. Signed-off-by: Geliang Tang <geliangtang@163.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-01-08PCI: rcar: Remove unused pci_sys_data struct from pcie-rcarPhil Edworthy1-9/+0
The pci_sys_data struct was previously used by pci_common_init_dev() and by the ARM pcibios_align_resource(), but recent commits removed those uses: cbce7900598c ("PCI: designware: Make driver arch-agnostic") b3a72384fe29 ("ARM/PCI: Replace pci_sys_data->align_resource with global function pointer") cbce7900598c removed the use of pci_common_init_dev() by DesignWare drivers, including pcie-rcar.c, and b3a72384fe29 removed the use of struct pci_sys_data by the ARM pcibios_align_resource(). Remove struct pci_sys_data from pcie-rcar.c. [bhelgaas: changelog] Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-01-08PCI: hisi: Add support for HiSilicon Hip06 PCIe host controllersGabriele Paoloni4-17/+73
Add support for the HiSilicon Hip06 SoC. Documentation has been updated to include Hip06. Add Gabriele Paoloni as maintainer of the driver. Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com>
2016-01-08PCI: Avoid iterating through memory outside the resource windowEdward O'Callaghan1-0/+3
If the 'image' pointer has been advanced more than 'size', we've already iterated through memory outside the resource window. We have zero control over whatever we find in the option ROM, if it's even an option ROM and not just an accident of random data just happening to look like an option ROM. Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-01-08PCI: acpiphp_ibm: Fix null dereferences on null ibm_slotColin Ian King1-3/+14
ibm_slot_from_id() can return null if the des header signature is not "aPCI" or if the kmalloc() for the return ACPI descriptor fails, causing potential null pointer dereferences on the return null descriptor. Handle the null case with appropriate check and error return. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-01-08PCI: shpchp: Constify hpc_ops structureJulia Lawall2-3/+3
The hpc_ops structure is never modified, so declare it as const. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-01-08PCI: Use kobj_to_dev() instead of open-coding itGeliang Tang2-27/+17
Use kobj_to_dev() instead of open-coding it. Signed-off-by: Geliang Tang <geliangtang@163.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-01-08PCI: Use to_pci_dev() instead of open-coding itGeliang Tang2-2/+2
Use to_pci_dev() instead of open-coding it. Signed-off-by: Geliang Tang <geliangtang@163.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-01-08PCI: Fix all whitespace issuesBogicevic Sasa39-1432/+1432
Fix all whitespace issues (missing or needed whitespace) in all files in drivers/pci. Code is compiled with allyesconfig before and after code changes and objects are recorded and checked with objdiff and they are not changed after this commit. Signed-off-by: Bogicevic Sasa <brutallesale@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-01-07PCI/MSI: Fix typos in <linux/msi.h>Thomas Petazzoni1-2/+2
Fix two comment typos in the <linux/msi.h> header. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-01-07Merge branches 'pci/host-generic', 'pci/host-imx6', 'pci/host-iproc' and ↵Bjorn Helgaas15-129/+1166
'pci/host-rcar' into next * pci/host-generic: PCI: generic,versatile: Remove unused pci_sys_data structures * pci/host-imx6: PCI: imx6: Add support for active-low reset GPIO PCI: imx6: Use gpio_set_value_cansleep() * pci/host-iproc: PCI: iproc: Add iProc PCIe MSI support PCI: iproc: Add iProc PCIe MSI device tree binding PCI: iproc: Add PAXC interface support PCI: iproc: Update iProc PCIe device tree binding PCI: iproc: Do not use 0x in front of %pap PCI: iproc: Hide CONFIG_PCIE_IPROC * pci/host-rcar: PCI: rcar: Add gen2 fallback compatibility string for pcie-rcar PCI: rcar: Add gen2 fallback compatibility string for pci-rcar-gen2 PCI: rcar: Add support for R-Car H3 to pcie-rcar Revert "PCI: rcar: Build pcie-rcar.c only on ARM" PCI: rcar: Convert to DT resource parsing API PCI: rcar: Allow DT to override default window settings
2016-01-07PCI: iproc: Add iProc PCIe MSI supportRay Jui7-2/+735
Add PCIe MSI support for both PAXB and PAXC interfaces on all iProc-based platforms. The iProc PCIe MSI support deploys an event queue-based implementation. Each event queue is serviced by a GIC interrupt and can support up to 64 MSI vectors. Host memory is allocated for the event queues, and each event queue consists of 64 word-sized entries. MSI data is written to the lower 16-bit of each entry, whereas the upper 16-bit of the entry is reserved for the controller for internal processing. Each event queue is tracked by a head pointer and tail pointer. Head pointer indicates the next entry in the event queue to be processed by the driver and is updated by the driver after processing is done. The controller uses the tail pointer as the next MSI data insertion point. The controller ensures MSI data is flushed to host memory before updating the tail pointer and then triggering the interrupt. MSI IRQ affinity is supported by evenly distributing the interrupts to each CPU core. MSI vector is moved from one GIC interrupt to another in order to steer to the target CPU. Therefore, the actual number of supported MSI vectors is: M * 64 / N where M denotes the number of GIC interrupts (event queues), and N denotes the number of CPU cores. This iProc event queue-based MSI support should not be used with newer platforms with integrated MSI support in the GIC (e.g., giv2m or gicv3-its). [bhelgaas: fold in Kconfig fixes from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Vikram Prakash <vikramp@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
2016-01-07PCI: host: Mark PCIe/PCI (MSI) IRQ cascade handlers as IRQF_NO_THREADGrygorii Strashko7-8/+15
On -RT and if kernel is booting with "threadirqs" cmd line parameter, PCIe/PCI (MSI) IRQ cascade handlers (like dra7xx_pcie_msi_irq_handler()) will be forced threaded and, as result, will generate warnings like this: WARNING: CPU: 1 PID: 82 at kernel/irq/handle.c:150 handle_irq_event_percpu+0x14c/0x174() irq 460 handler irq_default_primary_handler+0x0/0x14 enabled interrupts Backtrace: (warn_slowpath_common) from (warn_slowpath_fmt+0x38/0x40) (warn_slowpath_fmt) from (handle_irq_event_percpu+0x14c/0x174) (handle_irq_event_percpu) from (handle_irq_event+0x84/0xb8) (handle_irq_event) from (handle_simple_irq+0x90/0x118) (handle_simple_irq) from (generic_handle_irq+0x30/0x44) (generic_handle_irq) from (dra7xx_pcie_msi_irq_handler+0x7c/0x8c) (dra7xx_pcie_msi_irq_handler) from (irq_forced_thread_fn+0x28/0x5c) (irq_forced_thread_fn) from (irq_thread+0x128/0x204) This happens because all of them invoke generic_handle_irq() from the requested handler. generic_handle_irq() grabs raw_locks and thus needs to run in raw-IRQ context. This issue was originally reproduced on TI dra7-evem, but, as was identified during discussion [1], other hosts can also suffer from this issue. Fix all them at once by marking PCIe/PCI (MSI) IRQ cascade handlers IRQF_NO_THREAD explicitly. [1] http://lkml.kernel.org/r/1448027966-21610-1-git-send-email-grygorii.strashko@ti.com [bhelgaas: add stable tag, fix typos] Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Lucas Stach <l.stach@pengutronix.de> (for imx6) CC: stable@vger.kernel.org CC: Kishon Vijay Abraham I <kishon@ti.com> CC: Jingoo Han <jingoohan1@gmail.com> CC: Kukjin Kim <kgene@kernel.org> CC: Krzysztof Kozlowski <k.kozlowski@samsung.com> CC: Richard Zhu <Richard.Zhu@freescale.com> CC: Thierry Reding <thierry.reding@gmail.com> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Alexandre Courbot <gnurou@gmail.com> CC: Simon Horman <horms@verge.net.au> CC: Pratyush Anand <pratyush.anand@gmail.com> CC: Michal Simek <michal.simek@xilinx.com> CC: "Sören Brinkmann" <soren.brinkmann@xilinx.com> CC: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
2016-01-07PCI: Fix minimum allocation address overwriteChristoph Biedl1-2/+4
Commit 36e097a8a297 ("PCI: Split out bridge window override of minimum allocation address") claimed to do no functional changes but unfortunately did: The "min" variable is altered. At least the AVM A1 PCMCIA adapter was no longer detected, breaking ISDN operation. Use a local copy of "min" to restore the previous behaviour. [bhelgaas: avoid gcc "?:" extension for portability and readability] Fixes: 36e097a8a297 ("PCI: Split out bridge window override of minimum allocation address") Signed-off-by: Christoph Biedl <linux-kernel.bfrz@manchmal.in-ulm.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v3.14+
2016-01-06PCI: designware: Simplify control flowBjorn Helgaas1-36/+18
Return values immediately when possible to simplify the control flow. No functional change intended. Folded in unused variable removal as pointed out by Fabio Estevam <fabio.estevam@nxp.com>, Arnd Bergmann <arnd@arndb.de>, and Thierry Reding <thierry.reding@gmail.com>. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
2016-01-06PCI: qcom: Add Qualcomm PCIe controller driverStanimir Varbanov4-0/+634
The PCIe driver reuses the Designware common code for host and MSI initialization, and also programs the Qualcomm application specific registers. [bhelgaas: remove COMPILE_TEST Kconfig dependency] Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com> Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-01-06PCI: qcom: Document PCIe devicetree bindingsStanimir Varbanov1-0/+233
Document Qualcomm PCIe driver devicetree bindings. Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com> Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org>
2016-01-05PCI: designware: Ensure ATU is enabled before IO/conf space accessesStanimir Varbanov1-0/+8
Read back the ATU CR2 register to ensure ATU programming is effective before any subsequent I/O or config space accesses. Without this, PCI device enumeration is unreliable. [bhelgaas: changelog, comment] Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
2015-12-11Merge branches 'pci/aspm', 'pci/hotplug', 'pci/misc' and 'pci/msi' into nextBjorn Helgaas16-145/+104
* pci/aspm: PCI/ASPM: Make sysfs link_state_store() consistent with link_state_show() * pci/hotplug: PCI: pciehp: Always protect pciehp_disable_slot() with hotplug mutex * pci/misc: x86/PCI: Simplify pci_bios_{read,write} PCI: Simplify config space size computation PCI: Limit config space size for Netronome NFP6000 family PCI: Add Netronome vendor and device IDs PCI: Support PCIe devices with short cfg_size x86/PCI: Clarify AMD Fam10h config access restrictions comment PCI: Print warnings for all invalid expansion ROM headers PCI: Check for PCI_HEADER_TYPE_BRIDGE equality, not bitmask * pci/msi: PCI/MSI: Remove empty pci_msi_init_pci_dev() PCI/MSI: Initialize MSI capability for all architectures
2015-12-11x86/PCI: Simplify pci_bios_{read,write}Geliang Tang1-70/+38
There is some repetitive code in the switch/case statements in pci_bios_read() and pci_bios_write(). Factor out the BIOS function IDs and the result widths to simplify the code. Signed-off-by: Geliang Tang <geliangtang@163.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
2015-12-11PCI: Simplify config space size computationBjorn Helgaas1-15/+10
Restructure the logic so we return the config space size as soon as we know it. This reduces indentation, removes negations, and removes gotos. No functional change. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2015-12-11PCI: Limit config space size for Netronome NFP6000 familyJason S. McMullan1-0/+11
The NFP6000 has an erratum where reading/writing to PCI config space addresses above 0x600 can cause the NFP to generate PCIe completion timeouts. Limit the NFP6000's config space size to 0x600 bytes. Signed-off-by: Jason S. McMullan <jason.mcmullan@netronome.com> [simon: edited changelog] Signed-off-by: Simon Horman <simon.horman@netronome.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2015-12-11PCI: Add Netronome vendor and device IDsJason S. McMullan1-0/+6
Device IDs for the Netronome NFP3200, NFP3240, NFP6000, and NFP6000 SR-IOV devices. Signed-off-by: Jason S. McMullan <jason.mcmullan@netronome.com> [simon: edited changelog] Signed-off-by: Simon Horman <simon.horman@netronome.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2015-12-11PCI: Support PCIe devices with short cfg_sizeJason S. McMullan1-9/+9
If a device quirk modifies the pci_dev->cfg_size to be less than PCI_CFG_SPACE_EXP_SIZE (4096), but greater than PCI_CFG_SPACE_SIZE (256), the PCI sysfs interface truncates the readable size to PCI_CFG_SPACE_SIZE. Allow sysfs access to config space up to cfg_size, even if the device doesn't support the entire 4096-byte PCIe config space. Note that pci_read_config() and pci_write_config() limit access to dev->cfg_size even though pcie_config_attr contains 4096 (the maximum size). Signed-off-by: Jason S. McMullan <jason.mcmullan@netronome.com> [simon: edited changelog] Signed-off-by: Simon Horman <simon.horman@netronome.com> [bhelgaas: more changelog edits] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2015-12-11x86/PCI: Clarify AMD Fam10h config access restrictions commentTomasz Nowicki1-5/+5
Clarify the comment about AMD Fam10h config access restrictions, fix typos, and add a reference to the specification. [bhelgaas: streamline] Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
2015-12-11PCI: Print warnings for all invalid expansion ROM headersVladis Dronov1-12/+8
We've always validated that both bytes of the Expansion ROM signature and all four bytes of the PCI Data Structure signature (see PCI Firmware spec r3.0, sec 5.1.1), but we only printed a warning if the first byte of the ROM signature was invalid. Print warnings if *any* of those bytes are invalid. Note that we only look at these headers if we map or read the ROM. [bhelgaas: changelog, tweak printk format] Signed-off-by: Vladis Dronov <vdronov@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2015-12-11PCI: Check for PCI_HEADER_TYPE_BRIDGE equality, not bitmaskBjorn Helgaas3-7/+7
Bit 7 of the "Header Type" register indicates a multi-function device when set. Bits 0-6 contain encoded values, where 0x1 indicates a PCI-PCI bridge. It is incorrect to test this as though it were a mask. For example, while the PCI 3.0 spec only defines values 0x0, 0x1, and 0x2, it's conceivable that a future spec could define 0x3 to mean something else; then tests for "(hdr_type & 0x7f) & PCI_HEADER_TYPE_BRIDGE" would incorrectly succeed for this new 0x3 header type. Test bits 0-6 of the Header Type for equality with PCI_HEADER_TYPE_BRIDGE. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2015-12-09PCI: rcar: Add gen2 fallback compatibility string for pcie-rcarSimon Horman2-4/+12
Add fallback compatibility string for R-Car Gen 2 family. This is in keeping with the fallback scheme being adopted wherever appropriate for drivers for Renesas SoCs. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2015-12-09PCI: rcar: Add gen2 fallback compatibility string for pci-rcar-gen2Simon Horman2-2/+10
Add fallback compatibility string for R-Car Gen 2 family. This is in keeping with the fallback scheme being adopted wherever appropriate for drivers for Renesas SoCs. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org>
2015-12-09PCI: rcar: Add support for R-Car H3 to pcie-rcarHarunobu Kurokawa2-1/+3
Add the "renesas,pcie-r8a7795" property for the R-Car H3 device to the pcie-rcar driver. Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-01-03 18:58:09 +0300