| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2017-07-05 | MIPS: MIPS16e2: Subdecode extended LWSP/SWSP instructions | Maciej W. Rozycki | 1 | -2/+37 |
| 2017-07-05 | MIPS: MIPS16e2: Identify ASE presence | Maciej W. Rozycki | 4 | -0/+7 |
| 2017-06-29 | MIPS: VDSO: Fix a mismatch between comment and preprocessor constant | Aleksandar Markovic | 1 | -1/+1 |
| 2017-06-29 | MIPS: VDSO: Add implementation of gettimeofday() fallback | Goran Ferenc | 1 | -1/+23 |
| 2017-06-29 | MIPS: VDSO: Add implementation of clock_gettime() fallback | Goran Ferenc | 1 | -3/+22 |
| 2017-06-29 | MIPS: VDSO: Fix conversions in do_monotonic()/do_monotonic_coarse() | Goran Ferenc | 2 | -6/+6 |
| 2017-06-29 | MIPS: Use current_cpu_type() in m4kc_tlbp_war() | Paul Burton | 1 | -2/+1 |
| 2017-06-29 | MIPS: Allow storing pgd in C0_CONTEXT for MIPSr6 | Paul Burton | 1 | -1/+1 |
| 2017-06-29 | MIPS: Handle tlbex-tlbp race condition | Paul Burton | 1 | -1/+37 |
| 2017-06-29 | MIPS: Add CPU shared FTLB feature detection | Paul Burton | 3 | -0/+56 |
| 2017-06-29 | MIPS: CPS: Handle spurious VP starts more gracefully | Paul Burton | 1 | -1/+6 |
| 2017-06-29 | MIPS: CPS: Handle cores not powering down more gracefully | Paul Burton | 1 | -3/+24 |
| 2017-06-29 | MIPS: CPS: Prevent multi-core with dcache aliasing | Paul Burton | 1 | -3/+5 |
| 2017-06-29 | MIPS: CPS: Select CONFIG_SYS_SUPPORTS_SCHED_SMT for MIPSr6 | Paul Burton | 1 | -0/+1 |
| 2017-06-29 | MIPS: CM: WARN on attempt to lock invalid VP, not BUG | Paul Burton | 1 | -1/+1 |
| 2017-06-29 | MIPS: CM: Avoid per-core locking with CM3 & higher | Paul Burton | 1 | -6/+32 |
| 2017-06-29 | MIPS: Skip IPI setup if we only have 1 CPU | Paul Burton | 1 | -0/+3 |
| 2017-06-29 | MIPS: Use `pr_debug' for messages from `__compute_return_epc_for_insn' | Maciej W. Rozycki | 1 | -6/+6 |
| 2017-06-29 | MIPS: math-emu: For MFHC1/MTHC1 also return SIGILL right away | Maciej W. Rozycki | 1 | -3/+2 |
| 2017-06-29 | MIPS: Fix a typo: s/preset/present/ in r2-to-r6 emulation error message | Maciej W. Rozycki | 1 | -1/+1 |
| 2017-06-29 | MIPS: Send SIGILL for R6 branches in `__compute_return_epc_for_insn' | Maciej W. Rozycki | 1 | -20/+15 |
| 2017-06-29 | MIPS: Send SIGILL for linked branches in `__compute_return_epc_for_insn' | Maciej W. Rozycki | 1 | -8/+4 |
| 2017-06-29 | MIPS: Rename `sigill_r6' to `sigill_r2r6' in `__compute_return_epc_for_insn' | Maciej W. Rozycki | 1 | -8/+8 |
| 2017-06-29 | MIPS: Send SIGILL for BPOSGE32 in `__compute_return_epc_for_insn' | Maciej W. Rozycki | 1 | -3/+4 |
| 2017-06-29 | MIPS: Fix unaligned PC interpretation in `compute_return_epc' | Maciej W. Rozycki | 1 | -4/+1 |
| 2017-06-29 | MIPS: Actually decode JALX in `__compute_return_epc_for_insn' | Maciej W. Rozycki | 1 | -0/+1 |
| 2017-06-29 | MIPS: math-emu: Prevent wrong ISA mode instruction emulation | Maciej W. Rozycki | 1 | -0/+38 |
| 2017-06-29 | MIPS: Use queued spinlocks (qspinlock) | Paul Burton | 4 | -232/+4 |
| 2017-06-29 | MIPS: Use queued read/write locks (qrwlock) | Paul Burton | 4 | -224/+4 |
| 2017-06-29 | MIPS: cmpxchg: Rearrange __xchg() arguments to match xchg() | Paul Burton | 1 | -2/+3 |
| 2017-06-29 | MIPS: cmpxchg: Implement 1 byte & 2 byte cmpxchg() | Paul Burton | 2 | -0/+64 |
| 2017-06-29 | MIPS: cmpxchg: Implement 1 byte & 2 byte xchg() | Paul Burton | 3 | -3/+60 |
| 2017-06-29 | MIPS: cmpxchg: Implement __cmpxchg() as a function | Paul Burton | 1 | -27/+32 |
| 2017-06-29 | MIPS: cmpxchg: Drop __xchg_u{32,64} functions | Paul Burton | 1 | -31/+17 |
| 2017-06-29 | MIPS: cmpxchg: Error out on unsupported xchg() calls | Paul Burton | 1 | -15/+17 |
| 2017-06-29 | MIPS: cmpxchg: Use __compiletime_error() for bad cmpxchg() pointers | Paul Burton | 1 | -3/+10 |
| 2017-06-29 | MIPS: cmpxchg: Pull xchg() asm into a macro | Paul Burton | 1 | -48/+33 |
| 2017-06-29 | MIPS: cmpxchg: Unify R10000_LLSC_WAR & non-R10000_LLSC_WAR cases | Paul Burton | 1 | -58/+22 |
| 2017-06-29 | MIPS: unaligned: Add DSP lwx & lhx missaligned access support | Miodrag Dinic | 2 | -74/+111 |
| 2017-06-29 | MIPS: R6: Fix PREF instruction usage by memcpy for MIPS R6 | Leonid Yegoshin | 1 | -0/+3 |
| 2017-06-29 | MIPS: build: Fix "-modd-spreg" switch usage when compiling for mips32r6 | Miodrag Dinic | 1 | -1/+1 |
| 2017-06-29 | MIPS: cmdline: Add support for 'memmap' parameter | Miodrag Dinic | 1 | -0/+40 |
| 2017-06-29 | MIPS: Loogson: Make enum loongson_cpu_type more clear | Huacai Chen | 2 | -9/+24 |
| 2017-06-29 | MIPS: Loongson-3: support irq_set_affinity() in i8259 chip | Huacai Chen | 1 | -13/+54 |
| 2017-06-29 | MIPS: Loongson-3: IRQ balancing for PCI devices | Huacai Chen | 2 | -3/+34 |
| 2017-06-29 | MIPS: Loongson-3: Support 4 packages in CPU Hwmon driver | Huacai Chen | 1 | -61/+58 |
| 2017-06-29 | MIPS: Loongson: Add NMI handler support | Huacai Chen | 1 | -0/+13 |
| 2017-06-28 | MIPS: Loongson: Add Loongson-3A R3 basic support | Huacai Chen | 5 | -6/+24 |
| 2017-06-28 | MIPS: SEAD-3: Fix GIC interrupt specifiers | Paul Burton | 1 | -4/+4 |
| 2017-06-28 | MIPS: SEAD-3: Set interrupt-parent per-device, not at root node | Paul Burton | 2 | -7/+24 |
