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2014-03-25clk: s2mps11: Use of_get_child_by_nameKrzysztof Kozlowski1-1/+1
of_find_node_by_name() walks over all nodes and can thus walk outside of the parent node. Use of_get_child_by_name() instead. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-25clk: s2mps11: Fix possible NULL pointer dereferenceKrzysztof Kozlowski1-1/+1
If parent device does not have of_node set the s2mps11_clk_parse_dt() returned NULL. This NULL was later passed to of_clk_add_provider() which dereferenced it in pr_debug() call. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: <stable@vger.kernel.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-21clk: hisilicon: fix warning from smatchZhangfei Gao1-8/+7
drivers/clk/hisilicon/clk-hi3620.c:338 mmc_clk_delay() warn: always true condition '(para >= 0) => (0-u32max >= 0)' Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-21clk: shmobile: add CPG driver for rz-platformsWolfram Sang3-0/+133
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-21clk: turn rate change failed warning into pr_debugSascha Hauer1-1/+1
If a rate change failed it's the opportunity of the caller to handle this. Do not spam the log with a message. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-20MAINTAINERS: use LKML for common clk frameworkMike Turquette1-1/+1
Framework is not ARM specific and used by many architectures. Change ML from LAKML to LKML. Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-20clk: respect the clock dependencies in of_clk_initGregory CLEMENT1-4/+79
Until now the clock providers were initialized in the order found in the device tree. This led to have the dependencies between the clocks not respected: children clocks could be initialized before their parent clocks. Instead of forcing each platform to manage its own initialization order, this patch adds this work inside the framework itself. Using the data of the device tree the of_clk_init function now delayed the initialization of a clock provider if its parent provider was not ready yet. The strict dependency check (all parents of a given clk must be initialized) was added by Boris BREZILLON Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-20clk: mpc85xx: Update the driver to align to new clock bindingsTang Yuantian1-22/+48
The clock bindings for Freescale CoreNet platform are updated. So, the driver needs to be updated accordingly. The main changes include: - Added a new node to present the input system clock - Changed PLL and MUX's compatible string Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-20clk: at91: optimization of the set_rate callbackJean-Jacques Hiblot1-30/+8
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-20clk: at91: fix programmable clk irq handlingJean-Jacques Hiblot2-93/+89
The PCKRDY bit is not set until the system clock is enabled. This patch moves the management of the ready status in the system clock driver. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-20clk: at91: propagate rate change on system clksBoris BREZILLON1-1/+1
System clks are just gates, and thus do not provide any rate operations. Authorize clk rate change to be propagated to system clk parents. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-20clk: at91: replace prog clk round_rate with determine_rateBoris BREZILLON1-28/+28
Implement the determine_rate callback to choose the best parent clk that fulfills the requested rate. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-20Documentation: clk: Add locking documentationLaurent Pinchart1-0/+34
Briefly document the common clock framework locking scheme from a clock driver point of view. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-19Merge tag 'clk-hisi' of ↵Mike Turquette7-39/+164
https://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux into clk-next-hisilcon updating clock drivers for Hisilicon
2014-03-19clk: sunxi: fix thinko in commentEmilio López1-1/+1
This should read MOD0 and not MMC; MMC is just one example of a MOD0 clock. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-19clk: sunxi: fix some calculationsEmilio López1-3/+3
Some divisor calculations were misrounded, causing higher than requested rates on some clocks. Fix them up using DIV_ROUND_UP, and replace one homebrew instance of it as well with the right macro. Reported-by: Boris BREZILLON <b.brezillon.dev@gmail.com> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-19clk: sunxi: fix A20 PLL4 calculationEmilio López1-0/+7
Allwinner actually reworked the PLL4 on A20; now it's compatible with the sun4i PLL5/6 design previous to any divisions, as well as to the new PLL8 in sun7i. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-19Merge tag 'sunxi-clk-for-3.15' of https://bitbucket.org/emiliolopez/linux ↵Mike Turquette2-48/+344
into clk-next-sunxi Allwinner sunXi SoCs clock changes This adds support for the new, more correct clock node naming and gets the A10 compatibles in line with the rest of the other SoCs. It also adds support for the USB, GMAC and A31's PLL6 clocks. Some of these changes also require DT modifications that will be merged via arm-soc.
2014-03-19clk: hisi: remove static variableHaojian Zhuang4-42/+72
Remove the static variable. So these common clock register helper could be used in more SoCs. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-03-19clk: hip04: add clock driverHaojian Zhuang4-1/+94
Now only fixed rate clocks are appended into the clock driver. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-03-19clk: hisi: assign missing clk to tableHaojian Zhuang1-0/+2
The fixed rate and fixed factor clock isn't registered to clk table. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-03-19clk: socfpga: Fix section mismatch warningDinh Nguyen1-1/+1
WARNING: drivers/clk/socfpga/built-in.o(.data+0xc0): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_pll_init() The variable socfpga_child_clocks references the function __init socfpga_pll_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console WARNING: drivers/clk/socfpga/built-in.o(.data+0x184): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_periph_init() The variable socfpga_child_clocks references the function __init socfpga_periph_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console WARNING: drivers/clk/socfpga/built-in.o(.data+0x248): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_gate_init() The variable socfpga_child_clocks references the function __init socfpga_gate_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console Reported-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-19Merge tag 'clk-mvebu-3xx-3.15-2' of git://git.infradead.org/linux-mvebu into ↵Mike Turquette2-2/+28
clk-next-mvebu clock: mvebu new SoC changes for v3.15 (incremental pull #2) - mvebu (Armada 375) - fix ratio register offest - mvebu (Armada 380) - expand core divider clock driver to support 380 SoC (enables nand support)
2014-03-19clk: clk-s2mps11: Add support for clocks in S5M8767 MFDTushar Behera2-2/+9
Since clock operation within S2MPS11 and S5M8767 are similar, we can support both the devices within a single driver. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-19clk: clk-s2mps11: Refactor for including support for other MFD clocksTushar Behera1-4/+16
The clocks in S2MPS11 and S5M8767 are managed in the same way, baring a difference in the register offset. It would be better to update existing S2MPS11 driver to support the clocks in S5M8767, rather than creating an almost duplicate driver altogether. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-19clk: add MOXA ART SoCs clock driverJonas Jensen3-0/+146
MOXA ART SoCs allow to determine PLL output and APB frequencies by reading registers holding multiplier and divisor information. Add a clock driver for this SoC. Signed-off-by: Jonas Jensen <jonas.jensen@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-14clk: mvebu: Update binding documentation for the core divider clockEzequiel Garcia1-1/+4
The Core Divider clock support two new compatible strings for Armada 375 and Armada 380 SoCs. Add the compatible strings to the documentation. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1394742273-5113-7-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-03-14clk: mvebu: Support Armada 380 SoC on the core divider clockEzequiel Garcia1-0/+23
This commit adds support for the Core Divider clocks of the Armada 380 SoCs. Similarly to Armada 370 and XP, the Core Divider clocks of the 380 have gate capabilities. The only difference is the register layout. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1394742273-5113-2-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-03-14clk: mvebu: Fix ratio register offset on A375 SoCEzequiel Garcia1-1/+1
This commit fixes the ratio register offset which is 0x4, as per the Armada 375 SoC specification. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1394638901-13368-2-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-02-27Merge branch 'clk-fixes' into clk-nextMike Turquette2-1/+4
2014-02-27clk: ti/divider: fix rate calculation for fractional ratesTomi Valkeinen1-4/+4
ti/clk-divider.c does not calculate the rates consistently at the moment. As an example, on OMAP3 we have a clock divider with a source clock of 864000000 Hz. With dividers 6, 7 and 8 the theoretical rates are: 6: 144000000 7: 123428571.428571... 8: 108000000 Calling clk_round_rate() with the rate in the first column will give the rate in the second column: 144000000 -> 144000000 143999999 -> 123428571 123428572 -> 123428571 123428571 -> 108000000 Note how clk_round_rate() returns 123428571 for rates from 123428572 to 143999999, which is mathematically correct, but when clk_round_rate() is called with 123428571, the returned value is surprisingly 108000000. This means that the following code works a bit oddly: rate = clk_round_rate(clk, 123428572); clk_set_rate(clk, rate); As clk_set_rate() also does clock rate rounding, the result is that the clock is set to the rate of 108000000, not 123428571 returned by the clk_round_rate. This patch changes the ti/clk-divider.c to use DIV_ROUND_UP when calculating the rate. This gives the following behavior which fixes the inconsistency: 144000000 -> 144000000 143999999 -> 123428572 123428572 -> 123428572 123428571 -> 108000000 Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-27clk: divider: fix rate calculation for fractional ratesTomi Valkeinen1-5/+5
clk-divider.c does not calculate the rates consistently at the moment. As an example, on OMAP3 we have a clock divider with a source clock of 864000000 Hz. With dividers 6, 7 and 8 the theoretical rates are: 6: 144000000 7: 123428571.428571... 8: 108000000 Calling clk_round_rate() with the rate in the first column will give the rate in the second column: 144000000 -> 144000000 143999999 -> 123428571 123428572 -> 123428571 123428571 -> 108000000 Note how clk_round_rate() returns 123428571 for rates from 123428572 to 143999999, which is mathematically correct, but when clk_round_rate() is called with 123428571, the returned value is surprisingly 108000000. This means that the following code works a bit oddly: rate = clk_round_rate(clk, 123428572); clk_set_rate(clk, rate); As clk_set_rate() also does clock rate rounding, the result is that the clock is set to the rate of 108000000, not 123428571 returned by the clk_round_rate. This patch changes the clk-divider.c to use DIV_ROUND_UP when calculating the rate. This gives the following behavior which fixes the inconsistency: 144000000 -> 144000000 143999999 -> 123428572 123428572 -> 123428572 123428571 -> 108000000 Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-27clk:at91: Fix memory leak in of_at91_clk_master_setup()Masanari Iida1-1/+1
cppcheck detected following error [clk-master.c:245]: (error) Memory leak: characteristics The original code forgot to free characteristics when irq_of_parse_and_map() failed. Signed-off-by: Masanari Iida <standby24x7@gmail.com> Acked-by Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-27clk: axi-clkgen: Add support for v2Lars-Peter Clausen2-44/+270
This patch adds support for the new v2 version of the axi-clkgen core. Unfortunately the method of accessing the registers is quite different on v2, while the content still stays largely the same. So the patch adds a small abstraction layer which implements the specific read and write functions for v1 and v2 in callback functions. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-02-27clk: hisilicon: add hi3620_mmc_clksZhangfei Gao4-0/+294
Suggest by Arnd: abstract mmc tuning as clock behavior, also because different soc have different tuning method and registers. hi3620_mmc_clks is added to handle mmc clock specifically on hi3620. Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-27clk: socfpga: Support multiple parents for the pll clocksDinh Nguyen1-4/+22
The PLLs can be from 3 different sources: osc1, osc2, or the f2s_ref_clk. Update the clock driver to be able to get the correct parent. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-27clk: socfpga: Fix integer overflow in clock calculationDinh Nguyen1-3/+5
Use 64-bit integer for calculating clock rate. Also use do_div for the 64-bit division. Signed-off-by: Graham Moore <grmoore@altera.com> Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-26clk: nomadik: fix multiplatform problemLinus Walleij1-0/+3
The Nomadik debugfs screws up multiplatform boots if debugfs is enabled on the multiplatform image, since it's a simple initcall that is unconditionally executed and reads from certain memory locations. Fix this by checking that the driver has been properly initialized, so a base offset to the Nomadik SRC controller exists, before proceeding to register debugfs files. Reported-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-26clk: zynq: Use clk_readl/clk_writel helper functionMichal Simek2-11/+11
Do not use readl/writel directly because the whole clk subsystem is using clk_readl/clk_writel functions. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-25clk: shmobile: div6: use proper description in kernel docWolfram Sang1-1/+1
These variable clocks have nothing to do with MSTP gating, probably a copy&paste leftover. Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-25Merge branch 'clk-fixes' into clk-nextMike Turquette391-2289/+3592
2014-02-25clk: ti: am335x: remove unecessary cpu0 clk nodeNishanth Menon1-1/+0
cpu0 clock node has no functionality, since cpufreq-cpu0 is already capable of picking up the clock from dts. Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-25Merge branch 'clocks/fixes/drivers' of git://linuxtv.org/pinchartl/fbdev ↵Mike Turquette375-2197/+3482
into clk-fixes
2014-02-25clk: Correct handling of NULL clk in __clk_{get, put}Sylwester Nawrocki1-6/+7
Ensure clk->kref is dereferenced only when clk is not NULL. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-25clk: return probe defer when DT clock not yet readyJean-Francois Moine2-1/+3
At probe time, a clock device may not be ready when some other device wants to use it. This patch lets the functions clk_get/devm_clk_get return a probe defer when the clock is defined in the DT but not yet available. Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-25clk: add pr_debug & kerneldoc around clk notifiersMike Turquette2-1/+18
Both the pr_err and the additional kerneldoc aim to help when debugging errors thrown from within a clock rate-change notifier callback. Reported-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-25Merge branch 'clk-tegra-more-fixes-3.14' of ↵Mike Turquette8-33/+47
git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-fixes Fixes stray access to undefined registers, use of wrong clock parents & running clocks at wrong rates. All of these issues cause regressions in the form of boards that are unable to boot or crash and die horrible deaths.
2014-02-24clk: shmobile: Fix typo in MSTP clock DT bindingsLaurent Pinchart1-2/+2
The DT bindings document a renesas,indices property, while the code, the DT example and the DT sources all use renesas,clock-indices. Fix the documentation. The shmobile mstp DT bindings have been merged in v3.14-rc1 with a bug in the DT ABI, a fix during the -rc series is appropriate. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Simon Horman <horms@verge.net.au>
2014-02-24clk: shmobile: rcar-gen2: Fix qspi divisorLaurent Pinchart1-1/+1
The qspi clock divisor is incorrectly set to twice the value it should have, possibly because it has been computed based on PLL1 as the clock parent instead of PLL1 / 2 (the datasheets specifies the qspi nominal frequencies, not the divisor values). Fix it. This bug introduced in v3.14-rc1 breaks various devices on the Lager and Kolesh shmobile boards and should thus be considered as a regression for which a fix during the -rc series is appropriate. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Simon Horman <horms+renesas@verge.net.au>
2014-02-24clk: shmobile: rcar-gen2: Fix clock parent for all non-PLL clocksLaurent Pinchart1-1/+9
The lb, qspi, sdh, sd0 and sd1 clocks have the PLL1 (divided by 2) as their parent, not the main clock. Fix it. This bug introduced in v3.14-rc1 breaks various devices on the Lager and Kolesh shmobile boards and should thus be considered as a regression for which a fix during the -rc series is appropriate. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Simon Horman <horms+renesas@verge.net.au>
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