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2020-11-30phy: amlogic: phy-meson-gxl-usb2: keep ID pull-up even in Host modeNeil Armstrong1-1/+2
In order to keep OTG ID detection even when in Host mode, the ID line of the PHY (if the current phy is an OTG one) pull-up should be kept enable in both modes. This fixes OTG switch on GXL, GXM & AXG platforms, otherwise once switched to Host, the ID detection doesn't work anymore to switch back to Device. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20201120153855.3920757-1-narmstrong@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-30phy: amlogic: meson-axg-mipi-pcie-analog: replace DSI_LANE definitions with ↵Neil Armstrong1-6/+5
BIT() macro For consistency, replace DSI_LANE definitions with BIT() macro and remove the unused DSI_LANE_MASK definition. Suggested-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20201120150347.3914901-1-narmstrong@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-30phy: samsung: Add support for the Exynos5420 variant of the USB2 PHYMarek Szyprowski5-15/+48
Exynos5420 differs a bit from Exynos5250 in USB2 PHY related registers in the PMU region. Add a variant for the Exynos5420 case. Till now, USB2 PHY worked only because the bootloader enabled the PHY, but then driver messed USB 3.0 DRD related registers during the suspend/resume cycle. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20201120085637.7299-2-m.szyprowski@samsung.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-30staging: mt7621-pci-phy: remove driver from stagingSergio Paracuellos7-426/+0
Remove this driver from staging because it has been moved into its properly place in the kernel. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Link: https://lore.kernel.org/r/20201121155037.21354-5-sergio.paracuellos@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-30MAINTAINERS: add MT7621 PHY PCI maintainerSergio Paracuellos1-0/+6
Adding myself as maintainer for mt7621 pci phy driver. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20201121155037.21354-4-sergio.paracuellos@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-30phy: ralink: Add PHY driver for MT7621 PCIe PHYSergio Paracuellos3-0/+361
This patch adds a driver for the PCIe PHY of MT7621 SoC. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20201121155037.21354-3-sergio.paracuellos@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-30dt-bindings: phy: Add binding for Mediatek MT7621 PCIe PHYSergio Paracuellos1-0/+36
Add bindings to describe Mediatek MT7621 PCIe PHY. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201121155037.21354-2-sergio.paracuellos@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-30phy: intel: Add Keem Bay USB PHY supportWan Ahmad Zainie3-0/+314
Add PHY driver for the USB3.1 and USB 2.0 PHYs found on Intel Keem Bay SoC. This driver takes care of enabling the required USB susbsystem (USS) clocks, initializing the PHYs and turning on/off the USB dwc3 core. Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20201116120831.32641-3-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-30dt-bindings: phy: Add Intel Keem Bay USB PHY bindingsWan Ahmad Zainie1-0/+44
Binding description for Intel Keem Bay USB PHY. Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201116120831.32641-2-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-20phy: samsung: phy-exynos-pcie: fix typo 'tunning'Vinod Koul1-1/+1
Fix the typo s/tunning/tuning Fixes: 496db029142f ("phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY") Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-20phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHYJaehoon Chung1-189/+112
Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM: dts: exynos: Remove Exynos5440"). Rework this driver to support PCIe PHY variant found in the Exynos5433 SoCs. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> [mszyprow: reworked the driver to support only Exynos5433 variant, rebased onto current kernel code, rewrote commit message] Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Jingoo Han <jingoohan1@gmail.com> Link: https://lore.kernel.org/r/20201120102627.14450-1-m.szyprowski@samsung.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-20dt-bindings: phy: phy-stm32-usbphyc: convert bindings to json-schemaAmelie Delaunay2-73/+138
Convert the STM32 USB PHY Controller (USBPHYC) bindings to DT schema format using json-schema. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201116171917.10447-1-amelie.delaunay@st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-20phy: amlogic: phy-meson-axg-mipi-pcie-analog: add support for MIPI DSI analogNeil Armstrong2-69/+136
The AXG Analog MIPI-DSI PHY also provides functions to the PCIe PHY, thus we need to have inclusive support for both interfaces at runtime. This fixes the regmap get from parent node, removes cell param to select a mode and implement runtime configuration & power on/off for both functions since they are not exclusive. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Remi Pommarel <repk@triplefau.lt> Link: https://lore.kernel.org/r/20201116101647.73448-4-narmstrong@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-20dt-bindings: phy: amlogic,meson-axg-mipi-pcie-analog: remove phy cell parameterNeil Armstrong1-2/+2
The Amlogic AXG MIPI + PCIe Analog PHY provides function for both PCIe and MIPI DSI at the same time, and is not exclusive. Thus remove the invalid phy cell parameter. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201116101647.73448-3-narmstrong@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-20phy: amlogic: Add AXG MIPI D-PHY driverNeil Armstrong3-0/+426
The Amlogic AXG SoCs embeds a MIPI D-PHY used to communicate with DSI panels. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20201116101315.71720-3-narmstrong@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-20dt-bindings: phy: amlogic,meson-axg-mipi-pcie-analog: remove reg attributeNeil Armstrong1-6/+11
The PHY registers happens to be at the beginning of a large zone containing interleaved system registers (mainly clocks, power management, PHY control..), found in all Amlogic SoC so far. The goal is to model it the same way as the other "features" of this zone, like Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt and Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml and have a coherent bindings scheme over the Amlogic SoCs. This update the description, removed the reg attribute then updates the example accordingly. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201116101647.73448-2-narmstrong@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-20dt-bindings: phy: add Amlogic AXG MIPI D-PHY bindingsNeil Armstrong1-0/+70
The Amlogic AXg SoCs embeds a MIPI D-PHY to communicate with DSI panels, this adds the bindings. This D-PHY depends on a separate analog PHY. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201116101315.71720-2-narmstrong@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-19phy: phy-bcm-ns-usb3: drop support for deprecated DT bindingRafał Miłecki1-151/+5
Initially this PHY driver was implementing MDIO access on its own. It was caused by lack of proper hardware design understanding. It has been changed back in 2017. DT bindings were changed and driver was updated to use MDIO layer. It should be really safe now to drop the old deprecated code. All Linux stored DT files don't use it for 3,5 year. There is close to 0 chance there is any bootloader with its own DTB using old the binding. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20201113113423.9466-1-zajec5@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-19phy: sun4i-usb: remove enable_pmu_unk1 from sun50i_h6_cfgYangtao Li1-1/+0
For the current code, enable_pmu_unk1 only works in non-a83t and non-h6 types. So let's delete it from the sun50i_h6_cfg. Signed-off-by: Yangtao Li <frank@allwinnertech.com> Link: https://lore.kernel.org/r/dc8cbb7b3cd59902a6719f207d18a232903fac8a.1604988979.git.frank@allwinnertech.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-17phy: amlogic: Revert "phy: amlogic: Replace devm_reset_control_array_get()"Vinod Koul4-4/+5
This reverts commit 3cc8e86721ad ("phy: amlogic: Replace devm_reset_control_array_get()") as it caused build failure drivers/soc/amlogic/meson-ee-pwrc.c: In function 'meson_ee_pwrc_init_domain': drivers/soc/amlogic/meson-ee-pwrc.c:416:65: error: expected ';' before 'if' Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: tegra: Don't warn on probe deferralJon Hunter1-1/+1
Deferred probe is an expected return value for devm_regulator_bulk_get(). Given that the driver deals with it properly, there's no need to output a warning that may potentially confuse users. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: JC Kuo <jckuo@nvidia.com> Link: https://lore.kernel.org/r/20201111103708.152566-1-jonathanh@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: phy-brcm-sata: Allow configuration SATA AFE TX amplitudeFlorian Fainelli1-0/+32
Read the 'brcm,tx-amplitude-millivolt' property from Device Tree and propagate its value into the appropriate test transmit register to change the TX amplitude. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20201022205056.233879-3-f.fainelli@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16dt-bindings: phy: Allow defining the SATA AFE TX amplitudeFlorian Fainelli1-0/+3
Document a new property which allows the selection of the SATA AFE TX amplitude in milli Volts. Possible values are 400, 500, 600 and 800mV. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20201022205056.233879-2-f.fainelli@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: stm32: defer probe for reset controllerAmelie Delaunay1-0/+4
Change stm32-usbphyc driver to defer its probe when the expected reset control has its probe operation deferred. Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Link: https://lore.kernel.org/r/20201110102305.27205-2-amelie.delaunay@st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: stm32: don't print an error on probe deferralAmelie Delaunay1-5/+2
Change stm32-usbphyc driver to not print an error message when the device probe operation is deferred. Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Link: https://lore.kernel.org/r/20201110130531.7610-1-amelie.delaunay@st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: tegra: Constify static device_type structsRikard Falkeborn1-2/+2
The only usage of tegra_xusb_pad_type and tegra_xusb_port_type is to assign their address to the type field in the device struct, which is a const pointer. Make them const to allow the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20201109215844.167954-1-rikard.falkeborn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: amlogic: Replace devm_reset_control_array_get()Yejune Deng4-5/+4
devm_reset_control_array_get_exclusive() looks more readable Signed-off-by: Yejune Deng <yejune.deng@gmail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/1604378274-6860-1-git-send-email-yejune.deng@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16dt-bindings: phy: Add Cadence Sierra PHY bindings in YAML formatSwapnil Jakhade2-70/+152
Add Cadence Sierra PHY bindings in YAML format. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1603898561-5142-1-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: ti: convert to devm_platform_ioremap_resource(_byname)Chunfeng Yun3-25/+11
Use devm_platform_ioremap_resource(_byname) to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1604642930-29019-17-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: tegra: convert to devm_platform_ioremap_resource(_byname)Chunfeng Yun2-6/+2
Use devm_platform_ioremap_resource(_byname) to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Cc: JC Kuo <jckuo@nvidia.com> Link: https://lore.kernel.org/r/1604642930-29019-16-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: phy-stm32-usbphyc: convert to devm_platform_ioremap_resourceChunfeng Yun1-3/+1
Use devm_platform_ioremap_resource to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Amelie Delaunay <amelie.delaunay@st.com> Link: https://lore.kernel.org/r/1604642930-29019-15-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: samsung: convert to devm_platform_ioremap_resourceChunfeng Yun4-15/+5
Use devm_platform_ioremap_resource to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/1604642930-29019-14-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: rockchip: convert to devm_platform_ioremap_resourceChunfeng Yun1-3/+1
Use devm_platform_ioremap_resource to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1604642930-29019-13-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: renesas: convert to devm_platform_ioremap_resourceChunfeng Yun4-12/+4
Use devm_platform_ioremap_resource to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1604642930-29019-12-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: phy-ralink-usb: convert to devm_platform_ioremap_resourceChunfeng Yun1-3/+1
Use devm_platform_ioremap_resource to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1604642930-29019-11-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: qualcomm: convert to devm_platform_ioremap_resource(_byname)Chunfeng Yun5-16/+5
Use devm_platform_ioremap_resource(_byname) to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1604642930-29019-10-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: phy-mtk-ufs: convert to devm_platform_ioremap_resourceChunfeng Yun1-3/+1
Use devm_platform_ioremap_resource to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1604642930-29019-9-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: phy-xgene: convert to devm_platform_ioremap_resourceChunfeng Yun1-3/+1
Use devm_platform_ioremap_resource to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1604642930-29019-8-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: marvell: convert to devm_platform_ioremap_resourceChunfeng Yun7-21/+7
Use devm_platform_ioremap_resource to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Link: https://lore.kernel.org/r/1604642930-29019-7-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: lantiq: convert to devm_platform_ioremap_resourceChunfeng Yun1-3/+1
Use devm_platform_ioremap_resource to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1604642930-29019-6-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: freescale: convert to devm_platform_ioremap_resourceChunfeng Yun2-6/+2
Use devm_platform_ioremap_resource to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Peter Chen <peter.chen@nxp.com> Link: https://lore.kernel.org/r/1604642930-29019-5-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: cadence: convert to devm_platform_ioremap_resourceChunfeng Yun3-9/+3
Use devm_platform_ioremap_resource to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Peter Chen <peter.chen@nxp.com> Link: https://lore.kernel.org/r/1604642930-29019-4-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: broadcom: convert to devm_platform_ioremap_resource(_byname)Chunfeng Yun8-36/+13
Use devm_platform_ioremap_resource(_byname) to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Cc: Al Cooper <alcooperx@gmail.com> Link: https://lore.kernel.org/r/1604642930-29019-3-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: amlogic: convert to devm_platform_ioremap_resourceChunfeng Yun4-12/+4
Use devm_platform_ioremap_resource to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Remi Pommarel <repk@triplefau.lt> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/1604642930-29019-2-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: allwinner: convert to devm_platform_ioremap_resource(_byname)Chunfeng Yun4-15/+5
Use devm_platform_ioremap_resource(_byname) to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1604642930-29019-1-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: qcom-qmp: Add SM8250 PCIe QMP PHYsManivannan Sadhasivam2-4/+295
SM8250 has multiple different PHY versions: QMP GEN3x1 PHY - 1 lane QMP GEN3x2 PHY - 2 lanes QMP Modem PHY - 2 lanes Add support for these with relevant init sequence. In order to abstract the init sequence, this commit introduces secondary tables which can be used to factor out the unique sequence for each PHY while the former tables can have the common sequence. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20201027170033.8475-3-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16dt-bindings: phy: qcom,qmp: Add SM8250 PCIe PHY bindingsManivannan Sadhasivam1-0/+6
Add the below three PCIe PHYs found in SM8250 to the QMP binding: QMP GEN3x1 PHY - 1 lane QMP GEN3x2 PHY - 2 lanes QMP Modem PHY - 2 lanes Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201027170033.8475-2-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-02phy: Add USB HSIC PHY driver for Marvell MMP3 SoCLubomir Rintel3-0/+95
Add PHY driver for the HSICs found on Marvell MMP3 SoC. The driver is rather straightforward -- the PHY essentially just needs to be enabled. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lore.kernel.org/r/20200925235828.228626-4-lkundrak@v3.sk Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-02dt-bindings: phy: Allow BSD licensing of marvell,mmp3-hsic-phy.yamlLubomir Rintel1-1/+1
I wrote this binding and I'm fine with it being GPL + BSD dual-licensed, as is recommended for new DT bindings. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200925235828.228626-3-lkundrak@v3.sk Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-02dt-bindings: phy: Drop reset-gpios from marvell,mmp3-hsic-phyLubomir Rintel1-7/+0
This has been added in error -- the PHY block doesn't have a reset pin. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200925235828.228626-2-lkundrak@v3.sk Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-02-03 03:40:21 +0300